VME02FPFPMXNOPB - National Semiconductor

TL/F/11658

VME02 Control Transceiver with Incident Wave Switching

PRELIMINARY

May 1994

VME02 Control Transceiver

with Incident Wave Switching

General Description

The VME02 is designed for two-way synchronous communi-

cations between data buses with minimal external timing

requirements.

The VME02 consists of three non-inverting bidirectional

buffers with TRI-STATEÉoutputs designed with incident

wave switching, live insertion support and enhanced noise

margin optimized for VME backplane applications. In addi-

tion the VME02 contains eight bidirectional buffers with

open collector driver with enhanced noise margin and live

insertion support.

CC bias pin provides for the precharging of the A side

outputs during live insertion. When set at 5.0V, this pin will

establish a voltage of 1.5V on the A port before VCC is

connected. This precharge will minimize the capacitive dis-

charge, and associated discontinuity, onto the active back-

plane during board insertion.

The B port includes a bus hold circuit to latch the output to

the value last forced on that pin.

The B port of this device includes 25Xseries output resis-

tors, which minimize undershoot and ringing.

Features

YSupports the VME64 ETL specification

YFunctionally and pin compatible with

TI SN74ABTE16246

YImproved TTL-compatible input threshold range

YEight outputs support VME open collector functions

YSupports 25Xincident wave switching on the A port

YVCC Bias pin minimizes signal distortion during live

insertion

YBiCMOS design significantly reduces power dissipation

YDistributed VCC and GND pin configuration minimizes

high-speed switching noise

Y25Xseries-dampening resistor on B-port

YAvailable in 48-pin SSOP and ceramic flatpak

YGuaranteed output skew

YGuaranteed simultaneous switching noise level and

dynamic threshold performance

YGuaranteed latchup protection

Pin Description

Pin Names Description

9DIR–11DIR Transmit/Receive Inputs

OE Output Enable Input (Active LOW)

1A–8A Backplane Bus Inputs or Open

Collector Outputs, with Live Insertion

9A–11A Backplane Bus Inputs or

TRI-STATE Outputs, with Live Insertion

1BI–8BI Local Bus Input Pins

1BO–8BO Local Bus Output Pins, with Bus Hold

9B–11B Local Bus Inputs, with Bus Hold or

TRI-STATE Outputs

VCC Bias Live Insertion Power Supply

Connection Diagram

Pin Assignment for

SSOP and Flatpak

TL/F/11658–1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Functional Description

The device uses Direction (DIR) control and Output Enable (OE) control. The DIR inputs determine the direction of data flow

through the device.

The part contains active circuitry which keeps all outputs disabled when VCC is less than 2.2V to aid in live insertion applications.

Truth Table

Inputs Operation

OE 9DIR 10DIR 11DIR 11OEA

H X X X X Isolation

L X X X X 1BI–8BI Data to 1A–8A Bus(*OC)

1A–8A Data to 1BO–8BO Bus

L L X X X 9A Data to 9B Bus

L H X X X 9B Data to 9A Bus

L X L X X 10A Data to 10B Bus

L X H X X 10B Data to 10A Bus

L X X L L 11A Data to 11B Bus

L X X L H 11A, 11B Isolation

L X X H X 11B Data to 11A Bus

Note: *OC eOpen Collector Outputs

Logic Diagram (Positive Logic)

TL/F/11658– 2

ETL’s Improved Noise Immunity

TTL input thresholds are typically determined by temperature-dependent junction voltages which result in worst case input

thresholds between 0.8V and 2.0V. By contrast, ETL provides greater noise immunity because its input thresholds are deter-

mined by current mode input circuits similar to those used for ECL or BTL. ETL’s worst case input thresholds, between 1.4V and

1.6V, are compensated for temperature, voltage and process variations.

Improved Input Threshold Characteristics of ETL

TL/F/11658– 11

TTL Worst Case VOUT–VIN

TL/F/11658– 12

ETL Worst Case VOUT–VIN

Incident Wave Switching

When TTL logic is used to drive fully loaded backplanes, the combination of low backplane bus characteristic impedance, wide

TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a valid signal can be

received across the backplane. The VME International Trade Association (VITA) defined ETL to provide incident wave switching

which increases the data transfer rate of a VME backplane and extends the life of VME applications. TTL compatibility with

existing VME backplanes and modules was maintained.

To demonstrate the incident wave switching capability, consider a VME application. A VME bus must be terminated to a2.94V

with 190Xat each end of its 21 card backplane. The surge impedance presented by a fully loaded VME backplane is approxi-

mately 25X. If the output voltage/current of an ABTC driver is plotted with this load, the intersection at 1.2V for a falling edge

and at 1.6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit. This is shown in the two

figures below. However, an ETL driver located at one end of the backplane is able to provide incident wave switching because it

has a higher drive and a tighter input threshold.

Estimated ETL/ABTC Initial Falling Edge Step

TL/F/11658– 3

Estimated ETL/ABTC Initial Rising Edge Step

TL/F/11658– 4

Because ETL has a much more precise input threshold region, an ETL receiver will interpret its predicted falling input of 0.85V as

a logic ZERO and the initial rising edge of 1.9V as a logic ONE. This comparison is for the case of a 25Xsurge impedance

backplane driven from one end.

Incident Wave Switching (Continued)

The resulting ABTC and ETL waveform predictions and their input thresholds are compared below. This shows how ETL can

achieve backplane speeds not always possible with conventional TTL compatible logic families.

Comparing the Incident Wave Switching of ETL with ABTC

TL/F/11658– 5

Live Insertion Module Replacement

To allow a system module to be replaced without disturbing

signals passing between other operating modules requires

careful design of operating systems, applications software

and hardware. ETL supports live insertion module replace-

ment with features that minimize backplane signal distur-

bance while a module is inserted. As specified by VITA, live

insertion requires several backward-compatible system en-

hancements including: an improved backplane connector

with an embedded ground plane and differential length con-

nector pins. The differential length connector pins allow

power sequencing to the module so that the signal pins can

be controlled to a biased high impedance before they make

contact with the backplane.

VITA’s ETL modules will use an early VCC power input,

called VCC Bias, to control the ETL transceivers to a high

impedance to minimize insertion disturbance. In addition,

VCC Bias is used to precharge the backplane driver output

capacitance including the module connector pin and mod-

ule etch. The precharge voltage is to 1.5V using a switched

40 kXresistor. This precharge will minimize the capacitive

discharge onto an active backplane as the signal connec-

tion is made. To allow designers to maintain this condition until

after a module is fully powered and initialized, the OE pin

can be used to maintain outputs in the high impedance,

precharged state. Contact bounce during live insertion will

charge each output pin to a logic ONE or ZERO. If the con-

tact bounces open, the 40 kXresistor will reestablish the

1.5V level in a few microseconds.

When applying power to a PCB containing ETL transceivers,

the system VCC can be connected to VCC Bias without dam-

age to the device.

If the advantages of Live Insertion are to be included in the

system, then VCC Bias should be allowed to reach normal

operating levels before VCC becomes higher than 2.2 volts.

In addition, when removing a module, or turning off system

power, VCC should be reduced below 2.2 volts before

VCC Bias is allowed to drop below normal operating limits.

This sequencing is shown below.

The figure VCC Power-up Critical Voltages shows the rela-

tionship between OE and VCC while power is being applied

and removed. This relationship holds if VCC Bias is within

normal operating conditions or if VCC Bias is equal to VCC.

TL/F/11658– 13

Power Sequencing to Achieve Live Insertion Precharging

TL/F/11658– 6

VCC and OE Power-Up Critical Relations

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias

Ceramic b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b50 mA to a5.0 mA

Voltage Applied to Any Output

in the Disabled or

Power-off State b0.5V to 5.5V

in the HIGH State b0.5V to VCC

Current Applied to Output

in LOW State (Max) 128 mA

DC Latchup Source Current b500 mA

Over Voltage Latchup (I/O) 10V

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial b40§Ctoa

85§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

Minimum Input Edge Rate (Dt/DV)

Data Input 20 ns/V

Enable Input 50 ns/V

DC Electrical Characteristics

Symbol Parameter VME02 Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage OE 2.0 VRecognized HIGH Signal

Other Inputs 1.6

VIL Input LOW Voltage OE 0.8 VRecognized LOW Signal

Other Inputs 1.4

VCD Input Clamp Diode Voltage b1.2 V Min IIN eb

18 mA (OEn, DIR)

VOH Output HIGH Voltage VCC b1V I

OH eb

100 mA

B Port 2.4 V Min IOH eb

1mA

2.0 V IOH eb

12 mA

VCC b1V I

OH eb

1mA

9A–11A 2.4 V Min IOH eb

32 mA

2.0 V IOH eb

60 mA

VOL Output LOW Voltage B Port 0.4 V Min IOL e1mA

0.8 V IOL e12 mA

A Port 0.55 V Min IOL e64 mA

0.9 V IOL e90 mA

IHOLD Bus Hold Current

B Port

100

mA Min

OE eHIGH,

VOe0.8V

b100 OE eHIGH,

VOe2.0V

ICC VCC Bias Supply Current VCC esVCC Bias

10 mA VCC Bias e0 to 5.5V

IOe0

IOFF Output Current, Power Down 100 mA 0.0 VCC Bias e0V

VIor VOs4.5V

IIInput Current Control Pins Military g10 mA 5.5 VIN e0orV

Commercial g5mA 5.5 VIN e0orV

IIH aOutput Leakage Current 9A–11A 50 mA 5.5 VOUT e2.7V, OE e2.0V

IOZH

IIL aOutput Leakage Current 9A–11A b50 mA 5.5 VOUT e0.5V, OE e2.0V

IOZL

DC Electrical Characteristics (Continued)

Symbol Parameter VME02 Units VCC Conditions

Min Typ Max

ICCH Power Supply Current 40 mA Max All Outputs HIGH,

OE eLOW, DIR eHIGH or LOW

ICCL Power Supply Current 80 mA Max All Outputs LOW,

OE eLOW, DIR eHIGH or LOW

ICCZ Power Supply Current

OE eHIGH

mA Max All Others at VCC or GND

DIR eHIGH or LOW

ICCD Dynamic ICC

0.15 MHz

mA/ Max

Outputs Open

No Load OEneGND, DIR eHIGH

(Note 1) One Bit Toggling, 50% Duty Cycle

VLI Output Live A Port 1.3 1.7 V 5.0 IOUT e0 mA, OE eHIGH

Insertion Voltage VCC Bias e5.0V

IPRE Precharge Current b20 b100 mA 5.0 OE eHIGH, VOe0V,

A-Port VCC Bias e5.0V

20 100 mA 5.0 VOe3V, VCC Bias e5.0V,

OE eHigh

VOLP Quiet Output Maximum 1.0 V 5.0 TAe25§C (Note 2)

Dynamic VOL CLe50 pF; RLe500X

VOLV Quiet Output Minimum b1.4 V 5.0 TAe25§C (Note 2)

Dynamic VOL CLe50 pF; RLe500X

VOHV Minimum High Level Dynamic 2.7 V 5.0 TAe25§C (Note 4)

Output Voltage (Note 1) CLe50 pF; RLe500X

VIHD Minimum High Level Dynamic 2.0 1.5 V 5.0 TAe25§C (Note 3)

Input Voltage (Note 1) CLe50 pF; RLe500X

VILD Maximum Low Level Dynamic 1.2 0.8 V 5.0 TAe25§C (Note 3)

Input Voltage (Note 1) CLe50 pF; RLe500X

Note 1: Guaranteed, but not tested.

Note 2: Max. number of outputs defined as (n). n b1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Note 3: Max. number of data inputs (n) switching. n b1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).

Guaranteed, but not tested.

Note 4: Max. number of outputs defined as (n). n b1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.

AC Electrical Characteristics

Symbol Parameter

Commercial Military Commercial

Units Fig.

No.

TAea

25§CT

55§Ctoa

125§CT

40§Ctoa

85§C

VCC ea

5V VCC e4.5V–5.5V VCC e4.5V–5.5V

Min Typ Max Min Max Min Max

tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 ns 1, 2, 4

tPHL Delay 9A–11A to 9B–11B 1.5 7.0 1.5 7.0 1.5 7.0

tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 ns 1, 2, 4

tPHL Delay 9B–11B to 9A–11A 1.5 7.0 1.5 7.0 1.5 7.0

tPHL Propagation Delay 7 7 7 ns 1,2,3

1BI–8BI to 1A–8A

tPLH Propagation Delay 15 15 15 ns 1, 2, 3

1BI–8BI to 1A–8A

tPZH Output Enable 1.0 7.0 1.0 7.0 1.0 7.0 ns 1, 2, 3

tPZL Time 9B–11B and 9A–11A 1.0 7.0 1.0 7.0 1.0 7.0

tPHZ Output Disable 1.0 7.0 1.0 7.0 1.0 7.0 ns 1, 2, 3

tPLZ Time 9B–11B and 9A–11A 1.0 7.0 1.0 7.0 1.0 7.0

trRise Time 1V

2V, 1.2 3.0 0.8 4.0 1.2 3.0 ns 1, 2, 4

9A–11A Outputs

tfFall Time 2V

1V, 1.2 3.0 0.8 4.0 1.2 3.0 ns 1, 2, 4

9A–11A Outputs

Skew

Symbol Parameter

Commercial Military

Units Conditions

TAeb

40§Ctoa

85§CT

55§Ctoa

125§C

VCC e4.5V–5.5V VCC e4.5V–5.5V

16 Outputs Switching 16 Outputs Switching

Max Max

tOHS Pin-to-Pin Skew 1.3 1.3 ns

Figures 1, 2, 4

(Notes 1, 2) LH/HL A-Port to B-Port

tOHS Pin-to-Pin Skew 1.3 1.3 ns

Figures 1, 2, 4

(Notes 1, 2) LH/HL B-Port to A-Port

tPS Duty Cycle Skew 2.0 2.0 ns

Figures 1, 2, 4

(Notes 1, 2) B-Port to A-Port

tPS Duty Cycle Skew 2.0 2.0 ns

Figures 1, 2, 4

(Notes 1, 2) A-Port to B-Port

VME Extended Skew

Symbol Parameter

Commercial Military

Units Conditions

TAeb

40§Ctoa

85§CT

55§Ctoa

125§C

VCC e4.5V–5.5V VCC e4.5V–5.5V

16 Outputs Switching 16 Outputs Switching

Max Max

tPV Device-to-Device Skew LH/HL 4.0 4.5 ns

Figures 1, 2, 4

(Notes 1, 2) Transitions 9B– 11B to 9A – 11A

tPV Device-to-Device Skew LH/HL 2.5 3.0 ns

Figures 1, 2, 4

(Notes 1, 2) Transitions 9A– 11A to 9B – 11B

tCP Change in Propagation Delay 4.0 4.5 ns

Figures 1, 2, 4

(Note 3) with Load 9B–11B to 9A–11A

tCPV Device-to-Device, Change

(Notes 1, 2, 3) in Propagation Delay with 6.0 7.0 ns

Figures 1, 2, 4

Load 9B–11B to 9A–11A

Note 1: Skew is defined as the absolute difference in delay between two outputs. The specification applies to any outputs switching HIGH to LOW, LOW to HIGH,

or any combination switching HIGH-to-LOW or LOW-to-HIGH. This specification is guaranteed but not tested.

Note 2: This is measured with both devices at the same value of VCC g1% and with package temperature differences of 20§C from each other.

Note 3: This is measured with Rx in

Figure 1

at 13Xfor one unit and at 56Xfor the other unit.

Capacitance

Symbol Parameter Typ Max Units Conditions, TAe25§C

CIN Input Capacitance 5 8 pF VCC e0.0V (OEn, DIR)

CI/O (Note 1) Output Capacitance 9 12 pF VCC e5.0V (An)

Note 1: CI/O is measured at frequency f e1 MHz, per MIL-STD-883B, Method 3012.

AC Loading

TL/F/11658– 7

*Includes jig and probe capacitance

FIGURE 1. Standard AC Test Load

Note 1: Defined to emulate the range of VME bus transmission line loading

as a function of board population and driver location. Rx e13X,26Xor

56Xdepending on test.

Test Port SW1 SW2 Rx

tPHZ,t

PZH 9A–11A, B Open Open

tPLZ,t

PZL 9A–11A, B a7 Open

tPHL/tPLH 1A–8A a7 Open

tPLH/tPHL 9A–11A Open Closed 26

tPLH/tPHL B Open Open

tr,t

f9A–11A Open Closed 26

tPV 9A–11A Open Closed 26

tPV B Open Open

tCP 9A–11A Open Closed 13 then 56

tCPV 9A–11A Open Closed 13 and 56

FIGURE 1a

TL/F/11658– 8

FIGURE 2. Input Pulse Requirements

Amplitude Rep. Rate tWtrtf

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

FIGURE 2a. Test Input Signal Requirements

TL/F/11658– 9

FIGURE 3. TRI-STATE Output HIGH

and LOW Enable and Disable Times

TL/F/11658– 10

FIGURE 4. Rise, Fall Time and Propagation Delay Waveforms

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

VME02 SS C X

Device Type Special Variations

XeDevices shipped in 13×reels

Package Code QB eMilitary grade device with

SS eSmall Outline (SSOP) environmental and burn-in

FPFP eFine Pitch Flatpak processing shipped in tubes.

Temperature Range

CeCommercial (b40§Ctoa

85§C)

MeMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

48-Lead SSOP (0.300×Wide) (SS)

NS Package Number MS48A

VME02 Control Transceiver with Incident Wave Switching

Physical Dimensions inches (millimeters) (Continued)

48-Pin Ceramic Flatpak (FPFP)

NS Package Number WA48A

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SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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