P0012-02
DRBPackage
(TopView)
1
2
3
45
6
7
8OUT
VDD
CD
VC4
VC1
VC2
VC3
GND
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries
(Second-Level Protection)
Check for Samples: bq29440,bq2944L0,bq29441,bq29442,bq29443,bq29449,bq2944L9
1FEATURES APPLICATIONS
• Second-Level Protection in Li-Ion Battery
• 2-Series, 3-Series, or 4-Series Cell Secondary Packs
Protection – Notebook Computers
• External Capacitor-Controlled Delay Timer – Power Tools
• Low Power Consumption ICC < 2 µA Typical – Portable Equipment and Instrumentation
[VCELL(ALL) < VPROTECT]
• High-Accuracy Overvoltage Protection: ±25
mV with TA= 0°C to 60°C
• Fixed Overvoltage Protection Thresholds:
4.30 V, 4.35 V, 4.40 V, 4.45 V, 4.50 V
• Small 8L QFN Package
DESCRIPTION
The bq2944x is a secondary overvoltage protection IC for 2-series, 3-series, or 4-series cell Li-Ion battery packs
that incorporates a high-accuracy precision overvoltage detection circuit.
FUNCTION
The voltage of each cell in a battery pack is compared to an internal reference voltage. If any cells reach an
overvoltage condition, the bq2944x device starts a timer that provides a delay proportional to the capacitance on
the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low state to a high state. An
optional latch configuration is available that holds the OUT pin in a high state indefinitely after an overvoltage
condition has satisfied the specified delay timer period. The latch is released when the CD pin is shorted to GND.
T
T
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
ORDERING INFORMATION(2)
OUT PIN
PART PACKAGE PACKAGE
TALATCH PACKAGE OVP TAPE AND REEL TAPE AND REEL
NUMBER DESIGNATOR MARKING
OPTION (LARGE)(3) (SMALL)(4)
BQ29440 No 440 4.35 V BQ29440DRBR BQ29440DRBT
BQ2944L0 Yes 44L0 4.35 V BQ2944L0DRBR BQ2944L0DRBT
BQ29441 No 441 4.40 V BQ29441DRBR BQ29441DRBT
–40°C
to BQ29442 No QFN-8 DRB 442 4.45 V BQ29442DRBR BQ29442DRBT
+110°C BQ29443 No 443 4.50 V BQ29443DRBR BQ29443DRBT
BQ29449 No 449 4.30 V BQ29449DRBR BQ29449DRBT
BQ2944L9 Yes 44L9 4.30 V BQ2944L9DRBR BQ2944L9DRBT
(1) Example: bq2944L0DRBR is a device with the OUT latch option with a VOV threshold of 4.35 V.
Contact Texas Instruments for other VOV threshold options.
(2) For the most current package and ordering information, see the Package Addendum at the end of this document, or the TI website at
www.ti.com.
(3) Large tape and reel quantity is 3,000 units.
(4) Small tape and reel quantity is 250 units.
THERMAL INFORMATION bq2944x
THERMAL METRIC(1) DRB UNITS
8 PINS
qJA Junction-to-ambient thermal resistance(2) 50.5
qJC(top) Junction-to-case(top) thermal resistance(3) 25.1
qJB Junction-to-board thermal resistance(4) 19.3 °C/W
yJT Junction-to-top characterization parameter(5) 0.7
yJB Junction-to-board characterization parameter(6) 18.9
qJC(bottom) Junction-to-case(bottom) thermal resistance(7) 5.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN FUNCTIONS
PIN NAME PIN NO. DESCRIPTION
CD 6 Connection to external capacitor for programmable delay time
GND 4 Ground pin
OUT 8 Output
VC1 1 Sense voltage input for top cell
VC2 2 Sense voltage input for second-to-top cell
VC3 3 Sense voltage input for third-to-top cell
VC4 5 Sense voltage input for fourth-to-top cell (bottom cell)
VDD 7 Power supply
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Product Folder Link(s): bq29440 bq2944L0 bq29441 bq29442 bq29443 bq29449 bq2944L9
OUT
VC1
VC2
VC3
VC4
GND
VDD
CD
RIN
RIN
RIN
RIN
CIN
CIN
CIN
CIN
RVD
CVD
CCD
B0394-01
ICD
VCD
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE/UNIT
Supply voltage range, VMAX VDD–GND –0.3 to 28 V
VC1–GND, VC2–GND, VC3–GND –0.3 to 28 V
Input voltage range, VIN VC1–VC2, VC2–VC3, VC3–VC4, VC4–GND –0.3 to 8 V
CD–GND –0.3 to 8 V
Output voltage range, VOUT OUT–GND –0.3 to 28 V
Storage temperature range, Tstg –65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VDD 4 25 V
Input voltage range VC1–VC2, VC2–VC3, VC3–VC4, VC4–GND 0 5 V
td(CD) delay-time capacitance CCD (See Figure 7.) 0.1 µF
Voltage monitor filter resistance RIN (See Figure 7.) 0.1 1 kΩ
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): bq29440 bq2944L0 bq29441 bq29442 bq29443 bq29449 bq2944L9
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT
Voltage monitor filter capacitance CIN (See Figure 7.) 0.01 0.1 µF
Supply voltage filter resistance RVD (See Figure 7.) 0.1 1 kΩ
Supply voltage filter capacitance CVD (See Figure 7.) 0.1 µF
Operating ambient temperature range, TA–40 110 °C
ELECTRICAL CHARACTERISTICS
Typical values stated where TA= 25°C and VDD = 17 V, MIN/MAX values stated where TA= –40°C to 110°C and VDD = 4 V
to 25 V (unless otherwise noted).
PARAMETER TEST CONDITION MIN NOM MAX UNIT
bq29440 4.35
bq29441 4.40
Overvoltage
VPROTECT detection bq29442 4.45 V
voltage bq29443 4.50
bq29449 4.30
Overvoltage detection
VHYS For non-latch devices only 200 300 400 mV
hysteresis
Overvoltage detection
VOA TA= 25°C –10 10 mV
accuracy TA= 0°C to 60°C –0.4 0.4
Overvoltage threshold
VOA_DRIFT mV/°C
temperature drift TA= –40°C to 110°C –0.6 0.6
TA= 0°C to 60°C 6.0 9.0 12
Note: Does not include external capacitor variation
Overvoltage delay time
XDELAY s/µF
scale factor TA= –40°C to 110°C 5.5 9.0 13.5
Note: Does not include external capacitor variation
Overvoltage delay time
XDELAY_CTM scale factor in See CUSTOMER TEST MODE. 0.08 s/µF
Customer Test Mode
Overvoltage detection
ICD(CHG) See Figure 1. 140 nA
charging current
Overvoltage detection
ICD(DSG) See Figure 2. 60 µA
discharging current
Overvoltage detection
VCD external capacitor 1.2 V
comparator threshold (VC1–VC2), (VC2–VC3), (VC3–VC4) and (VC4–GND) =
3.5 V
ICC Supply current 2 3.5 µA
See Figure 3.
(VC1–VC2), (VC2–VC3), (VC3–VC4) or
(VC4–GND) = VPROTECT, VDD = 20 V, 6.5 8.0 9.5 V
IOH = 0 to –10 µA
(VC1–VC2), (VC2–VC3), (VC3–VC4) or
(VC4–GND) = VPROTECT, VDD = 4.35 V, 1.50 3.0 V
IOL = –10 µA, TA= 0°C to 60°C
VOUT OUT pin drive voltage (VC1–VC2), (VC2–VC3), (VC3–VC4) or
(VC4–GND) = VPROTECT, VDD > 6 V, 2.0 3.0 V
IOH = –10 µA, TA= 0°C to 60°C
(VC1–VC2), (VC2–VC3), (VC3–VC4) or 0.1 V
(VC4–GND) = 4 V, IOL = 0 µA
OUT short circuit OUT = 0 V, (VC1–VC2), (VC2–VC3), (VC3–VC4) or
IOUT(SHORT) 4 mA
current (VC4–GND) > VPROTECT, VDD = 18 V
tr(OUT)(1) OUT output rise time CL= 1 nF, VDD = 4 V to 25 V, VOH(OUT) = 0 V to 5 V 5 µs
ZO(OUT)(1) OUT output impedance 2 kΩ
(1) Specified by design. Not 100% tested in production.
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Temperature (°C)
ICD Charge Current (nA)
ICD CHARGE CURRENT
vs
TEMPERATURE
-40 -20 0 20 40 60 80 100
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
G001
Temperature (°C)
ICD Discharge Current (µA)
ICD DISCHARGE CURRENT
vs
TEMPERATURE
40
45
50
55
60
65
70
75
80
-40 -20 0 20 40 60 80 100
G002
1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
ICC
IIN
IIN
IIN
IIN
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA= 25°C and VDD = 17 V, MIN/MAX values stated where TA= –40°C to 110°C and VDD = 4 V
to 25 V (unless otherwise noted).
PARAMETER TEST CONDITION MIN NOM MAX UNIT
Measured at VC1, (VC1–VC2), (VC2–VC3), (VC3–VC4) and
(VC4–GND) = 3.5 V, TA= 0°C to 60°C –0.3 1.5 µA
See Figure 3.
Input current at VCx
IIN pins Measured at VC2, VC3 OR VC4, (VC1–VC2), (VC2–VC3),
(VC3–VC4) and (VC4–GND) = 3.5 V, TA= 0°C to 60°C –0.3 0.3 µA
See Figure 3.
TYPICAL CHARACTERISTICS
Figure 1. ICD Charge Current Figure 2. ICD Discharge Current
Figure 3. ICC, IIN Measurement
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): bq29440 bq2944L0 bq29441 bq29442 bq29443 bq29449 bq2944L9
OUT L H
VPROTECT
V –
PROTECT VHYS
Cell Voltage
VC1–VC2
VC2–VC3
VC3–VC4
VC4–GND
T0461-01
td
d
CD
DELAY
t
C
X
=
CD DELAY
d
t C X´=
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
www.ti.com
APPLICATIONS INFORMATION
PROTECTION (OUT) TIMING AND DELAY TIME CAPACITOR SIZING
The bq2944x uses an external capacitor to set delay timing during an overvoltage condition. When any of the
cells exceed the overvoltage threshold, the bq2944x activates an internal current source of nominally 140 nA,
which charges the external capacitor. When the external capacitor charges up to a voltage of nominally 1.2 V,
the OUT pin transitions from a low state to a high state, by means of an internal pull-up network, to a regulated
voltage of no more than 9.5 V when IOH = 0 mA.
Figure 4. Timing for Overvoltage Sensing
Sizing the external capacitor is based on the desired delay time as follows:
Where tdis the desired delay time and xDELAY is the overvoltage delay time scale factor, expressed in seconds
per microFarad. xDELAY is nominally 9.0 s/µF. For example, if a nominal delay of 3 seconds is desired, the
customer should use a CCD capacitor that is 3 s/9.0 s/µF = 0.33 µF.
The delay time is calculated as follows:
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
For latched versions of the bq2944x, if an overvoltage condition has caused the OUT pin to transition to a high
state, the external capacitor remains charged even after the overvoltage condition has been removed. In this
instance, the OUT pin remains in a high state.
For non-latched versions, the OUT pin is allowed to transition back from a high to low state when the overvoltage
condition is no longer present, and the external capacitor is discharged down to 0 V.
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1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
RVD
RIN
RIN
RIN
CIN
CIN
CIN
CVD
CCD
1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
RVD
RIN
RIN
RIN
RIN
CIN
CIN
CIN
CIN
CVD
CCD
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
BATTERY CONNECTION FOR 2-SERIES, 3-SERIES, AND 4-SERIES CELL CONFIGURATIONS
Figure 5,Figure 6, and Figure 7 show the 2-series, 3-series, and 4-series cell configurations.
Figure 5. 2-Series Cell Configuration
Figure 6. 3-Series Cell Configuration
Figure 7. 4-Series Cell Configuration
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): bq29440 bq2944L0 bq29441 bq29442 bq29443 bq29449 bq2944L9
d _ CTM CD DELAY_CTM
t C X= ´
bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
www.ti.com
CELL CONNECTION SEQUENCE
NOTE
Before connecting the cells, propagate the overvoltage delay timing capacitor, CCD.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC4
3. VC3
4. VC2
5. VC1
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC4, VC3, VC2, or VC1
3. Remaining VCx pin
4. Remaining VCx pin
5. Remaining VCx pin
CUSTOMER TEST MODE
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC1. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, xDELAY, to a significantly reduced factor, xDELAY_CTM,
thereby reducing the delay time during an overvoltage condition. The CTM overvoltage delay time is similar to
the equation presented in PROTECTION (OUT) TIMING AND DELAY TIME CAPACITOR SIZING with the
substitution of xDELAY_CTM in place of xDELAY:
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also, avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (VC1–VC2), (VC2–VC3), (VC3–VC4), and (VC4–GND).
Stressing the pins beyond the rated limits may cause permanent damage to the
device.
To exit CTM, power off the device and then power it back on.
For latched versions of the bq2944x, the external CCD capacitor must be externally discharged if any overvoltage
functionality is exercised during protection testing. This can be accomplished by shorting the CD pin to GND. If
the CCD capacitor is not explicitly discharged, a residual charge may cause the overvoltage delay time to be
inaccurate.
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bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C –JUNE 2010–REVISED NOVEMBER 2010
REVISION HISTORY
Changes from Revision B (June 2010) to Revision C Page
• Added new protection thresholds ......................................................................................................................................... 1
• Changed occurrences of VDD to VDD throughout document ................................................................................................ 1
• Added part numbers ............................................................................................................................................................. 2
• Changed the Functional Block Diagram ............................................................................................................................... 3
• Changed the Electrical Characteristics ................................................................................................................................. 4
• Deleted 3.5 from one of the maximum values from the VOUT specification .......................................................................... 4
• Changed nominal delay time ................................................................................................................................................ 6
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ29440DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29440DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29441DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29441DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29442DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29442DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29443DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29443DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29449DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29449DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jun-2012
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ29440DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29440DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29441DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29441DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29442DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29442DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29443DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29443DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29449DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29449DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29440DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29440DRBT SON DRB 8 250 210.0 185.0 35.0
BQ29441DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29441DRBT SON DRB 8 250 210.0 185.0 35.0
BQ29442DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29442DRBT SON DRB 8 250 210.0 185.0 35.0
BQ29443DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29443DRBT SON DRB 8 250 210.0 185.0 35.0
BQ29449DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29449DRBT SON DRB 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2012
Pack Materials-Page 2
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