CS5364-DQZR - Cirrus Logic - Datasheet.Directory

http://www.cirrus.com

114 dB, 192 kHz, 4-Channel A/D Converter

Features

Advanced Multi-bit Delta-Sigma Architecture

24-Bit Conversion

114 dB Dynamic Range

-105 dB THD+N

Supports Audio Sample Rates up to 216 kHz

Selectable Audio Interface Formats

– Left-Justified, I²S, TDM

– 4-Channel TDM Interface Formats

Low Latency Digital Filter

Less than 365 mW Power Consumption

On-Chip Oscillator Driver

Operation as System Clock Master or Slave

Auto-Detect Speed in Slave Mode

Differential Analog Architecture

Separate 1.8 V to 5 V Logic Supplies for

Control and Serial Ports

High-Pass Filter for DC Offset Calibration

Overflow Detection

Footprint Compatible with the 8-Channel

CS5368

Additional Control Port Features

Supports I²C or SPI™ Control Interface per

specifications on page 17 and page 18

Individual Channel HPF Disable

Overflow Detection for Individual Channels

Mute Control for Individual Channels

Independent Power-Down Control per Channel

Pair

Digital

Audio

Voltage

Reference

Level

Translator

Level

Translator

Internal

Oscillator

3.3 - 5V

Control Interface

I2C, SPI

or Pins

Configuration

Registers

VLC

1.8 - 5V

VLS

1.8 - 5V

4 Differential

Analog Inputs

Device

Control

Serial

Audio Out

PCM or

TDM

Decimation

Filter

High Pass

Filter

Multi-bit

 ADC

CS5364

JUL '14

DS625F5

2DS625F5

CS5364

Description

The CS5364 is a complete 4-channel analog-to-digital converter for digital audio systems. It performs sampling, an-

alog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 4-channel inputs in serial form at

sample rates up to 216 kHz per channel.

The CS5364 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decima-

tion, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which

provides excellent noise rejection.

Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5364 and

other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking

flexibility and simplifies design.

The CS5364 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output

of 4 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout

complexity and relieves input/output constraints in digital signal processors.

The CS5364 is available in a 48-pin LQFP package in both Commercial (-40°C to 85°C) and Automotive grades

(-40°C to +105°C). The CDB5364 Customer Demonstration board is also available for device evaluation and

implementation suggestions. Please see “Ordering Information” on page 41 for complete ordering information.

The CS5364 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion,

wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record-

ers, outboard converters, digital effect processors, and automotive audio systems.

DS625F5 3

CS5364

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 6

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9

3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 10

RECOMMENDED OPERATING CONDITIONS ................................................................................. 10

ABSOLUTE RATINGS ....................................................................................................................... 10

SYSTEM CLOCKING ......................................................................................................................... 10

DC POWER ........................................................................................................................................ 11

LOGIC LEVELS ................................................................................................................................. 11

PSRR, VQ AND FILT+ CHARACTERISTICS .................................................................................... 11

ANALOG CHARACTERISTICS (COMMERCIAL) .............................................................................. 12

ANALOG PERFORMANCE (AUTOMOTIVE) ..................................................................................... 13

DIGITAL FILTER CHARACTERISTICS ............................................................................................. 14

OVERFLOW TIMEOUT ...................................................................................................................... 14

SERIAL AUDIO INTERFACE - I²S/LJ TIMING ................................................................................... 15

SERIAL AUDIO INTERFACE - TDM TIMING ..................................................................................... 16

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING ................................................... 17

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING .................................................. 18

4. APPLICATIONS ................................................................................................................................... 19

4.1 Power ............................................................................................................................................. 19

4.2 Control Port Mode and Stand-Alone Operation .............................................................................. 19

4.2.1 Stand-Alone Mode ................................................................................................................. 19

4.2.2 Control Port Mode ................................................................................................................. 19

4.3 Master Clock Source ...................................................................................................................... 20

4.3.1 On-Chip Crystal Oscillator Driver .......................................................................................... 20

4.3.2 Externally Generated Master Clock ....................................................................................... 20

4.4 Master and Slave Operation ........................................................................................................... 21

4.4.1 Synchronization of Multiple Devices ......................................................................................21

4.5 Serial Audio Interface (SAI) Format ................................................................................................ 22

4.5.1 I²S and LJ Format .................................................................................................................. 22

4.5.2 TDM Format .......................................................................................................................... 23

4.5.3 Configuring Serial Audio Interface Format ............................................................................ 23

4.6 Speed Modes ................................................................................................................................. 23

4.6.1 Sample Rate Ranges ............................................................................................................ 23

4.6.2 Using M1 and M0 to Set Sampling Parameters .................................................................... 23

4.6.3 Master Mode Clock Dividers ................................................................................................. 24

4.6.4 Slave Mode Audio Clocking With Auto-Detect ...................................................................... 24

4.7 Master and Slave Clock Frequencies ............................................................................................. 25

4.8 Reset .............................................................................................................................................. 27

4.8.1 Power-Down Mode ................................................................................................................ 27

4.9 Overflow Detection ......................................................................................................................... 27

4.9.1 Overflow in Stand-Alone Mode .............................................................................................. 27

4.9.2 Overflow in Control Port Mode .............................................................................................. 27

4.10 Analog Connections ..................................................................................................................... 28

4.11 Optimizing Performance in TDM Mode ........................................................................................29

4.12 DC Offset Control ......................................................................................................................... 29

4.13 Control Port Operation .................................................................................................................. 30

4.13.1 SPI Mode ............................................................................................................................. 30

4.13.2 I²C Mode .............................................................................................................................. 31

5. REGISTER MAP ................................................................................................................................... 32

5.1 Register Quick Reference ............................................................................................................. 32

5.2 00h (REVI) Chip ID Code & Revision Register ............................................................................... 32

4DS625F5

CS5364

5.3 01h (GCTL) Global Mode Control Register ...................................................................................32

5.4 02h (OVFL) Overflow Status Register ........................................................................................... 33

5.5 03h (OVFM) Overflow Mask Register ............................................................................................ 33

5.6 04h (HPF) High-Pass Filter Register ............................................................................................. 34

5.7 05h Reserved ................................................................................................................................ 34

5.8 06h (PDN) Power Down Register .................................................................................................. 34

5.9 07h Reserved ................................................................................................................................ 34

5.10 08h (MUTE) Mute Control Register .............................................................................................. 34

5.11 09h Reserved .............................................................................................................................. 35

5.12 0Ah (SDEN) SDOUT Enable Control Register ............................................................................ 35

6. FILTER PLOTS ..................................................................................................................................... 36

7. PARAMETER DEFINITIONS ................................................................................................................ 39

8. PACKAGE DIMENSIONS ................................................................................................................... 40

THERMAL CHARACTERISTICS .......................................................................................................40

9. ORDERING INFORMATION ................................................................................................................ 41

10. REVISION HISTORY ......................................................................................................................... 41

LIST OF FIGURES

Figure 1. CS5364 Pinout ............................................................................................................................. 6

Figure 2. Typical Connection Diagram ........................................................................................................ 9

Figure 3. I²S/LJ Timing .............................................................................................................................. 15

Figure 4. TDM Timing ............................................................................................................................... 16

Figure 5. I²C Timing .................................................................................................................................. 17

Figure 6. SPI Timing ................................................................................................................................. 18

Figure 7. Crystal Oscillator Topology ........................................................................................................ 20

Figure 8. Master/Slave Clock Flow ........................................................................................................... 21

Figure 9. Master and Slave Clocking for a Multi-Channel Application ...................................................... 21

Figure 10. I²S Format ................................................................................................................................ 22

Figure 11. LJ Format ................................................................................................................................. 22

Figure 12. TDM Format ............................................................................................................................. 23

Figure 13. Master Mode Clock Dividers .................................................................................................... 24

Figure 14. Slave Mode Auto-Detect Speed ............................................................................................... 24

Figure 15. Recommended Analog Input Buffer ......................................................................................... 28

Figure 16. SPI Format ............................................................................................................................... 30

Figure 17. I²C Write Format ...................................................................................................................... 31

Figure 18. I²C Read Format ...................................................................................................................... 31

Figure 19. SSM Passband ........................................................................................................................ 36

Figure 20. DSM Passband ........................................................................................................................ 36

Figure 21. QSM Passband ........................................................................................................................ 36

Figure 22. SSM Stopband ......................................................................................................................... 37

Figure 23. DSM Stopband ......................................................................................................................... 37

Figure 24. QSM Stopband ........................................................................................................................ 37

Figure 25. SSM -1 dB Cutoff ..................................................................................................................... 38

Figure 26. DSM -1 dB Cutoff .................................................................................................................... 38

Figure 27. QSM -1 dB Cutoff ..................................................................................................................... 38

DS625F5 5

CS5364

LIST OF TABLES

Table 1. Power Supply Pin Definitions ...................................................................................................... 19

Table 2. DIF1 and DIF0 Pin Settings ........................................................................................................ 23

Table 3. M1 and M0 Settings .................................................................................................................... 23

Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S ..................................................................... 25

Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S ..................................................................... 25

Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S ................................................................... 25

Table 7. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25

Table 8. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25

Table 9. Frequencies for 96 kHz Sample Rate using TDM ....................................................................... 26

Table 10. Frequencies for 96 kHz Sample Rate using TDM ..................................................................... 26

Table 11. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26

Table 12. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26

6DS625F5

CS5364

1. PIN DESCRIPTION

Figure 1. CS5364 Pinout

DIF1/AD1/CDIN

REF_GND

AIN3+

SDOUT1/TDM

VLS

TSTO

GND

SDOUT2

M0/SDA/CDOUT

AIN1+

AIN3-

GND

XTI

GND

VLC

DIF0/AD0/CS

AIN1-

M1/SCL/CCLK

LRCK/FS

SCLK

MCLK

XTO

OVFL

CLKMODE

MDIV

RST

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

CS5364

FILT+

AIN2-

GND

AIN2+

GND

AIN4+

AIN4-

GND

TDM

DS625F5 7

CS5364

Pin Name Pin # Pin Description

AIN2+, AIN2-

AIN4+, AIN4-

AIN3+, AIN3-

AIN1+, AIN1-

1,2

11,12

13,14

47,48

Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula-

tors via the AIN+/- pins.

GND

3,8

10,15

16,17

18,19

29,32

43,44

45,46

Ground (Input) - Ground reference. Must be connected to analog ground.

VA 4,9 Analog Power (Input) - Positive power supply for the analog section.

REF_GND 5 Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog

ground.

FILT+ 6 Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits.

VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

VX 20 Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir-

cuits.

XTI

XTO

Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be

used to generate MCLK.

MCLK 23

System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK

Source (Output). When the oscillator function is not used, this pin acts as an input for the system

master clock. In this case, the XTI and XTO pins must be tied low.

LRCK/FS 24

Serial Audio Channel Clock (Input/Output)

In I²S mode, Serial Audio Channel Select. When low, the odd channels are selected.

In LJ mode, Serial Audio Channel Select. When high, the odd channels are selected.

In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial

audio samples. In Slave Mode, this pin acts as an input pin.

SCLK 25 Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin

acts as an output, and during Slave Mode it acts as an input pin.

TSTO 26 Test Out (Output) - Must be left unconnected.

SDOUT2 27 Serial Audio Data (Output) - Channels 3,4.

VLS 28 Serial Audio Interface Power - Positive power for the serial audio interface.

SDOUT1/TDM 30 Serial Audio Data (Output) - Channels 1,2.

TDM 31 TDM - TDM is complementary TDM data.

VD 33 Digital Power (Input) - Positive power supply for the digital section.

VLC 35 Control Port Interface Power - Positive power for the control port interface.

OVFL 36 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.

RST 41 Reset (Input) - The device enters a low power mode when low.

8DS625F5

CS5364

Stand-Alone Mode

CLKMODE 34 CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the

core device circuitry.

DIF1

DIF0

38 DIF1, DIF0 (Input) - Sets the serial audio interface format.

40 Mode Selection (Input) - Determines the operational mode of the device.

MDIV 42 MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the

core device circuitry.

Control Port Mode

CLKMODE 34

CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is

obtained from the corresponding bit in the Global Control Register. Note: Should be connected

to GND when using the part in Control Port Mode.

AD1/CDIN 37 I²C Format, AD1 (Input) - Forms the device address input AD[1].

SPI Format, CDIN (Input) - Becomes the input data pin.

AD0/CS 38 I²C Format, AD0 (Input) - Forms the device address input AD[0].

SPI Format, CS (Input) - Acts as the active low chip select input.

SCL/CCLK 39

I²C Format, SCL (Input) – Serial clock for the serial control port. An external pull-up resistor is

required for I²C control port operation.

SPI Format, CCLK (Input) – Serial clock for the serial control port.

SDA/CDOUT 40

I²C Format SDA (Input/Output) - Acts as an input/output data pin. An external pull-up resistor is

required for I²C control port operation.

SPI Format CDOUT (Output) - Acts as an output only data pin.

MDIV 42

MCLK Divider (Input) - This pin is ignored in Control Port Mode, and the same functionality is

obtained from the corresponding bit in the Global Control Register.

Note: Should be connected to GND when using the part in Control Port Mode.

DS625F5 9

CS5364

2. TYPICAL CONNECTION DIAGRAM

Figure 2. Typical Connection Diagram

For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen-

tial solution is provided on the Customer Evaluation Board.

FILT+

VA V

+5V

5.1 

1 F

SDOUT2

DIF0/AD0/CS

Power Down

and Mode

Settings

0.01 F

MODE0/SDA/CDOUT

MODE1/SCL/CCLK

REF_GND VLC

AIN +1

AIN -

Channel 1 Analog

Input Buffer

AIN +2

AIN -

Channel 2 Analog

Input Buffer

AIN +3

AIN -

Channel 3 Analog

Input Buffer

AIN +4

AIN -

Channel 4 Analog

Input Buffer

0.1 F

GND

220 F

0.1 F

1F

GND

DIF1/AD1/CDIN

RST

OVFL

0.01

0.01F

+5V to 3.3V

1 F

A/D CONVERTER

CS5364

SDOUT1/TDM

SCLK

MCLK

Timing Logic

and Clock

Audio Data

Processor

MDIV

CLKMODE

LRCK/FS

RESERVED

+5V to 1.8V

3, 8,10, 15, 16, 17, 18,

19, 29, 32, 43, 44, 45, 46

334, 9

VLS +5V to 1.8V

XTI

XTO

+5V

VX 20

Resistor may only be used if

VD is derived from VA. If used,

do not drive any other logic

from VD.

0.01

F

TDM

10 DS625F5

CS5364

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to 0 V.

1. TDM Quad-Speed Mode specified to operate correctly at VLS  3.14 V.

ABSOLUTE RATINGS

Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed

at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up.

SYSTEM CLOCKING

Parameter Symbol Min Typ Max Unit

DC Power Supplies: Positive Analog

Positive Crystal

Positive Digital

Positive Serial Logic

Positive Control Logic

VLS

VLC

4.75

3.14

1.711

1.71

5.0

3.3

5.25 V

Ambient Operating Temperature (-CQZ)

(-DQZ)

TAC

TAA

-40

105 °C

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Analog

Positive Crystal

Positive Digital

Positive Serial Logic

Positive Control Logic

VLS

VLC

-0.3 - +6.0 V

Input Current Iin -10

10 mA

Analog Input Voltage VIN -0.3 VA+0.3 V

Digital Input Voltage VIND VL+0.3

Ambient Operating Temperature (Power Applied) TA-50 +125 C

Storage Temperature Tstg -65 +150

Parameter Symbol Min Typ Max Unit

Input Master Clock Frequency MCLK 0.512 55.05 MHz

Input Master Clock Duty Cycle tclkhl 40 60 %

DS625F5 11

CS5364

DC POWER

MCLK = 12.288 MHz; Master Mode. GND = 0 V.

1. Power-Down is defined as RST = LOW with all clocks and data lines held static at a valid logic level.

LOGIC LEVELS

PSRR, VQ AND FILT+ CHARACTERISTICS

MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in

the “Typical Connection Diagram”.

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V

(Normal Operation) VX = 5 V

VD = 5 V

VD = 3.3 V

VLS, VLC = 5 V

VLS, VLC = 3.3 V

Power Supply Current VA = 5 V

(Power-Down) (Note 1) VLS, VLC,VD = 5 V

500

A

Power Consumption

(Normal Operation) All Supplies = 5 V

VA = 5 V, VD = VLS = VLC = 3.3 V

(Power-Down) (Note 1)

510

360

2.75

580

419

Parameter Symbol Min Typ Max Units

High-Level Input Voltage %VLS/VLC VIH 70 - - %

Low-Level Input Voltage %VLS/VLC VIL --30%

High-Level Output Voltage at 100 A load %VLS/VLC VOH 85 - - %

Low-Level Output Voltage at -100 A load %VLS/VLC VOL --15%

SDA Low-Level Output Voltage at -2 mA load %VLC VOL --TBD%

OVFL Current Sink -4 mA

Input Leakage Current logic pins only Iin -10 - 10 A

Parameter Symbol Min Typ Max Unit

Power Supply Rejection Ratio at (1 kHz) PSRR - 65 - dB

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

VA/2

k

A

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

4.4

k

A

12 DS625F5

CS5364

ANALOG CHARACTERISTICS (COMMERCIAL)

Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full-scale input

sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

108

105

114

111

-dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

THD+N -

-105

-91

-51

-99

-45

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

-dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

40 kHz bandwidth -1dB

THD+N -

-105

-91

-51

-102

-99

-45

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

-dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

40 kHz bandwidth -1dB

THD+N -

-105

-91

-51

-102

-99

-45

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -5 - 5 %

Gain Drift - 100 - ppm/°C

Offset Error HPF enabled

HPF disabled

100 LSB

Analog Input Characteristics

Full-scale Differential Input Voltage 1.07*VA 1.13*VA 1.19*VA Vpp

Input Impedance (Differential) - 250 - k

Common Mode Rejection Ratio CMRR - 82 - dB

DS625F5 13

CS5364

ANALOG PERFORMANCE (AUTOMOTIVE)

Test Conditions (unless otherwise specified). VA = 5.25 to 4.75 V, VD = 5.25 to 3.14 V, VLS = VLC = 5.25 to 1.71 V

and TA= -40° to +85° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

106

103

114

111 -dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

THD+N -

-105

-91

-51

-97

-45

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

-dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-97

-45

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

-dB

Total Harmonic Distortion + Noise -1 dB

referred to typical full scale -20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-97

-45

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -7 - 7 %

Gain Drift - 100 - ppm/°C

Offset Error HPF enabled

HPF disabled

100 LSB

Analog Input Characteristics

Full-scale Input Voltage 1.02*VA 1.13*VA 1.24*VA Vpp

Input Impedance (Differential) 250 - k

Common Mode Rejection Ratio CMRR - 82 - dB

14 DS625F5

CS5364

DIGITAL FILTER CHARACTERISTICS

Notes:

1. The filter frequency response scales precisely with Fs.

2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

OVERFLOW TIMEOUT

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode (2 kHz to 54 kHz sample rates)

Passband (Note 1) (-0.1 dB) 0

0.47 Fs

Passband Ripple -0.035 0.035 dB

Stopband (Note 1) 0.58

Stopband Attenuation -95 dB

Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs s

Double-Speed Mode (54 kHz to 108 kHz sample rates)

Passband (Note 1) (-0.1 dB) 0

0.45 Fs

Passband Ripple -0.035 0.035 dB

Stopband (Note 1) 0.68

Stopband Attenuation -92 dB

Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs s

Quad-Speed Mode (108 kHz to 216 kHz sample rates)

Passband (Note 1) (-0.1 dB) 0

0.24 Fs

Passband Ripple -0.035 0.035 dB

Stopband (Note 1) 0.78

Stopband Attenuation -92 dB

Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs s

High-Pass Filter Characteristics

Frequency Response (Note 2) -3.0 dB

-0.13 dB -1

20 -Hz

Phase Deviation (Note 2) @ 20 Hz

10 - Deg

Passband Ripple -0dB

Filter Settling Time 105/Fs - s

Parameter Symbol Min Typ Max Unit

OVFL time-out on overrange condition

Fs = 44.1 kHz

Fs = 192 kHz

(217-1)/Fs

2972

683

-ms

DS625F5 15

CS5364

SERIAL AUDIO INTERFACE - I²S/LJ TIMING

The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.

Notes:

1. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System

Clocking” on page 10.

2. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.

3. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance

is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page

25.

Figure 3. I²S/LJ Timing

Parameter Symbol Min Typ Max Unit

Sample Rates Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

108

216

kHz

Master Mode

SCLK Frequency

SCLK Period 1/(64*216 kHz)

SCLK Duty Cycle (Note 1) (CLKMODE = 0)(Note 2)

(CLKMODE = 1)(Note 2)

tPERIOD

tHIGH

64*Fs

72.3

64*Fs

LRCK setup before SCLK rising

LRCK hold after SCLK rising

tSETUP1

tHOLD1

20 --ns

SDOUT setup before SCLK rising

SDOUT hold after SCLK rising (VLS = 1.8 V)

after SCLK rising (VLS = 3.3 V)

after SCLK rising (VLS = 5 V)

tSETUP2

tHOLD2

--ns

Slave Mode

SCLK Frequency (Note 3)

SCLK Period 1/(64*216 kHz)

SCLK Duty Cycle

tPERIOD

tHIGH

72.3

64*Fs

LRCK setup before SCLK rising

LRCK hold after SCLK rising

tSETUP1

tHOLD1

20 --ns

SDOUT setup before SCLK rising (VLS = 1.8 V)

before SCLK rising (VLS = 3.3 V)

before SCLK rising (VLS = 5 V)

SDOUT hold after SCLK rising (VLS = 1.8 V)

after SCLK rising (VLS = 3.3 V)

after SCLK rising (VLS = 5 V)

tSETUP2

tHOLD2

--ns

LRCK

SDOUT

SCLK

data

channelchannel

data

tHOLD2

tSETUP2

tHOLD1 tSETUP1

tPERIOD tHIGH

16 DS625F5

CS5364

SERIAL AUDIO INTERFACE - TDM TIMING

The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.

Notes:

1. TDM Quad-Speed Mode only specified to operate correctly at VLS  3.14 V.

2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System

Clocking” on page 10.

3. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.

4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaran-

teed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25.

Figure 4. TDM Timing

Parameter Symbol Min Typ Max Unit

Sample Rates Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode1

108

216

kHz

Master Mode

SCLK Frequency

SCLK Period 1/(256*216 kHz)

SCLK Duty Cycle (Note 2) (CLKMODE = 0)(Note 3)

(CLKMODE = 1)(Note 3)

tPERIOD

tHIGH1

256*Fs

FS setup before SCLK rising (Single-Speed Mode)

FS setup before SCLK rising (Double-Speed Mode)

FS setup before SCLK rising (Quad-Speed Mode)

FS width in SCLK cycles

tSETUP1

tHIGH2

128

SDOUT setup before SCLK rising

SDOUT hold after SCLK rising

tSETUP2

tHOLD2

Slave Mode

SCLK Frequency (Note 4)

SCLK Period 1/(256*216 kHz)

SCLK Duty Cycle

tPERIOD

tHIGH1

256*Fs

FS setup before SCLK rising (Single-Speed Mode)

FS setup before SCLK rising (Double-Speed Mode)

FS setup before SCLK rising (Quad-Speed Mode)

FS width in SCLK cycles

tSETUP1

tHIGH2

244

SDOUT setup before SCLK rising

SDOUT hold after SCLK rising

tSETUP2

tHOLD2

SDOUT

SCLK

data data

tHOLD2

tSETUP2

tSETUP1

new frame

data

tPERIOD tHIGH1

tHIGH2

DS625F5 17

CS5364

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING

Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL=30pF

Notes:

1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Figure 5. I²C Timing

2. The operational timing specification deviates from the I2C-Bus Specification and User Manual of

250 ns.

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 600

Bus Free Time Between Transmissions tbuf 4.7 µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0

µs

Clock Low time tlow 4.7

Clock High Time thigh 4.0

Setup Time for Repeated Start Condition tsust 4.7

SDA Hold Time from SCL Falling (Note 1) thdd 0

SDA Setup time to SCL Rising (Note 2) tsud 600 ns

Rise Time of SCL and SDA trc -1µs

Fall Time SCL and SDA tfc -300ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 1000 ns

tbuf thdst

tlo w thdd

thigh

tsud

Stop Sta rt

SDA

SCL

tirs

RST

thdst

trc

tfc

tsust

tsusp

Start Stop

Repe ated

trd tfd

tack

18 DS625F5

CS5364

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING

Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL=30pF

Notes:

1. Data must be held for sufficient time to bridge the transition time of CCLK.

2. For fsck <1 MHz

Figure 6. SPI Timing

Parameter Symbol Min Max Units

CCLK Clock Frequency fsck 06.0MHz

RST Rising Edge to CS Falling tsrs 20

CS Falling to CCLK Edge tcss 20

CS High Time Between Transmissions tcsh 1.0 s

CCLK Low Time tscl 66

CCLK High Time tsch 66

CDIN to CCLK Rising Setup Time tdsu 40

CCLK Rising to DATA Hold Time (Note 1) tdh 15

CCLK Falling to CDOUT Stable tpd

Rise Time of CDOUT tr1 25

Fall Time of CDOUT tf1

Rise Time of CCLK and CDIN (Note 2) tr2 100

Fall Time of CCLK and CDIN (Note 2) tf2

CCLK

CDIN

CDOUT

RST tsrs

tscl

tsch

tcss

tr2

tf2

tcsh

tdsu tdh

tpd

DS625F5 19

CS5364

4. APPLICATIONS

4.1 Power

CS5364 features five independent power pins that power various functional blocks within the device and

allow for convenient interfacing to other devices. Table 1 shows what portion of the device is powered from

each supply pin. Please refer to “Recommended Operating Conditions” on page 10 for the valid range of

each power supply pin. The power supplied to each power pin can be independent of the power supplied to

any other pin.

To meet full performance specifications, the CS5364 requires normal low-noise board layout. The “Typical

Connection Diagram” on page 9 shows the recommended power arrangements, with the VA pins connected

to a clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be

powered from the analog supply via a single-pole decoupling filter.

Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high-frequen-

cy capacitors placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ pins

in order to avoid unwanted coupling of these signals into the device. The FILT+ and VQ decoupling capac-

itors must be positioned to minimize the electrical path to ground.

The CDB5364 evaluation board demonstrates optimum layout for the device.

4.2 Control Port Mode and Stand-Alone Operation

4.2.1 Stand-Alone Mode

In Stand-Alone Mode, the CS5364 is programmed exclusively with multi-use configuration pins. This mode

provides a set of commonly used features, which comprise a subset of the complete set of device features

offered in Control Port Mode.

To use the CS5364 in Stand-Alone Mode, the configuration pins must be held in a stable state, at valid logic

levels, and RST must be asserted until the power supplies and clocks are stable and valid. More informa-

tion on the reset function is available in Section 4.5 on page 22.

4.2.2 Control Port Mode

In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become

software pins that support the I²C or SPI bus protocol. To initiate Control Port Mode, a controller that sup-

ports I²C or SPI must be used to enable the internal register functionality. This is done by setting the CP-

EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins

are ignored, and the internal register settings determine the operating modes of the part. Figure 4.13 on

page 30 provides detailed information about the I²C and SPI bus protocols.

Power Supply Pin

Pin Name Pin Number Functional Block

VA 4, 9 Analog Core

VX 20 Crystal Oscillator

VD 33 Digital Core

VLS 28 Serial Audio Interface

VLC 35 Control Logic

Table 1. Power Supply Pin Definitions

20 DS625F5

CS5364

4.3 Master Clock Source

The CS5364 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillator

driver or an externally generated clock.

4.3.1 On-Chip Crystal Oscillator Driver

When using the on-board crystal oscillator driver, the XTI pin (pin 21) is the input for the Master Clock (MC-

LK) to the device. The XTO pin (pin 22) must not be used to drive anything other than the oscillator tank

circuitry. When using the on-board crystal driver, the topology shown in Figure 7 must be used. The crystal

oscillator manufacturer supplies recommended capacitor values. A buffered copy of the XTI input is avail-

able as an output on the MCLK pin (pin 23), which is level-controlled by VLS and may be used to synchro-

nize other parts to the device.

Figure 7. Crystal Oscillator Topology

4.3.2 Externally Generated Master Clock

If an external clock is used, the XTI and XTO pins must be grounded, and the MCLK pin becomes an input

for the system master clock. The incoming MCLK should be at the logic level set by the user on the VLS

supply pin.

XTI

XTO 22

DS625F5 21

CS5364

4.4 Master and Slave Operation

CS5364 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.

See Section 4.5 on page 22 for a detailed description of SCLK and LRCK/FS.

The CS5364 can operate as either clock master or clock slave with respect to SCLK and LRCK/FS. In Mas-

ter Mode, the CS5364 derives SCLK and LRCK/FS synchronously from MCLK and outputs the derived

clocks on the SCLK pin (pin 25) and the LRCK/FS pin (pin 24), respectively. In Slave Mode, the SCLK and

LRCK/FS are inputs, and the input signals must be synchronously derived from MCLK by a separate device

such as another CS5364 or a microcontroller. Figure 8 illustrates the clock flow of SCLK and LRCK/FS in

both Master and Slave Modes.

The Master/Slave operation is controlled through the settings of M1 and M0 pins in Stand-Alone Mode or

by the M[1] and M[0] bits in the Global Mode Control Register in Control Port Mode. See Section 4.6 on page

23 for more information regarding the configuration of M1 and M0 pins or M[1] and M[0] bits.

Figure 8. Master/Slave Clock Flow

4.4.1 Synchronization of Multiple Devices

To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must

be the same for all CS5364 devices in the system. If only one master clock source is needed, one solution

is to place one CS5364 in Master Mode, and slave all of the other devices to the one master, as illustrated

in Figure 9. If multiple master clock sources are needed, one solution is to supply all clocks from the same

external source and time the CS5364 reset de-assertion with the falling edge of MCLK. This will ensure that

all converters begin sampling on the same clock edge.

Figure 9. Master and Slave Clocking for a Multi-Channel Application

ADC as

clock

master

Controller

LRCK/FS

SCLK ADC as

clock

slave

Controller

LRCK/FS

SCLK

Master

ADC

Slave1

ADC

Slave2

ADC

Slave3

ADC

SCLK & LRCK/FS

22 DS625F5

CS5364

4.5 Serial Audio Interface (SAI) Format

The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM,

SDOUT2, SDOUT3/TDM and SDOUT4). The CS5364 output is serial data in I²S, Left-Justified (LJ), or Time

Division Multiplexed (TDM) digital audio interface formats. These formats are available to the user in both

Stand-Alone Mode and Control Port Mode.

4.5.1 I²S and LJ Format

The I²S and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are

transmitted, odd channels first, then even. The MSB is always clocked out first.

In Slave Mode, the number of SCLK cycles per channel is fixed as described under “Serial Audio Interface

- I²S/LJ Timing” on page 15. In Slave Mode, if more than 32 SCLK cycles per channel are received from a

master controller, the CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per

channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK

cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Ap-

plication Note AN282.

Figure 10. I²S Format

Figure 11. LJ Format

Odd Channels 1,3, ... Even Channels 2,4, ...

LRCK

receiver latches data on rising edges of SCLK

SDOUT

SCLK

MSB ... LSB MSB ... LSB MSB

Odd Channels 1,3, ... Even Channels 2,4, ...

LRCK

receiver latches data on rising edges of SCLK

MSB ... LSB MSBMSB ... LSBSDOUT

SCLK

DS625F5 23

CS5364

4.5.2 TDM Format

In TDM Mode, all four channels of audio data are serially clocked out during a single Frame Sync (FS) cy-

cle, as shown in Figure 12. The rising edge of FS signifies the start of a new TDM frame cycle. Each chan-

nel slot occupies 32 SCLK cycles, with the data left justified and with MSB first. TDM output data should be

latched on the rising edge of SCLK within time specified under ”Serial Audio Interface - TDM Timing” sec-

tion on page 16. The TDM data output port resides on the SDOUT1 pin. The TDM output pin is compli-

mentary TDM data. All SDOUT pins will remain active during TDM Mode. Refer to Section 4.11 “Optimizing

Performance in TDM Mode” on page 29 for critical system design information.

Figure 12. TDM Format

4.5.3 Configuring Serial Audio Interface Format

The serial audio interface format of the data is controlled by the configuration of the DIF1 and DIF0 pins in

Stand-Alone Mode or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control Port

Mode, as shown in Table 2.

Table 2. DIF1 and DIF0 Pin Settings

4.6 Speed Modes

4.6.1 Sample Rate Ranges

CS5364 supports sampling rates from 2 kHz to 21 kHz, divided into three ranges: 2 kHz - 54 kHz, 54 kHz -

108 kHz, and 108 kHz - 216 kHz. These sampling speed modes are called Single-Speed Mode (SSM),

Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively.

4.6.2 Using M1 and M0 to Set Sampling Parameters

The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and

M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control

Port Mode, as shown in Table 3.

Table 3. M1 and M0 Settings

DIF1 DIF0 Mode

0 0 Left-Justified

01 I²S

10 TDM

11 Reserved

M1 M0 Mode Frequency Range

0 0 Single-Speed Master Mode (SSM) 2 kHz - 54 kHz

0 1 Double-Speed Master Mode (DSM) 54 kHz - 108 kHz

1 0 Quadruple-Speed Master Mode (QSM) 108 kHz - 216 kHz

1 1 Auto-Detected Speed Slave Mode 2 kHz - 216 kHz

SCLK

LSBMSB LSBMSB LSBMSB

TDM OUT

Channel 1 Channel 4Channel 2 Channel 3

32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks

LSB LSBMSB

LSBMSB

Data

Zeroes

24 DS625F5

CS5364

4.6.3 Master Mode Clock Dividers

Figure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in-

cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).

Figure 13. Master Mode Clock Dividers

4.6.4 Slave Mode Audio Clocking With Auto-Detect

In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when

changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider

pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided-

down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio

as shown in Figure 14.

Figure 14. Slave Mode Auto-Detect Speed

÷ 128

÷ 64

M0M1

LRCK/ FS

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 4

÷ 1

SCLK

Single

Speed

Quad

Speed

Double

Speed

÷ 256

pin CLKMODE MDIV n/a

MCLK ÷ 1

÷ 1.5 ÷ 2

÷ 1

÷ 2

÷ 1

bit MDIV1 MDIV0

0/1 0/1 0/1

MCLK DIVIDERS

SAMPLE RATE DIVIDERS

CLKMODE

128

Single-Speed

256

pin CLKMODE MDIV n/a

External

MCLK

÷ 1

÷ 1.5 ÷ 2

÷ 1

÷ 2

÷ 1

bit MDIV1 MDIV0

0/1 0/1 0/1

MCLK DIVIDERS

CLKMODE

÷LRCK

LRCK

Double-Speed

Quad-Speed

SPEED MODE

Internal

MCLK

DS625F5 25

CS5364

4.7 Master and Slave Clock Frequencies

Tables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The MC-

LK/LRCK ratio should be kept at a constant value during each mode. In Master Mode, the device outputs

the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set according to design preference.

However, device performance is guaranteed only when using the ratios shown in the tables.

Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S

Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S

Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S

Table 7. Frequencies for 48 kHz Sample Rate using TDM

Table 8. Frequencies for 48 kHz Sample Rate using TDM

Control Port Mode only

LJ/I²S MASTER OR SLAVE SSM Fs = 48 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.576 18.384 12.288

SCLK (MHz) 3.072 3.072 3.072 3.072 3.072

MCLK/LRCK Ratio 1024 768 512 384 256

SCLK/LRCK Ratio 64 64 64 64 64

LJ/I²S MASTER OR SLAVE DSM Fs = 96 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.567 18.384 12.288

SCLK (MHz) 6.144 6.144 6.144 6.144 6.144

MCLK/LRCK Ratio 512 384 256 192 128

SCLK/LRCK Ratio 64 64 64 64 64

LJ/I²S MASTER OR SLAVE QSM Fs = 192 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24 18.384 12.288

SCLK (MHz) 12.288 12.288 12.288 12.288 12.288

MCLK/LRCK Ratio 256 192 128 96 64

SCLK/LRCK Ratio 64 64 64 64 64

TDM MASTER SSM Fs = 48 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.567 18.384 12.288

SCLK (MHz) 12.288 12.288 12.288 12.288 12.288

MCLK/FS Ratio 1024 768 512 384 256

SCLK/FS Ratio 256 256 256 256 256

TDM SLAVE SSM Fs = 48 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.567 18.384 12.288

SCLK (MHz) 12.288 12.288 12.288 12.288 12.288

MCLK/FS Ratio 1024 768 512 384 256

SCLK/FS Ratio 256 256 256 256 256

26 DS625F5

CS5364

Table 9. Frequencies for 96 kHz Sample Rate using TDM

Table 10. Frequencies for 96 kHz Sample Rate using TDM

Table 11. Frequencies for 192 kHz Sample Rate using TDM

Table 12. Frequencies for 192 kHz Sample Rate using TDM

TDM MASTER DSM Fs = 96 kHz

MCLK Divider 432- -

MCLK (MHz) 49.152 36.864 24.567 - -

SCLK (MHz) 24.576 24.576 24.576 - -

MCLK/FS Ratio 512 384 256 - -

SCLK/FS Ratio 256 256 256 - -

TDM SLAVE DSM Fs = 96 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.567 18.384 12.288

SCLK (MHz) 24.576 24.576 24.576 24.576 24.576

MCLK/FS Ratio 512 384 256 192 128

SCLK/FS Ratio 256 256 256 256 256

TDM MASTER QSM Fs = 192 kHz

MCLK Divider 4----

MCLK (MHz) 49.152 - - - -

SCLK (MHz) 49.152 - - - -

MCLK/FS Ratio 256 - - - -

SCLK/FS Ratio 256 - - - -

TDM SLAVE QSM Fs = 192 kHz

MCLK Divider 4321.5 1

MCLK (MHz) 49.152 36.864 24.567 18.384 12.288

SCLK (MHz) 49.152 49.152 49.152 49.152 49.152

MCLK/FS Ratio 256 192 128 96 64

SCLK/FS Ratio 256 256 256 256 256

DS625F5 27

CS5364

4.8 Reset

The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon

de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device

starts sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When chang-

ing between mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface for-

mat, master/slave, or speed modes, it is recommended to reset the device following the change by holding

the RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition.

4.8.1 Power-Down Mode

The CS5364 features a Power-Down Mode in which power is temporarily withheld from the modulators, the

crystal oscillator driver, the digital core, and the serial port. The user can access Power-Down Mode by

holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logic-

low). “DC Power” on page 11 shows the power-saving associated with Power-Down Mode.

4.9 Overflow Detection

4.9.1 Overflow in Stand-Alone Mode

The CS5364 includes overflow detection on all input channels. In Stand-Alone Mode, this information is

presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over-

range condition in any channel is detected. The data will remain low, then time-out as specified in Section

"Overflow Timeout" on page 14. After the time-out, the OVFL pin will return to a logical high if there has not

been any other over-range condition detected. Note that an over-range condition on any channel will restart

the time-out period.

4.9.2 Overflow in Control Port Mode

In Control Port Mode, the Overflow Status Register interacts with the Overflow Mask Register to provide

interrupt capability for each individual channel. See Section 5.4 "02h (OVFL) Overflow Status Register" on

page 33 for details on these two registers.

28 DS625F5

CS5364

4.10 Analog Connections

The analog modulator samples the input at half of the internal Master Clock frequency, or 6.144 MHz nom-

inally. The digital filter will reject signals within the stopband of the filter. However, there is no rejection of

input signals that are at (N X 6.144 MHz) the digital passband frequency, where n=0,1,2.... Refer to

Figure 15, which shows the suggested filter that will attenuate any noise energy at 6.144 MHz in addition to

providing the optimum source impedance for the modulators. The use of capacitors that have a large volt-

age coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linear-

ity. COG capacitors are recommended for this application. For additional configurations, refer to Cirrus

Application Note AN241.

Figure 15. Recommended Analog Input Buffer

634 

91 

2700 pF

470 pF

COG

10 uF

ADC AIN+

ADC AIN-

AIN+

AIN-

COG

100k

10 k 

10 k

100k

DS625F5 29

CS5364

4.11 Optimizing Performance in TDM Mode

Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise man-

agement is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital

activity with the analog sampling processes to ensure that the noise generated by the digital activity is min-

imized (ideally non-existant) when the analog sampling occurs. Noise management, when implemented

properly, minimizes the on-chip interference between the analog and digital sections of the device. This

technique has proven to be very effective and has simplified the process of implementing an A/D converter

into a systems design. The dominate source of interference (and most difficult to control) is the activity on

the serial audio interface (SAI). However, noise management becomes more difficult to implement as audio

sample rates increase simply due to the fact that there is less time between transitions on the SAI.

The CS5364 A/D converter supports a multi-channel Time-Division-Multiplexed interface for Single, Double

and Quad-Speed sampling modes. In Single-Speed Mode, sample rates below 50 kHz, the required fre-

quencies of the audio serial ports are sufficiently low that it is possible to implement noise-management. In

this mode, the performance of the devices are relatively immune to activity on the audio ports.

However, in Double-Speed and Quad-Speed modes there is insufficient time to implement noise manage-

ment due to the required frequencies of the audio ports. Therefore, analog performance, both dynamic

range and THD+N, can be degraded if the serial port transitions occurr concurrently with the analog sam-

pling. The magnitude of the interference is not only related to the timing of the transition but also the di/dt or

transient currents associated with the activity on the serial ports. Even though there is insufficient time to

properly implement noise management, the interference effects can be minimized by controlling the tran-

sient currents required of the serial ports in Double- and Quad-Speed TDM Modes.

In addition to standard mixed-signal design techniques, system performance can be maximized by following

several guidelines during design.

– Operate the serial audio port at 3.3 V and not 5 V. The lower serial port voltage lowers transent

currents.

– Operate the A/D converter as a system clock Slave. The serial clock and Left/Right clock become high-

impedence inputs in this mode and do not generate significant transient currents.

– Place a buffer on the serial data output very near the A/D converter. Minimizing the stray capacitance

of the printed circuit board trace and the loading presented by other devices on the serial data line will

minimize the transient current.

– Place a resistor, near the converter, beween the A/D serial data output and the buffer. This resistor will

reduce the instantaneous switching currents into the capacitive loads on the nets, resulting in a slower

edge rate. The value of the resistor should be as high as possible without causing timing problems

elsewhere in the system.

4.12 DC Offset Control

The CS5364 includes a dedicated high-pass filter for each channel to remove input DC offset at the system

level. A DC level may result in audible “clicks” when switching between devices in a multi-channel system.

In Stand-Alone Mode, all of the high-pass filters remain enabled. In Control Port Mode, the high-pass filters

default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the re-

spective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output

of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset reg-

ister is frozen, and this DC offset will continue to be subtracted from the conversion result.

30 DS625F5

CS5364

4.13 Control Port Operation

The Control Port is used to read and write the internal device registers. It supports two industry standard

formats, I²C and SPI. The part is in I²C format by default. SPI Mode is selected if there is ever a high-to-low

transition on the AD0/CS pin after the RST pin has been restored high.

In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become

software pins that support the I²C or SPI bus protocol. To initiate Control Port Mode, a controller that sup-

ports I²C or SPI must be used to enable the internal register functionality. This is done by setting the

CP-EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins

are ignored, and the internal register settings determine the operating modes of the part.

4.13.1 SPI Mode

In SPI Mode, CS is the CS5364 chip select signal; CCLK is the control port bit clock (input into the CS5364

from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller.

Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.

To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be

1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits

form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.

The next eight bits are the data that will be placed into the register designated by the MAP. During writes,

the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if

desired.

There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is

a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-

increment after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle that fin-

ishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as

desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.

The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high

impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear

consecutively

Figure 16. SPI Format

MAP

MSB LSB

DATA

byte 1 byte n

R/W R/W

ADDRESS

CHIP

ADDRESS

CHIP

CDIN

CCLK

CDOUT MSB LSB MSB LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

DS625F5 31

CS5364

4.13.2 I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should

be connected through a resistor to VLC or DGND, as desired. The state of the pins is latched when the

CS5364 is being released from RST.

A Start condition is defined as a falling transition of SDA while SCL is high. A Stop condition is a rising tran-

sition of SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent to

the CS5364 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a CS5364,

the chip address field, which is the first byte sent to the CS5364, should match 10011 and be followed by

the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the

next byte is the Memory Address Pointer (MAP), which selects the register to be read or written. If the op-

eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-

ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an

acknowledge bit. The ACK bit is output from the CS5364 after each input byte is read and is input to the

CS5364 from the microcontroller after each transmitted byte.

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. The write

operation is aborted after the acknowledge for the MAP byte by sending a Stop condition. The following

pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10011xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10011xx1 (chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Figure 17. I²C Write Format

Figure 18. I²C Read Format

4 5 6 7 24 25

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK

STOP

ACKACKACK

1 0 0 1 1 AD1 AD0 0

SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28

DATA +n

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK

STOP

ACK

1 0 0 1 1 AD1 AD0 0

SDA 1 0 0 1 1 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR 6 5 4 3 2 1 0 7 0 7 0 7 0

168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28

2 3 10 11 17 18 19 25

ACK

DATA + n

STOP

32 DS625F5

CS5364

5. REGISTER MAP

In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All

registers above 0Ah are RESERVED.

5.1 Register Quick Reference

5.2 00h (REVI) Chip ID Code & Revision Register

Default: See description

The Chip ID Code & Revision Register is used to store the ID and revision of the chip.

Bits[7:4] contain the chip ID, where the CS5364 is represented with a value of 0x4.

Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented

as 0x1, etc.

5.3 01h (GCTL) Global Mode Control Register

Default: 0x00

The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data

format and the Master clock dividers for all channels. It also contains a Control Port enable bit.

Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone

Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding reg-

ister values become functional.

Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit in-

vokes 256X mode (divide XTI by 1.0 - pass through).

Adr Name76543210

00 REVI CHIP-ID[3:0] REVISION[3:0]

01 GCTL CP-EN CLKMODE MDIV[1:0] DIF[1:0] MODE[1:0]

02 OVFL RESERVED RESERVED RESERVED RESERVED OVFL4 OVFL3 OVFL2 OVFL1

03 OVFM RESERVED RESERVED RESERVED RESERVED OVFM4 OVFM3 OVFM2 OVFM1

04 HPF RESERVED RESERVED RESERVED RESERVED HPF4 HPF3 HPF2 HPF1

05 RESERVED - - - - - - - -

06 PDNE RESERVED PDN-BG PDN-OSC RESERVED RESERVED PDN43 PDN21

07 RESERVED - - - - - - - -

08 MUTE RESERVED RESERVED RESERVED RESERVED MUTE4 MUTE3 MUTE2 MUTE1

09 RESERVED - - - - - - - -

0A SDEN RESERVED RESERVED RESERVED SDEN2 SDEN1

R/W76543210

R CHIP-ID[3:0] REVISION[3:0]

R/W76543210

R/W CP-EN CLKMODE MDIV[1:0] DIF[1:0] MODE[1:0]

DS625F5 33

CS5364

Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is

selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divid-

ed by 4.

The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].

Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data.

DIF[1:0]

0x00 Left-Justified format

0x01 I²S format

0x02 TDM

0x03 Reserved

Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as

an audio clocking Master or Slave.

MODE[1:0]

0x00 Single-Speed Mode Master

0x01 Double-Speed Mode Master

0x02 Quad-Speed Mode Master

0x03 Slave Mode all speeds

5.4 02h (OVFL) Overflow Status Register

Default: 0xFF, no overflows have occurred.

Note: This register interacts with Register 03h, the Overflow Mask Register.

The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition

on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open

drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, pro-

viding full interrupt capability.

5.5 03h (OVFM) Overflow Mask Register

Default: 0xFF, all overflow interrupts enabled.

The Overflow Mask Register is used to allow or prevent individual channel overflow events from creating

activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow

bit in the Overflow Status register is prevented from causing any activity on the OVFL pin.

CLKMODE,MDIV[1],MDIV[0] DESCRIPTION

000 Divide-by-1

100 Divide-by-1.5

001 or 010 Divide-by-2

101 or 110 Divide-by-3

011 Divide-by-4

111 Reserved

R/W76543210

R RESERVED RESERVED RESERVED RESERVED OVFL4 OVFL3 OVFL2 OVFL1

R/W76543210

R/W RESERVED RESERVED RESERVED RESERVED OVFM4 OVFM3 OVFM2 OVFM1

34 DS625F5

CS5364

5.6 04h (HPF) High-Pass Filter Register

Default: 0x00, all high-pass filters enabled.

The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel.

These filters are used to perform DC offset calibration, a procedure that is detailed in “DC Offset Control”

on page 29.

5.7 05h Reserved

5.8 06h (PDN) Power Down Register

Default: 0x00 - everything powered up

The Power Down Register is used as needed to reduce the chip’s power consumption.

Bit[7] RESERVED

Bit[6] RESERVED

Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.

Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is

shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the

MCLK pin, it is also prevented from clocking the device internally.

Bit[1:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs

are forced to all zeroes.

5.9 07h Reserved

5.10 08h (MUTE) Mute Control Register

Default: 0x00, no channels are muted.

The Mute Control Register is used to mute or unmute the serial audio data output of individual channels.

When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes.

R/W76543210

R/W RESERVED RESERVED RESERVED RESERVED HPF4 HPF3 HPF2 HPF1

R/W76543210

RESERVED - - - - - - - -

R/W76543210

R/W RESERVED PDN-BG PDN-OSC RESERVED RESERVED PDN43 PDN21

R/W76543210

RESERVED - - - - - - - -

R/W76543210

R/W RESERVED RESERVED RESERVED RESERVED MUTE4 MUTE3 MUTE2 MUTE1

DS625F5 35

CS5364

5.11 09h Reserved

5.12 0Ah (SDEN) SDOUT Enable Control Register

Default: 0x00, all SDOUT pins enabled.

The SDOUT Enable Control Register is used to tri-state the serial audio data output pins. Each bit, when

set, tri-states the associated SDOUT pin.

R/W76543210

RESERVED - - - - - - - -

R/W76543210

R/W RESERVED RESERVED RESERVED SDEN2 SDEN1

36 DS625F5

CS5364

6. FILTER PLOTS

Figure 19. SSM Passband

Figure 20. DSM Passband

Figure 21. QSM Passband

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

Frequency (normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

Frequency (normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.2

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

Frequency (normalized to Fs)

Amplitude (dB)

DS625F5 37

CS5364

Figure 22. SSM Stopband

Figure 23. DSM Stopband

Figure 24. QSM Stopband

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

−140

−120

−100

−80

−60

−40

−20

Frequency (normalized to Fs)

Amplitude (dB)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

−140

−120

−100

−80

−60

−40

−20

Frequency (normalized to Fs)

Amplitude (dB)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

−120

−100

−80

−60

−40

−20

Frequency (normalized to Fs)

Amplitude (dB)

38 DS625F5

CS5364

Figure 25. SSM -1 dB Cutoff

Figure 26. DSM -1 dB Cutoff

Figure 27. QSM -1 dB Cutoff

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

−2

−1.8

−1.6

−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

Frequency (normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

−2

−1.8

−1.6

−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

Frequency (normalized to Fs)

Amplitude (dB)

0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.

−2

−1.8

−1.6

−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

Frequency (normalized to Fs)

Amplitude (dB)

DS625F5 39

CS5364

7. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with

a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This

technique ensures that the distortion components are below the noise level and do not affect the measure-

ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-199, and

the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. The dynamic range is

specified with and without an A-weighting filter.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Specified using an A-weighting filter.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at

1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between one channel and all remaining channels, measured for each channel at the

converter's output with no signal to the input under test and a full-scale signal applied to all other channels.

Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

Intrachannel Phase Deviation

The deviation from linear phase within a given channel.

Interchannel Phase Deviation

The difference in phase response between channels.

40 DS625F5

CS5364

8. PACKAGE DIMENSIONS

THERMAL CHARACTERISTICS

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- 0.055 0.063 --- 1.40 1.60

A1 0.002 0.004 0.006 0.05 0.10 0.15

B 0.007 0.009 0.011 0.17 0.22 0.27

D 0.343 0.354 0.366 8.70 9.0 BSC 9.30

D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

E 0.343 0.354 0.366 8.70 9.0 BSC 9.30

E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60

L 0.018 0.24 0.030 0.45 0.60 0.75

0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm. JEDEC Designation: MS026

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature - - 135 C

Package Thermal Resistance JA -48-

C/W

JC -15-



48L LQFP PACKAGE DRAWING



DS625F5 41

CS5364

9. ORDERING INFORMATION

10.REVISION HISTORY

Product Description Package Pb-Free Grade Temp Range Container Order #

CS5364

114dB, 192kHz,

4-channel A/D

Converter

48-pin

LQFP YES

Commercial -40°C to +85°C Tray CS5364-CQZ

Tape & Reel CS5364-CQZR

Automotive -40°C to +105°C Tray CS5364-DQZ

Tape & Reel CS5364-DQZR

CDB5364 Evaluation Board for CS5364 CDB5364

Revision Changes

DEC ‘06

Initial release.

JUL ‘07

Updated the wording of pin 24, LRCK/FS, in the pin description table on page 7 to correctly reflect the

high/low clocking state for odd-channel c in I²S and LJ Modes.

JAN ‘08

Corrected SCL/CCLK pin description (Pin 39) for "Control Port Mode" on page 8.

APR ‘09

Corrected Absolute Max temp for “Ambient Operating Temperature (Power Applied)” on page 10.

JUL ‘14

Updated I2C and SPI bullet under “Additional Control Port Features” on page 1.

Added Note 2 to “Switching Specifications - Control Port - I²C Timing” on page 17.

42 DS625F5

CS5364

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find the one nearest you, go to www.cirrus.com.

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information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

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CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO

FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-

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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

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