DATASHEET ISL33001, ISL33002, ISL33003 FN7560 Rev 6.00 July 11, 2014 I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability The ISL33001, ISL33002, ISL33003 are 2-Channel Bus Buffers that provide the buffering necessary to extend the bus capacitance beyond the 400pF maximum specified by the I2C specification. In addition, the ISL33001, ISL33002, ISL33003 feature rise time accelerator circuitry to reduce power consumption from passive bus pull-up resistors and improve data-rate performance. All devices also include hot swap circuitry to prevent corruption of the data and clock lines when I2C devices are plugged into a live backplane, and the ISL33002 and ISL33003 add level translation for mixed supply voltage applications. The ISL33001, ISL33002, ISL33003 operate at supply voltages from +2.3V to +5.5V at a temperature range of -40C to +85C. Summary of Features PART NUMBER LEVEL TRANSLATION Features * 2 Channel I2C compatible bi-directional buffer * +2.3VDC to +5.5VDC supply range * >400kHz operation * Bus capacitance buffering * Rise time accelerators * Hot swapping capability * 6kV Class 3 HBM ESD protection on all pins * 12kV HBM ESD protection on SDA/SCL pins * Enable pin (ISL33001 and ISL33003) * Logic level translation (ISL33002 and ISL33003) ENABLE READY PIN PIN ACCELERATOR DISABLE ISL33001 No Yes Yes No ISL33002 Yes No No Yes ISL33003 Yes Yes No No * READY logic pin (ISL33001) * Accelerator disable pin (ISL33002) * Pb-free (RoHS Compliant) 8 Ld SOIC (ISL33001 only), 8 Ld TDFN (3mmx3mm) and 8 Ld MSOP packages * Low quiescent current . . . . . . . . . . . . . . . . . . . . . . . 2.1mA typ * Low shutdown current . . . . . . . . . . . . . . . . . . . . . . . . 0.5A typ Related Literature * AN1543, "ISL33001MSOPEVAL1Z, ISL33002MSOPEVAL1Z, ISL33003MSOPEVAL1Z Evaluation Board User's Manual" * AN1637, "Level Shifting Between 1.8V and 3.3V Using I2C Buffers" Applications * I2C bus extender and capacitance buffering * Server racks for telecom, datacom, and computer servers * Desktop computers * Hot-swap board insertion and bus isolation VCC1 +3.3V +5.0V 100kHz I2C BUS WITH 2.7k PULL-UP RESISTOR AND 400pF BUS CAPACITANCE VCC2 WITHOUT BUFFER C SDA SDA ISL33003 SCL SCL I2C DEVICE A EN I2C DEVICE B VOLTAGE (1V/DIV) BACK PLANE WITH BUFFER GND TIME (2s/DIV) FIGURE 1. TYPICAL OPERATING CIRCUIT FN7560 Rev 6.00 July 11, 2014 FIGURE 2. BUS ACCELERATOR PERFORMANCE Page 1 of 18 ISL33001, ISL33002, ISL33003 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. # ISL33001IRTZ 3001 -40 to +85 8 Ld TDFN (0.65mm Pitch) L8.3x3A ISL33001IRT2Z 01R2 -40 to +85 8 Ld TDFN (0.5mm Pitch) L8.3x3H ISL33001IBZ 33001 IBZ -40 to +85 8 Ld SOIC M8.15 ISL33001IUZ 33001 -40 to +85 8 Ld MSOP M8.118 ISL33002IRTZ 3002 -40 to +85 8 Ld TDFN (0.65mm Pitch) L8.3x3A ISL33002IRT2Z 02R2 -40 to +85 8 Ld TDFN (0.5mm Pitch) L8.3x3H ISL33002IUZ 33002 -40 to +85 8 Ld MSOP M8.118 ISL33003IRTZ 3003 -40 to +85 8 Ld TDFN (0.65mm Pitch) L8.3x3A ISL33003IRT2Z 03R2 -40 to +85 8 Ld TDFN (0.5mm Pitch) L8.3x3H ISL33003IUZ 33003 -40 to +85 8 Ld MSOP M8.118 ISL33001MSOPEVAL1Z ISL33001 Evaluation Board ISL33002MSOPEVAL1Z ISL33002 Evaluation Board ISL33003MSOPEVAL1Z ISL33003 Evaluation Board NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL33001, ISL33002, ISL33003. For more information on MSL please see techbrief TB363. Pin Configurations ISL33001 (8 LD SOIC, MSOP) TOP VIEW ISL33001 (8 LD TDFN) TOP VIEW 8 VCC1 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 READY EN 1 SCL_OUT 2 PAD EN 1 8 VCC1 SCL_OUT 2 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 READY ISL33002 (8 LD MSOP) TOP VIEW ISL33002 (8 LD TDFN) TOP VIEW VCC2 1 8 VCC1 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 ACC SCL_OUT 2 FN7560 Rev 6.00 July 11, 2014 PAD VCC2 1 8 VCC1 SCL_OUT 2 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 ACC Page 2 of 18 ISL33001, ISL33002, ISL33003 Pin Configurations (Continued) ISL33003 (8 LD MSOP) TOP VIEW ISL33003 (8 LD TDFN) TOP VIEW VCC2 1 8 VCC1 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 EN SCL_OUT 2 VCC2 1 8 VCC1 SCL_OUT 2 7 SDA_OUT SCL_IN 3 6 SDA_IN GND 4 5 EN PAD Pin Descriptions PIN PIN NAME NUMBER FUNCTION NOTES VCC1 8 VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency 0.01F to 0.1F capacitor. VCC2 1 VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency ISL33002 (8 LD TDFN, 8 LD MSOP) 0.01F to 0.1F capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic ISL33003 (8 LD TDFN, 8 LD MSOP) thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these pins to VCC2. GND 4 Device Ground Pin EN 1 Buffer Enable Pin. Logic "0" disables the device. Logic "1" enables the device. Logic ISL33001 (8 LD TDFN, 8 LD SOIC, MSOP) threshold referenced to VCC1. ISL33003 (8 LD TDFN, 8 LD MSOP) 5 READY 5 ISL33001 only Buffer active `Ready' open drain logic output. When buffer is active, READY is high impedance. When buffer is inactive, READY is low impedance to ground. Connect to 10k pull-up resistor to VCC1. ACC 5 Rise Time Accelerator Enable Pin. Logic "0" disables the accelerator. Logic "1" enables the accelerator. Logic threshold referenced to VCC1. SDA_IN 6 Data I/O Pins SDA_OUT 7 SCL_IN 3 SCL_OUT 2 PAD FN7560 Rev 6.00 July 11, 2014 ISL33002 only Clock I/O Pins Thermal pad should be connected to ground or floated. Thermal Pad; TDFN only Page 3 of 18 ISL33001, ISL33002, ISL33003 Absolute Maximum Ratings Thermal Information (All voltages referenced to GND) VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY. . . . . . . . . . . . . -0.3V to +7V EN, ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V Maximum Sink Current (SDA and SCL Pins) . . . . . . . . . . . . . . . . . . . . 20mA Maximum Sink Current (READY pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7mA Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . . . . . . . . . . . . 85C ESD Ratings. . . . . . . . . . . . . . . . . . . . . . See "ESD PROTECTION" on page 5 Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VCC1 and VCC2 Supply Voltage Range . . . . . . . . . . . . . . . . . +2.3V to +5.5V Thermal Resistance JA (C/W) JC (C/W) 47 4 8 Ld TDFN Package (Notes 5, 6) . . . . . . . . . . (0.50mm Pitch) 8 Ld TDFN Package (Notes 5, 6) . . . . . . . . . . 48 6 (0.65mm Pitch) 8 Ld MSOP Package (Notes 4, 7) . . . . . . . . . 151 50 8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . . 120 56 Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. For JC, the "case temp" location is taken at the package top center. Electrical Specifications VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply over the operating temperature range, -40C to +85C. PARAMETER SYMBOL CONDITIONS TEMP (C) MIN (Note 9) TYP MAX (Note 9) UNITS Full 2.3 - 5.5 V POWER SUPPLIES VCC1 Supply Range VCC1 VCC2 Supply Range VCC2 ISL33002 and ISL33003 Full 2.3 - 5.5 V Supply Current from VCC1 ICC1 VCC1 = 5.5V; ISL33001 only (Note 11) Full - 2.1 4.0 mA VCC1 = VCC2 = 5.5V; ISL33002 and ISL33003 (Note 11) Full - 2.0 3.0 mA VCC2 = VCC1 = 5.5V; ISL33002 and ISL33003 (Note 11) Full - 0.22 0.6 mA Supply Current from VCC2 ICC2 VCC1 Shut-down Supply Current ISHDN1 VCC2 Shut-down Supply Current ISHDN2 VCC1 = 5.5V, VEN = GND; ISL33001 only Full - 0.5 - A VCC1 = VCC2 = 5.5V, VEN = GND; ISL33003 only (Note 13) Full - 0.05 - A VCC1 = VCC2 = 5.5V, VEN = GND, ISL33003 only (Note 13) Full - 0.06 - A SDA and SCL pins floating Full 0.8 1 1.2 V START-UP CIRCUITRY Precharge Circuitry Voltage VPRE Enable High Threshold Voltage VEN_H +25 - 0.5*VCC 0.7*VCC V Enable Low Threshold Voltage VEN_L +25 0.3*VCC 0.5*VCC - V Enable from 0V to VCC1; ISL33001 and ISL33003 Full -1 0.1 1 A Enable Pin Input Current IEN Enable Delay, On-Off tEN-HL ISL33001 and ISL33003 (Note 10) +25 - 10 - ns Enable Delay, Off-On tEN-LH ISL33001 and ISL33003 (Figure 3) +25 - 86 - s Bus Idle Time tIDLE (Figure 4, Note 12) Full 50 83 150 s Ready Pin OFF State Leakage Current IOFF ISL33001 only +25 -1 0.1 1 A Ready Delay, On-Off tREADY-HL ISL33001 only (Note 10) +25 - 10 - ns FN7560 Rev 6.00 July 11, 2014 Page 4 of 18 ISL33001, ISL33002, ISL33003 Electrical Specifications VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) PARAMETER SYMBOL CONDITIONS TEMP (C) MIN (Note 9) TYP MAX (Note 9) UNITS Ready Delay, Off-On tREADY-LH ISL33001 only (Note 10) +25 - 10 - ns Ready Output Low Voltage VOL_READY VCC1 = +2.5V, IPULLUP = 3mA; ISL33001 only Full - - 0.4 V ITRAN_ACC VCC1 = 2.7V, VCC2 = 2.7V ; (ACC = 0.7*VCC1 for ISL33002 only) (Figure 8) +25 - 5 - mA RISE-TIME ACCELERATORS Transient Accelerator Current Accelerator Pin Enable Threshold VACC_EN ISL33002 only +25 - 0.5*VCC1 0.7*VCC1 V Accelerator Pin Disable Threshold VACC_DIS ISL33002 only +25 0.3*VCC1 0.5*VCC1 - V IACC ISL33002 only +25 -1 0.1 1 A ISL33002 only (Note 10) +25 - 10 - ns SDA, SCL I/O Pins Human Body Model, SDA and SCL pins to ground only (JESD22-A114) +25 - 12 - kV All Pins Machine Model (JESD22-A115) +25 - 400 - V Class 3 HBM ESD (JESD22-A114) +25 6 - kV Accelerator Pin Input Current Accelerator Delay, On-Off tPDOFF ESD PROTECTION INPUT-OUTPUT CONNECTIONS Input Low Threshold VIL VCC1 = VCC2, 10kto VCC1 on SDA and SCL pins +25 - - 0.3*VCC1 V Input-Output Offset Voltage VOS VCC1 = 3.3V, 10kto VCC1 on SDA and SCL pins, VINPUT = 0.2V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 5) Full 0 50 150 mV Output Low Voltage VOL VCC1 = 2.7V, VINPUT = 0V, ISINK = 3mA on SDA/SCL pins; VCC2 = 2.7V, ISL33002 and ISL33003 (Figure 6) Full - - 0.4 V Buffer SDA and SCL Pins Input Capacitance CIN (Figure 25) +25 - 10 - pF ILEAK SDA and SCL pins = VCC1 = 5.5V; VCC2 = 5.5V, ISL33002 and ISL33003 Full -5 0.1 5 A SCL/SDA Propagation Delay High-to-Low tPHL CLOAD = 100pF, 2.7kto VCC1 on SDA and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 7) +25 0 27 100 ns SCL/SDA Propagation Delay Low-to-High tPLH CLOAD = 100pF, 2.7kto VCC1 on SDA and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 7) +25 0 2 26 ns Input Leakage Current TIMING CHARACTERISTICS NOTES: 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Typical value determined by design simulations. Parameter not tested. 11. Buffer is in the connected state. 12. ISL33002 and ISL33003 limits established by characterization. Not production tested. 13. If the VCC1 and VCC2 voltages diverge, then the shut down ICC increases on the higher voltage supply. FN7560 Rev 6.00 July 11, 2014 Page 5 of 18 ISL33001, ISL33002, ISL33003 Test Circuits and Waveforms - VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC - SDA_OUT and SCL pins connected to VCC - Enable Delay Time Measured on ISL33001 only - ISL33003 performance inferred from ISL33001 - If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH - If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH - EN Logic Input must be high for t > Enable Delay (tEN_LH) prior to SCL_IN transition - Bus Idle Time Measured on ISL33001 only - ISL33002 and ISL33003 performance inferred from ISL33001 VEN VCC VCC 0.5*VCC 0V VSDA_IN VREADY VCC 0.5*VCC 0.5*VCC 0.5VCC VSCL_IN 0V VCC 0V 0.5VCC VREADY 0V tDELAY1 tREADY-LH tDELAY2 tIDLE FIGURE 3. ENABLE DELAY TIME FIGURE 4. BUS IDLE TIME +3.3V 10k 10k VCC1 SCL_OUT 10k SDA_OUT 0.2V SCL_IN OR SDA_IN 10k SDA_IN SCL_IN GND VIN 0.2V VO SCL_OUT OR SDA_OUT VIN 0.2V VOS = VO - 0.2V FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. INPUT TO OUTPUT OFFSET VOLTAGE +2.7V 900 900 VCC1 SCL_OUT 900 VCC1 SDA_OUT 900 SCL_OUT SDA_IN SCL_IN VOL VCC1 GND 0V 0V SDA_OUT FIGURE 6A. TEST CIRCUIT VOL FIGURE 6B. MEASUREMENT POINTS FIGURE 6. OUTPUT LOW VOLTAGE FN7560 Rev 6.00 July 11, 2014 Page 6 of 18 ISL33001, ISL33002, ISL33003 Test Circuits and Waveforms (Continued) +3.3V SCL_IN OR SDA_IN 2.7k 2.7k VCC1 SCL_OUT 2.7k SDA_OUT 2.7k SCL_OUT OR SDA_OUT SDA_IN SCL_IN GND VIN VIN 100pF 100pF 100pF *tPLH 100pF *tPHL *Propagation delay measured between 50% of VCC1 FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FIGURE 7. PROPAGATION DELAY ITRAN_ACC = CV/t V/t is for only the accelerator portion of the waveform *V VCC1 2.7k 2.7k SCL_OUT VCC1 SDA_IN SCL_IN 2nF SDA_OUT GND *V VCC1 X 2.7k 10k 100k X 10k 10k SCL_OUT VCC1 10k SDA_OUT SDA_IN SCL_IN GND *V < V X CC1 (See Figure 22) FIGURE 8. ACCELERATOR CURRENT TEST CIRCUIT FN7560 Rev 6.00 July 11, 2014 FIGURE 9. ACCELERATOR PULSE WIDTH TEST CIRCUIT Page 7 of 18 ISL33001, ISL33002, ISL33003 SDA_IN SDA_OUT U1 M2 M1 U2 RISE TIME ACCELERATOR READY ISL33001 ONLY M5 LOGIC CONTROL START-UP CIRCUITRY VCC1 VCC2 ISL33002 AND ISL33003 EN ISL33001 AND ISL33003 SCL_IN ACC ISL33002 ONLY PRECHARGE CIRCUIT SCL_OUT U3 M4 M3 U4 FIGURE 10. CIRCUIT BLOCK DIAGRAM Application Information The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional Bus Buffers designed to drive heavy capacitive loads in open-drain/open-collector systems. The ISL33001, ISL33002, ISL33003 incorporate rise time accelerator circuitry that improves the rise time for systems that use a passive pull-up resistor for logic HIGH. These devices also feature hot swapping circuitry for applications that require hot insertion of boards into a host system (i.e., servers racks and I/O card modules). The ISL33001 features a logic output flag (READY) that signals the status of the buffer and an EN pin to enable or disable the buffer. The ISL33002 features two separate supply pins for voltage level shifting on the I/O pins and a logic input to disable the rise time accelerator circuitry. The ISL33003 features an EN pin and the level shifting functionality. I2C and SMBUS Compatibility The ISL33001, ISL33002, ISL33003 ICs are I2C and SMBUS compatible devices, designed to work in open-drain/open-collector bus environments. The ICs support both clock stretching and bus arbitration on the SDA and SCL pins. They are designed to operate from DC to more than 400kHz, supporting Fast Mode data rates of the I2C specification.In addition, the buffer rise time accelerators are designed to increase the capacitive drive capability of the bus. With careful choosing of components, driving a bus with the I2C specified maximum bus capacitance of 400pF at 400kHz data rate is possible. FN7560 Rev 6.00 July 11, 2014 Start-Up Sequencing and Hot Swap Circuitry The ISL33001, ISL33002, ISL33003 buffers contain undervoltage lock out (UVLO) circuitry that prevents operation of the buffer until the IC receives the proper supply voltage. For VCC1 and VCC2, this voltage is approximately 1.8V on the rising edge of the supply voltage. Externally driven signals at the SDA/SCL pins are ignored until the device supply voltage is above 1.8V. This prevents communication errors on the bus until the device is properly powered up. The UVLO circuitry is also triggered on the falling edge when the supply voltage drops below 1.7V. Once the IC comes out of the UVLO state, the buffer remains disconnected until it detects a valid connection state. A valid connection state is either a BUS IDLE condition (see Figure 4) or a STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high) along with the SCL_OUT and SDA_OUT pins being logic high. Note: For the ISL33001 and ISL33003 with EN pins, after coming out of UVLO, there will be an additional delay from the enable circuitry if the EN pin voltage is not rising at the same time as the supply pins (see Figure 3) before a valid connection state can be established. Coming out of UVLO but prior to a valid connection state, the SDA and SCL pins are pre-charged to 1V to allow hot insertion. Because the bus at any time can be between 0V and VCC, pre-charging the I/O pins to 1V reduces the maximum differential voltage from the buffer I/O pin and the active bus. Page 8 of 18 ISL33001, ISL33002, ISL33003 The pre-charge circuitry reduces system disturbance when the IC is hot plugged into a live back plane that may have the bus communicating with other devices. performance. The rise time accelerators are only active on the low-to-high transitions and provide an active constant current source to slew the voltage on the pin quickly (Figure 21). Note: For The ISL33001 and ISL33003 with EN pins, the pre-charge circuitry is active only after coming out of UVLO and having the device enabled. The rise time accelerators are triggered immediately after the buffer release threshold (approximately 30% of VCC) on both sides of the buffer is crossed. Once triggered, the accelerators are active for a defined pulse width (Figure 22) with the current source turning off as it approaches the supply voltage. Connection Circuitry Once a valid connection condition is met, the buffer is active and the input stage of the SDA/SCL pins is controlled by external drivers. The output of the buffer will follow the input of the buffer. The directionality of the IN/OUT pins are not exclusive (bi-directional operation) and functionally behave identical to each other. Being a two channel buffer, the SDA and SCL pins also behave identically. In addition, the SDA and SCL portions of the buffer are independent from each other. The SDA pins can be driven in one direction while the SCL pins can be driven opposite. Refer to Figure 10 for the operation of the bi-directional buffer. When the input stage of the buffer on one side is driven low by an external device, the output of the buffer drives an open-drain transistor to pull the `output' pin low. The `output' pin will continue to be held low by the transistor until the external driver on the `input' releases the bus. To prevent the buffer from entering a latched condition where both internal transistors are actively pulling the I/O pins low, the buffer is designed to be active in only one direction. The buffer logic circuitry senses, which input stage is being externally driven low and sets that buffer to be the active one. For example, referring to Figure 10, if SDA_OUT is externally driven low, buffer U2 will be active and buffer U1 is inactive. M1 is turned on to drive SDA_IN low, effectively buffering the signal from SDA_OUT to SDA_IN. The low signal at the input of U1 will not turn M2 on because U1 remains inactive, preventing a latch condition. Buffer Output Low and Offset Voltage By design, when a logic input low voltage is forced on the input of the buffer, the output of the buffer will have an input to output offset voltage. The output voltage of the buffer is determined by Equation 1: V OUT = V IN + V OS + V CC /R PULL-UP r ON (EQ. 1) Where VOS is the buffer internal offset voltage, RPull-Up is the pull-up resistance on the SDA/SCL pin to VCC and rON is the ON-resistance of the buffer's internal NMOS pull-down device. The last term of the equation is the additional voltage drop developed by sink current and the internal resistance of the transistor. The VOS of the buffer can be determined by Figures 19, 20 and is typically 40mV. Reducing the pull-up resistor values increases the sink current and increases the output voltage of the buffer for a given input low voltage (Figures 17, through 20). Rise Time Accelerators The ISL33001, ISL33002, ISL33003 buffer rise time accelerators on the SDA/SCL pins improve the transient performance of the system. Heavy load capacitance or weak pull-up resistors on an Open-Drain bus cause the rise time to be excessively long, which leads to data errors or reduced data rate FN7560 Rev 6.00 July 11, 2014 Enable Pin (ISL33001 and ISL33003) When driven high, the enable pin puts the buffer into its normal operating state. After power-up, EN high will activate the bus pre-charge circuitry and wait for a valid connection state to enable the buffer and the accelerator circuitry. Driving the EN pin low disables the accelerators, disables the buffer so that signals on one side of the buffer will be isolated from the other side, disables the pre-charge circuit and places the device in a low power shutdown state. READY Logic Pin (ISL33001 Only) The READY pin is a digital output flag for signaling the status of the buffer. The pin is the drain of an Open-Drain NMOS. Connect a resistor from the READY pin to VCC1 to provide the high pull-up. The recommended value is 10k. When the buffer is disabled by having the EN pin low or if the start-up sequencing is not complete, the READY pin will be pulled low by the NMOS. When the buffer has the EN pin high and a valid connection state is made at the SDA/SCL pins, the READY pin will be pulled high by the pull-up resistor. The READY pin is capable of sinking 3mA when pulled low while maintaining a voltage of less than 0.4V. ACC Accelerator Pin (ISL33002 Only) The ACC logic pin controls the rise time accelerator circuitry of the buffer. When ACC is driven high, the accelerators are enabled and will be triggered when crossing the buffer release threshold. When ACC is driven low, the accelerators are disabled. For lightly loaded buses, having the accelerators active may cause ringing or noise on the rising edge transition. Disabling the accelerators will have the buffers continue to perform level shifting with the VCC1 and VCC2 supplies and provide capacitance buffering. Propagation Delays On a low-to-high transition, the rising edge signal is determined by the bus pull-up resistor, load capacitance, and the accelerator current from the ISL33001, ISL33002, ISL33003 buffer. Prior to the accelerators becoming active, the buffer is connected and the output voltage will track the input of the buffer. When the accelerators activate the buffer connection is released and the signal on each side of the buffer rises independently. The accelerator current on both sides of the buffer will be equal. If the pull-up resistance on both sides of the buffer are also equal, then differences in the rise time will be proportional to the difference in capacitive loading on the two sides. Page 9 of 18 ISL33001, ISL33002, ISL33003 Because the signals on each side of the buffer rise independently, the propagation delay can be positive or negative. If the input side rises slowly relative to the output (i.e., heavy capacitive loading on the input and light load on the output) then the propagation delay tPLH is negative. If the output side rises slowly relative to the input, tPLH is positive. For high-to-low transitions, there is a finite propagation delay through the buffer from the time an external low on the input drives the NMOS output low. This propagation delay will always be positive because the buffer connect threshold on the falling edge is below the measurement points of the delay. In addition to the propagation delay of the buffer, there will be additional delay from the different capacitive loading of the buffer. Figures 23 and 24 show how the propagation delay from high-tolow, tPHL, is affected by VCC and capacitive loading. The buffer's propagation delay times for rising and falling edge signals must be taken into consideration for the timing requirements of the system. SETUP and HOLD times may need to be adjusted to take into account excessively long propagation delay times caused by heavy bus capacitances. Pull-Up Resistor Selection While the ISL33001, ISL33002, ISL33003 2-Channel buffers are designed to improve the rise time of the bus in passive pull-up systems, proper selection of the pull-up resistor is critical for system operation when a buffer is used. For a bus that is operating normally without active rise time circuitry, using the ISL33001, ISL33002, ISL33003 buffer allows larger pull-up resistor values to reduce sink currents when the bus is driving low. However, choose a pull-up resistor value of no larger than 20k regardless of the bus capacitance seen on the SDA/SCL lines. The Bus Idle or Stop Bit condition requires valid logic high voltages to give a valid connection state. Pull-up resistor values 20k or smaller are recommended to overcome the typical 150k impedance of the pre-charge circuitry, delivering valid high levels. FN7560 Rev 6.00 July 11, 2014 Page 10 of 18 ISL33001, ISL33002, ISL33003 Typical Performance Curves CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise Specified. 2.4 600 2.3 550 T = -40C 2.2 2.0 T = +25C 450 T = +85C 1.9 ICC1 (nA) ICC1 (mA) 500 T = +25C 2.1 1.8 1.7 1.6 T = +85C 400 350 300 250 1.5 200 1.4 150 1.3 1.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 6.0 2.0 2.5 3.0 3.5 4.0 VCC1 (V) 5.0 5.5 6.0 FIGURE 12. ICC1 DISABLED CURRENT vs VCC1 (ISL33001) FIGURE 11. ICC1 ENABLED CURRENT vs VCC1 (ISL33001) 2.4 60 VCC2 = 5.5V 2.3 VCC2 = 5.5V 2.2 50 2.1 T = -40C T = +85C 2.0 40 T = +25C 1.9 ICC1 (nA) ICC1 (mA) 4.5 VCC1 (V) 1.8 1.7 T = +25C 30 1.6 T = +85C 20 1.5 1.4 10 1.3 1.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 2.0 6.0 2.5 3.0 3.5 VCC1 (V) 4.0 4.5 5.0 5.5 6.0 VCC1 (V) FIGURE 13. ICC1 ENABLED CURRENT vs VCC1 (ISL33002 AND ISL33003) FIGURE 14. ICC1 DISABLED CURRENT vs VCC1 (ISL33003) 60 0.24 T = +25C VCC1 = 5.5V VCC1 = 5.5V 0.22 50 T = -40C 40 T = +85C ICC2 (nA) ICC2 (mA) 0.20 0.18 0.16 30 T = +25C T = +85C 20 0.14 10 0.12 0.10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC2 (V) FIGURE 15. ICC2 ENABLED CURRENT vs VCC2 (ISL33002 AND ISL33003) FN7560 Rev 6.00 July 11, 2014 6.0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC2 (V) FIGURE 16. ICC2 DISABLED CURRENT vs VCC2 (ISL33003) Page 11 of 18 6.0 ISL33001, ISL33002, ISL33003 Typical Performance Curves (Continued) CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise 120 120 VCC = 2.3V 100 100 80 80 T = -40C T = +25C 60 VOL (mV) VOL (mV) T = +85C VCC = 2.7V 40 40 VCC = 4.5V VIN = 0V 0 1 2 3 4 5 7 6 VCC = 3.3V VIN = 0V 20 20 0 60 8 9 10 0 0 11 1 2 3 4 IOL (mA) FIGURE 17. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs VCC 90 VCC = 5.5V 80 80 70 70 60 60 50 VCC = 3.3V VCC = 2.3V 40 VOS (mV) VOS (mV) 8 9 10 11 100 90 20 20 0 1 2 3 4 5 6 IOL (mA) 7 8 9 10 0 11 VIN = 0.2V 0 1 2 3 4 5 6 7 8 9 10 11 IOL (mA) FIGURE 20. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs TEMPERATURE 800 11 ACCELERATOR PULSE WIDTH (ns) 12 T = -40C 10 9 T = +85C 7 6 5 T = +25C 4 3 2.0 VCC = 3.3V 10 FIGURE 19. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs VCC 8 T = +85C 40 30 VIN = 0.2V T = -40C T = +25C 50 30 10 ACCELERATOR CURRENT (mA) 7 FIGURE 18. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs TEMPERATURE 100 0 5 6 IOL (mA) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) FIGURE 21. ACCELERATOR PULL-UP CURRENT vs VCC FN7560 Rev 6.00 July 11, 2014 6.0 700 See Figure 9 T = +25C 600 T = -40C T = +85C 500 400 300 200 2.0 2.5 3.0 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 FIGURE 22. ACCELERATOR PULSE WIDTH vs VCC Page 12 of 18 ISL33001, ISL33002, ISL33003 Typical Performance Curves (Continued) 50 40 T = +85C PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 50 RPULL-UP = 2.7k CIN = 10pF COUT = 100pF T = +85C T = +25C 30 20 T = -40C 10 0 2.0 2.5 3.0 CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise 3.5 4.0 4.5 VCC (V) 5.0 5.5 40 30 T = +25C 20 T = -40C VCC = 3.3V RPULL-UP = 10k CIN = 50pF 10 0 0 6.0 FIGURE 23. PROPAGATION DELAY H-L vs VCC 100 200 300 400 500 600 COUT (pF) 700 800 900 FIGURE 24. PROPAGATION DELAY H-L vs COUT Die Characteristics 12 11 SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): VCC = 2.3V CAPACITANCE (pF) VCC = 3.3V GND VCC = 5.5V 10 PROCESS: 0.25m CMOS 9 8 7 6 -30 -10 10 30 50 70 90 TEMPERATURE (C) FIGURE 25. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs VCC (c) Copyright Intersil Americas LLC 2010-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7560 Rev 6.00 July 11, 2014 Page 13 of 18 ISL33001, ISL33002, ISL33003 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE July 11, 2014 FN7560.6 In "Features" on page 1, changed "Low quiescent Current" from "2.2mA" to "2.1mA". On page 4, added "Pb-Free Reflow Profile" entry to "Thermal Info" section. In "Electrical Spec" table on page 4, changed "VCC" to "VCC1" in the "Supply Current from VCC2" row. In "Electrical Spec" table on page 5, for parameter "Input Low Threshold", moved the "TYP" column entry to the "MAX" column. On page 6, Figure 4, clarified the associated notes. On page 7, Figure 8, changed "IACC" to ITRAN_ACC", and noted that the V/t is for the accelerator portion of the waveform. December 19, 2013 FN7560.5 Added Note 13 at the end of the "Elec Spec" table on page 5 as follows: "13. If the Vcc1 and Vcc2 voltages diverge, then the shut-down Icc increases on the higher voltage supply." Added reference "(Note 13)" after "ISL33003 only" in rows for Vcc1 and Vcc2 "Shut-down Supply current" parameters (last 2 rows of "Power Supplies" section) on page 4. October 12, 2012 FN7560.4 Changed "SDA_IN, SCL_IN...0.3V to +(VCC1 + 0.3)V, SDA_OUT, SCL_OUT...0.3V to +(VCC2 + 0.3)V, ENABLE, READY, ACC...0.3V to +(VCC1 + 0.3)V" to "SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY...0.3V to +7V; ENABLE, ACC...0.3V to +(VCC1 + 0.3)V", in the Absolute Maximum Ratings section at the top of page 4. Removed "Pb-free Reflow Profile" and link from "Thermal Information" section at the top of page 4. Added "open drain" and "Connect to 10k pull-up resistor to VCC1.", in Pin Descriptions in the READY section on page 3. October 11, 2011 FN7560.3 Converted to new datasheet template. Changed Title of datasheet from: "2-Wire Bus Buffer With Rise Time Accelerators and Hot Swap Capability" to: I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability Pg 1, added to Related Literature: AN1637, "Level Shifting Between 1.8V and 3.3V Using I2C Buffers" Replaced POD M8.118 Rev 3 with Rev 4 due to the following changes: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36" Replaced POD M8.15 Rev 1 with Rev 3 due to the following changes: Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Figure 3 (was Fig1) - Added: - If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH - If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH and replaced graph September 13, 2010 FN7560.2 Added SOIC package information to datasheet for ISL33001. April 30, 2010 FN7560.1 Changed typical value of "Supply Current from VCC1" on page 4 for ISL33001 only from 2.2mA to 2.1mA. Changed typical value of "Input-Output Offset Voltage" on page 5 from 100mV to 50mV. March 18, 2010 FN7560.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7560 Rev 6.00 July 11, 2014 Page 14 of 18 ISL33001, ISL33002, ISL33003 Package Outline Drawing L8.3x3H 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) Rev 0, 2/08 2.38 1.50 REF 3.00 A PIN #1 INDEX AREA 6 PIN 1 INDEX AREA 6 X 0.50 6 B 1 8 X 0.40 4 2.20 3.00 (4X) 1.64 0.15 5 8 0.10 M C A B TOP VIEW 8 X 0.25 BOTTOM VIEW ( 2.38 ) SEE DETAIL "X" 0 .80 MAX 0.10 C C BASE PLANE SEATING PLANE 0.08 C 2 . 80 ( 2 .20 ) SIDE VIEW ( 1.64 ) C 0.2 REF 8X 0.60 0 . 00 MIN. 0 . 05 MAX. ( 8X 0.25 ) DETAIL "X" ( 6X 0 . 5 ) NOTES: TYPICAL RECOMMENDED LAND PATTERN 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7560 Rev 6.00 July 11, 2014 Page 15 of 18 ISL33001, ISL33002, ISL33003 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 0.10 C 0.75 0.05 C 0.08 C 1 SIDE VIEW 6 1.50 0.10 8 8X 0.30 0.05 8X 0.30 0.10 2.30 0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. FN7560 Rev 6.00 July 11, 2014 Compliant to JEDEC MO-229 WEEC-2 except for the foot length. Page 16 of 18 ISL33001, ISL33002, ISL33003 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.00.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.90.15 3.00.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 0.15 0.25 33 0.85010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN7560 Rev 6.00 July 11, 2014 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 17 of 18 ISL33001, ISL33002, ISL33003 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8 0 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW "B" TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW "A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN7560 Rev 6.00 July 11, 2014 Page 18 of 18