Features
•Usable for Automotive 12V/24V and Industrial Applications
•Maximum High-speed Data Transmissions up to 1 MBaud
•Fully Compatible with ISO 11898
•Controlled Slew Rate
•Standby Mode
•TXD Input Compatible to 3.3V
•Short-circuit Protection
•Overtemperature Protection
•High Voltage Bus Lines Protection, –40V to +40V
•High Speed Differential Receiver Stage with a Wide Common Mode Range,
–10V to +10V, for High Electromagnetic Immunity (EMI)
•Fully Controlled Bus Lines, CANH and CANL to Minimize
Electromagnetic Emissions (EME)
•High ESD Protection at CANH, CANL HBM 8 kV, MM 300V
1. Description
The ATA6660 is a monolithic circuit based on the Atmel’s Smart Power BCD60-III
technology. It is especially designed for high speed CAN-Controller (CAN-C) differen-
tial mode data transmission between CAN-Controllers and the physical differential bus
lines.
Figure 1-1. Block Diagram
4 RXD
5 VREF
7 CANH
6 CANL
8 RS
2 GND
3 VCC
1 TXD TXD input stage
Constant slope/
standby
Overtemperature
and Short circuit
protection
Driver
Reference
Voltage
0.5*VCC
Receiver
High-speed Can
Transceiver
ATA6660
4582D–BCD–06/06
2
4582D–BCD–06/06
ATA6660
2. Pin Configuration
Figure 2-1. Pinning SO8
TXD
GND
VCC
RXD
RS
CANH
CANL
VREF
1
2
3
4
8
7
6
5
Table 2-1. Pin Description
Pin Symbol Function
1 TXD Transmit data input
2 GND Ground
3 VCC Supply voltage
4 RXD Receive data output
5 VREF Reference voltage output
6 CANL Low level CAN voltage input/output
7 CANH High level CAN voltage input/output
8 RS Switch standby mode/normal mode
3
4582D–BCD–06/06
ATA6660
3. Functional Description
The ATA6660 is a monolithic circuit based on Atmel’s Smart Power BCD60-III technology. It is
especially designed for high-speed differential mode data transmission in harsh environments
like automotive and industrial applications. Baudrate can be adjusted up to 1 Mbaud. The
ATA6660 is fully compatible to the ISO11898, the developed standard for high speed CAN-C
(Controller Area Network) communication.
3.1 Voltage Protection and ESD
High voltage protection circuitry on both line pins, CANH (pin 7) and CANL (pin 6), allow bus line
voltages in the range of –40V to +40V. ESD protection circuitry on line pins allow HBM = 8 kV,
MM = 300V. The implemented high voltage protection on bus line output/input pins (7/6) makes
the ATA6660 suitable for 12V automotive applications as well as 24V automotive applications.
3.2 Slope Control
A fixed slope is adjusted to prevent unsymmetrical transients on bus lines causing EMC prob-
lems. Controlled bus lines, both CANH and CANL signal, will reduce radio frequency
interference to a minimum. In well designed bus configurations the filter design costs can be
reduced dramatically.
3.3 Overcurrent Protection
In the case of a line shorts, like CANH to GND, CANL to VCC, integrated short current limitation
allows a maximum current of ICANH_SC or ICANL_SC. If junction temperature rises above 165°C an
internal overtemperature protection circuitry shuts down both output stages, the receiver will
stay activated.
3.4 Standby Mode
The ATA6660 can be switched to standby mode by forcing the voltage VRS > 0.87 ×VCC. In
standby mode the supply current will reduce dramatically, supply current during standby mode is
typical 600 µA (IVCC_stby). Transmitting data function will not be supported, but the opportunity will
remain to receive data. A high-speed comparator is listening for activities on the bus. A domi-
nant bus signal will force the output RXD to a low level in typical tdRXDL = 400 ns. If the RS pin is
not connected, causing through a broken connection to the controller, the ATA6660 will switch to
standby mode automatically.
3.5 High-speed Receiver
In normal mode a fast receiver circuitry combined with a resistor network is able to detect differ-
ential bus line voltages Vrec_th > 0.9V as dominant bit, differential bus line voltages Vrec_th <0.5V
as recessive bit.
The wide receiver common mode range, –10V to +10V, combined with a symmetrical differential
receiver stage offers high immunity against electromagnetic interference. A typical hysteresis of
70 mV is implemented. Dominant differential bus voltages forces RXD output (pin 4) to low level,
recessive differential bus voltages to high level.
4
4582D–BCD–06/06
ATA6660
3.6 TXD Input
The input stage pin 1 (TXD) is compatible for 3.3V output levels from new controller families.
Pull-up resistance (25 kΩ) forces the IC to recessive mode, if TXD-Pin is not connected. TXD
low signal drives the transmitter into dominant state.
3.7 Transmitter
A integrated complex compensation technique allows stable data transmission up to 1 MBaud.
Low level on TXD input forces bus line voltages CANH to 3.5V, CANL to 1.5V with a termination
resistor of 60Ω. In the case of a line short circuit, like CANH to GND, CANL to VCC, integrated
short current limitation circuitry allows a maximum current of 150 mA. If junction temperature
rises above typical 163°C an internal overtemperature protection shuts down both output stages,
the receive mode will stay activated.
3.8 Split Termination Concept
With a modified bus termination (see Figure 8-3 on page 10) a reduction of emission and a
higher immunity of the bus system can be achieved. The one 120Ω resistor at the bus line end
nodes is split into two resistors of equal value, i.e., two resistors of 60Ω. The resistors for the
stub nodes is recommended with two resistors of 1.3 kΩ. (for example 8 stub nodes and 2 bus
end nodes) Notice: The bus load of all the termination resistors has to stay within the range of
50Ω to 65Ω.
The common mode signal at the centre tap of the termination is connected to ground via a
capacitor of e.g., Csplit = 10 nF to 100 nF. A separate ground lead to the ground pin of the mod-
ule connector is recommended.
5
4582D–BCD–06/06
ATA6660
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Conditions Min. Max. Unit
Supply voltage VCC –0.3 +6 V
DC voltage at pins 1, 4, 5 and 8 VTXD, VREF
, VRS,
VRXD –0.3 VCC +0.3 V
DC voltage at pins 6 and 7 VCANH, VCANL 0V < VCC < 5.25V;
no time limit –40.0 +40.0 V
Transient voltage at pins 6 and 7 –150 +100 V
Storage temperature TStg –55 +150 °C
Operating ambient temperature Tamb –40 +125 °C
ESD classification All pins HBM ESD S.5.1
MM JEDEC A115A
±3000
±200
V
V
ESD classification Pin 6, 7 versus
pin 2
HBM 1.5 kΩ, 100 pF
MM 0Ω, 200 pF
±8000
±300
V
V
5. Thermal Resistance
Parameters Symbol Value Unit
Thermal resistance from junction to ambient RthJA 160 K/W
6. Truth Table
VCC TXD RS CANH CANL Bus State RXD
4.75V to 5.25V 0 < 0.3 × VCC 3.5V 1.5V Dominant 0
4.75V to 5.25V 1 (or floating) < 0.3 × VCC 0.5 × VCC 0.5 × VCC Recessive 1
4.75V to 5.25V X > 0.87 × VCC 0.5 × VCC 0.5 × VCC Recessive 1
7. RS (Pin 8) Functionality
Slope Control Mode Voltage and Current Levels
VRS > 0.87 × VCC Standby IRS < | 10 µA |
VRS < 0.3 × VCC Constant slope control IRS ≤500 µA
6
4582D–BCD–06/06
ATA6660
8. Electrical Characteristics
VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified.
All voltages referenced to ground (pin 2); positive input current.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Supply Current
1.1 Supply current
dominant
VTXD = 0V
VRS = 0V 3I
vcc_dom 45 60 mA A
1.2 Supply current
recessive
VTXD = 5V
VRS = 0V 3I
vcc_rec 10 15 mA A
1.3 Supply current stand-by VRS = 5V 3 Ivcc_stby 600 980 µA A
2 Transmitter Data Input TXD
2.1 HIGH level input
voltage
VTXD = 5V
VRS = 0V 1V
TXDH 2V
CC + 0.3 V A
2.2 LOW level input voltage VTXD = 0V
VRS = 0V 1V
TXDL –0.3 +1 V A
2.3 HIGH level input current VTXD = VCC 1I
IH –1 0 µA A
2.4 LOW level input voltage VTXD = 0V 1 IIL –500 -50 µA A
3 Receiver Data Output RXD
3.1 High level output
voltage IRXD = –100 µA 4 VRXDH 0.8 × VCC VCC VA
3.2 Low level output
voltage IRXD = 1 mA 4 VRXDL 00.2 × VCC VA
3.3 Short current at RXD VTXD = 5V
VRXD = 0V 4I
RXDs1 –3 -1 mA A
3.4 Short current at RXD VTXD = 0V
VRXD = 5V 4I
RXDs2 26mAA
4 Reference Output Voltage VREF
4.1 Reference output
voltage normal mode
VRS = 0V;
–50 µA < I5 < 50 µA 5V
ref_no 0.45 VCC 0.55 VCC VA
4.2 Reference output
voltage standby mode
VRS = 5 V;
–5 µA < I5 < 5 µA 5V
ref_stby 0.4 × VCC 0.6 VCC VA
5 DC Bus Transmitter CANH; CANL
5.1 Recessive bus voltage VTXD = VCC; no load 6, 7 VCANH;
VCANL 2.0 2.5 3.0 V A
5.2 IO(CANH)(reces)
IO(CANL)(reces)
–40V < VCANH;
VCANL < 40V;
0V < VCC < 5.25V
6, 7 IO_reces –5 +5 mA A
5.3 CANH output voltage
dominant VTXD = 0V 6, 7 VCANH 2.8 3.5 4.5 V A
5.4 CANL output voltage
dominant VTXD = 0V 6, 7 VCANL 0.5 1.5 2.0 V A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7
4582D–BCD–06/06
ATA6660
5.5
Differential bus output
voltage
(VCANH – VCANL)
VTXD = 0V;
RL = 45Ω to 60Ω;
VCC = 4.9V
6, 7 Vdiffdom 1.5 2 3.0 V A
5.6 VTXD = VCC; no load 6, 7 Vdiffrec –500 +50 mV A
5.7 Short-circuit CANH
current
VCANH = –10V
TXD = 0V 6, 7 ICANH_SC –35 –100 mA A
5.8 Short-circuit CANL
current
VCANL = 18V
TXD = 0V 6, 7 ICANL_SC 50 - 150 mA A
6 DC Bus Receiver CANH; CANL
6.1
Differential receiver
threshold voltage
normal mode
–10V < VCANH < +10V
–10V < VCANL < +10V 6, 7 Vrec_th 0.5 0.7 0.9 V A
6.2
Differential receiver
threshold voltage
stand-by mode
VRS = VCC 6, 7 Vrec_th_stby 0.5 0.7 0.9 V A
6.3 Differential input
hysteresis 6, 7 Vdiff(hys) 70 mV A
6.4
CANH and CANL
common mode input
resistance
6, 7 Ri51525kΩA
6.5 Differential input
resistance 6, 7 Rdiff 10 30 100 kΩA
6.6
Matching between
CANH and CANL
common mode input
resistance
6, 7 Ri_m –3 +3 % A
6.7 CANH, CANL input
capacitance 6, 7 Ci20 pF D
6.8 Differential input
capacitance 6, 7 Cdiff 10 pF D
6.9 CANH, CANL input
leakage input current
VCC = 0V
VCANH = 3.5V
VCANL = 1.5V
6, 7 ILI(CANH);
ILI(CANL)
250 µA A
7 Thermal Shut-down
7.1
Shut-down junction
temperature for
CANH/CANL
TJ(SD) 150 163 175 °C B
7.2
Switch on junction
temperature for
CANH/CANL
TJ(SD) 140 154 165 °C B
7.3 Temperature hysteresis THys 10 K B
8. Electrical Characteristics (Continued)
VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified.
All voltages referenced to ground (pin 2); positive input current.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
4582D–BCD–06/06
ATA6660
8 Timing Characteristics Normal Mode, VRS ≤0.3 ×VCC (see Figure 8-1 on page 9)
8.1 Delay TXD to bus
active VRS = 0V td(TXD-BUS_ON) 120 180 ns A
8.2 Delay TXD to bus
inactive VRS = 0V td(TXD-BUS_OFF) 50 100 ns A
8.3 Delay TXD to RXD,
recessive to dominant VRS = 0V 6, 7 td_activ(TXD-RXD) 200 420 ns A
8.4 Delay TXD to RXD,
dominant to recessive VRS = 0V td_inactiv(TXD-RXD) 180 460 ns A
8.5
Difference between
Delay TXD to RXD
dominant to Delay
recessive
tdiff = td_activ(TXD-RXD)
– td_inactiv(TXD-RXD) tdiff –280 80 ns A
9 Timing Characteristics Stand-by Mode VRS ≥0.87 × VCC
9.1 Bus dominant to RXD
low in stand-by mode VRS = VCC 4t
dRxDL 300 450 ns A
9.2
Wake up time after
stand-by mode (time
delay between stand-by
to normal mode and to
bus dominant)
TXD = 0V
VRS from 0V to VCC 6, 7 Twake_up 2µsA
10 Standby/Normal Mode Selectable via RS (Pin 8)
10.1 Input voltage for normal
mode VRS = VCC 8V
RS 0.3 × VCC VA
10.2 Input current for normal
mode VRS = 0V 8 IRS –700 µA A
10.3 Input voltage for
stand-by mode 8V
stby 0.87 × VCC VA
8. Electrical Characteristics (Continued)
VCC = 4.75V to 5.25V; Tamb = –40°C to +125°C; RBus = 60Ω; unless otherwise specified.
All voltages referenced to ground (pin 2); positive input current.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9
4582D–BCD–06/06
ATA6660
Figure 8-1. Timing Diagrams
TXD
Vdiff
CANH
CANL
RXD
HIGH
LOW
dominant
(bus activ)
recessive
(bus inactive)
HIGH
LOW
0.7VCC
0.3VCC
0.9V
0.5V
t
d (TXD_bus_on)
t
d_activ(TXD_RXD)
t
d_inactiv (TXD_RXD)
t
d (TXD_bus_off)
dominant
CANH
dominant
CANL
10
4582D–BCD–06/06
ATA6660
Figure 8-2. Test Circuit for Timing Characteristics
Figure 8-3. Bus Application with Split Termination Concept
2
3
4
8
7
6
5
1
ATA6660
RXD
VCC
GND
TXD RS
CANH
CANL
Vref
C
L
=100pFR
L
=62
C=15pF
C=100nFC=47µF
+ 5V
234
8765
1
ATA6660
RXD
VCC
GND
TXD RS
CANH
CANL
Vref
C=15pF
C=100nFC=47µF
+ 5V
234
8765
1
ATA6660
TXD
GND
VCC
RXD
RS
CANH
CANL
Vref
C=15pF
CAN
Controller
R
L
=60
R
L
=60
C
SPLIT
=10nF
R
L
=60
R
L
=60
C
SPLIT
=10nF
bus line
end node
bus line
end node
R
L
=1,3k
C
SPLIT
=10nF
R
L
=1,3k
bus line
stub node
C=47µF C=100nF
CAN
Controller
+ 5V
11
4582D–BCD–06/06
ATA6660
10. Package Information
11. Revision History
9. Ordering Information
Extended Type Number Package Remarks
ATA6660-TAPY SO8 Taped and reeled, Pb-free
ATA6660-TAQY SO8 Taped and reeled, Pb-free
technical drawings
according to DIN
specifications
Package SO8
Dimensions in mm
5.00
4.85
0.4
1.27
3.81
1.4
0.25
0.10
5.2
4.8
3.7
3.8
6.15
5.85
0.2
85
14
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4582D-BCD-06/06
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
• Table “Ordering Information” on page 11 changed
4582C-BCD-09/05
• Put datasheet in a new template
• Pb-free logo on page 1 added
• Heading rows on Table “Absolute Maximum Ratings” on page 5 added
• Table “Ordering Information” on page 11 changed
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