FEATURES DESCRIPTION
APPLICATIONS
12-Bit
Pipelined
ADC
Error
Correction
Logic
Timing/Duty Cycle
Adjust (PLL)
Internal
Reference
3-State
Output
S/H
D11A
·
·
·
D0A
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
S/H
D11B
·
·
·
D0B
AVDD OEA
VDRV
SDATA SEN SCLK SEL
OVRA
OVRB
INA
CM
INA
INT/EXT CLK
DVA
DVB
REFT
REFB
INB
VIN
OEB
STPD
INB
ADS5232
VIN
Serial
Interface
DISABLE_PLL
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
Dual, 12-Bit, 65MSPS, +3.3VAnalog-to-Digital Converter
•Single +3.3V Supply
The ADS5232 is a dual, high-speed, high dynamicrange, 12-bit pipelined analog-to-digital converter•High SNR: 70.7dBFS at f
IN
= 5MHz
(ADC). This converter includes a high-bandwidth•Total Power Dissipation:
sample-and-hold amplifier that gives excellentInternal Reference: 371mW
spurious performance up to and beyond the NyquistExternal Reference: 335mW
rate. The differential nature of the sample-and-hold•Internal or External Reference
amplifier and ADC circuitry minimizes even-orderharmonics and gives excellent common-mode noise•Low DNL: ±0.3LSB
immunity.•Flexible Input Range: 1.5V
PP
to 2V
PP
The ADS5232 provides for setting the full-scale range•TQFP-64 Package
of the converter without any external referencecircuitry. The internal reference can be disabled,allowing low-drive, external references to be used for•Communications IF Processing
improved tracking in multichannel systems.•Communications Base Stations
The ADS5232 provides an over-range indicator flag•Test Equipment
to indicate an input signal that exceeds the full-scale•Medical Imaging
input range of the converter. This flag can be used to•Video Digitizing
reduce the gain of front-end gain control circuitry.There is also an output enable pin to allow for•CCD Digitizing
multiplexing and testing on a PC board.
The ADS5232 employs digital error correctiontechniques to provide excellent differential linearity fordemanding imaging applications. The ADS5232 isavailable in a TQFP-64 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS5232IPAG Tray, 160ADS5232 TQFP-64 PAG –40°C to +85°C ADS5232IPAG
ADS5232IPAGT Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
Supply Voltage Range, AVDD –0.3V to +3.8VSupply Voltage Range, VDRV –0.3V to +3.8VVoltage Between AVDD and VDRV –0.3V to +0.3VVoltage Applied to External REF Pins –0.3V to +2.4VAnalog Input Pins
(2)
–0.3V to min [3.3V, (AVDD + 0.3V)]Case Temperature +100°COperating Free-Air Temperature Range, T
A
–40°C to +85°CLead Temperature +260°CJunction Temperature +105°CStorage Temperature –65°C +150°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.(2) The DC voltage applied on the input pins should not go below –0.3V. Also, the DC voltage should be limited to the lower of either 3.3Vor (AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25 Ωshould be added in series witheach of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be definedeither as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3Vand +3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should notexceed 1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
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RECOMMENDED OPERATING CONDITIONS
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
ADS5232
MIN TYP MAX UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD 3.0 3.3 3.6 VOutput Driver Supply Voltage, VDRV 3.0 3.3 3.6 VREF
T
— External Reference Mode 1.875 2.0 2.05 VREF
B
— External Reference Mode 0.95 1.0 1.125 VREFCM = (REF
T
+ REF
B
)/2 – External Reference Mode
(1)
V
CM
± 50mV VReference = (REF
T
– REF
B
) – External Reference Mode 0.75 1.0 1.1 VAnalog Input Common-Mode Range
(1)
V
CM
± 50mV V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample RatePLL Enabled (default) 20 65 MSPSPLL Disabled 2 30
(2)
MSPSADCLK Duty Cycle
PLL Enabled (default) 45 55 MSPSLow-Level Voltage Clock Input 0.6 VHigh-Level Voltage Clock Input 2.2 VOperating Free-Air Temperature, T
A
–40 +85 °CThermal Characteristics:
θ
JA
42.8 °C/Wθ
JC
18.7 °C/W
(1) These voltages need to be set to 1.5V ± 50mV if they are derived independent of V
CM
.(2) When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variationis acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then theduty cycle needs to be maintained within 48%–52% duty cycle.
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ELECTRICAL CHARACTERISTICS
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
ADS5232
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
No Missing Codes TestedDNL Differential Nonlinearity f
IN
= 5MHz –0.9 ±0.3 +0.9 LSBINL Integral Nonlinearity f
IN
= 5MHz –2.5 ±0.4 +2.5 LSBOffset Error
(1)
–0.75 ±0.2 +0.75 %FSOffset Temperature Coefficient
(2)
±6 ppm/°CFixed Attenuation in Channel
(3)
1 %FSFixed Attenuation Matching Across Channels 0.01 0.2 dBGain Error/Reference Error
(4)
–3.5 ±1.0 +3.5 % FSGain Error Temperature Coefficient ±40 ppm/°C
POWER REQUIREMENTS
(5)
Internal Reference
Power Dissipation
(5)
Analog Only (AVDD) 260 297 mWOutput Driver (VDRV) 111 142 mWTotal Power Dissipation 371 439 mW
External Reference
Power Dissipation Analog Only (AVDD) 224 mWOutput Driver (VDRV) 111 mWTotal Power Dissipation 335 mWVREF
T
1.875 2 2.05 mWVREF
B
0.95 1 1.125 mW
Total Power-Down 88 mW
REFERENCE VOLTAGES
VREF
T
Reference Top (internal) 1.9 2.0 2.1 VVREF
B
Reference Bottom (internal) 0.9 1.0 1.1 VV
CM
Common-Mode Voltage 1.4 1.5 1.6 VV
CM
Output Current
(6)
±50mV Change in Voltage ±2 mAVREF
T
Reference Top (external) 1.875 VVREF
B
Reference Bottom (external) 1.125 VExternal Reference Common-Mode V
CM
± 50mV VExternal Reference Input Current
(7)
1.0 mA
(1) Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (2048). Offset error isexpressed in terms of % of full-scale.(2) If the offset at temperatures T
1
and T
2
are O
1
and O
2
, respectively (where O
1
and O
2
are measured in LSBs), the offset temperaturecoefficient in ppm/°C is calculated as (O
1
– O
2
)/(T
1
– T
2
) × 1E6/4096.(3) Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. When the differential voltage atthe analog input pins is changed from –V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale code(4096LSB) by the extent of this fixed attenuation. NOTE: V
REF
is defined as (REF
T
– REF
B
).(4) The reference voltages are trimmed at production so that (VREF
T
– VREF
B
) is within ± 35mV of the ideal value of 1V. This specificationdoes not include fixed attenuation.(5) Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.(6) The V
CM
output current specified is the drive of the V
CM
buffer if loaded externally.(7) Average current drawn from the reference pins in the external reference mode.
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ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
ADS5232
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Differential Input Capacitance 3 pFAnalog Input Common-Mode Range V
CM
± 0.05 VDifferential Input Voltage Range Internal Reference 2.02 V
PP
External Reference 2.02 × (VREF
T
– VREF
B
) V
PP
Voltage Overload Recovery Time
(8)
3 CLK Cycles–3dBFS Input, 25 ΩSeriesInput Bandwidth 300 MHzResistance
DIGITAL DATA INPUTS
Logic Family +3V CMOS CompatibleV
IH
High-Level Input Voltage V
IN
= 3.3V 2.2 VV
IL
Low-Level Input Voltage V
IN
= 3.3V 0.6 VC
IN
Input Capacitance 3 pF
DIGITAL OUTPUTS
Data Format Straight Offset Binary
(9)
Logic Family CMOSLogic Coding Straight Offset Binary or BTCLow Output Voltage (I
OL
= 50µA) +0.4 VHigh Output Voltage (I
OH
= 50µA) +2.4 V3-State Enable Time 2 Clocks3-State Disable Time 2 ClocksOutput Capacitance 3 pF
SERIAL INTERFACE
SCLK Serial Clock Input Frequency 20 MHz
CONVERSION CHARACTERISTICS
Sample Rate 20 65 MSPSData Latency 6 CLK Cycles
(8) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice thefull-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of theADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code valuewhen the pulse is switched from ON (high) to OFF (low).(9) Option for Binary Two’s Complement Output.
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AC CHARACTERISTICS
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = maximum specified, 50% clock dutycycle, AVDD = 3.3V, VDRV = 3.3V, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unless otherwise noted.
ADS5242
PARAMETER CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS
f
IN
= 5MHz 75 86 dBc
SFDR Spurious-Free Dynamic Range f
IN
= 32.5MHz 85 dBc
f
IN
= 70MHz 83 dBc
f
IN
= 5MHz 82 92 dBc
HD
2
2nd-Order Harmonic Distortion f
IN
= 32.5MHz 87 dBc
f
IN
= 70MHz 85 dBc
f
IN
= 5MHz 75 86 dBc
HD
3
3rd-Order Harmonic Distortion f
IN
= 32.5MHz 85 dBc
f
IN
= 70MHz 83 dBc
f
IN
= 5MHz 68 70.7 dBFS
SNR Signal-to-Noise Ratio f
IN
= 32.5MHz 69.5 dBFS
f
IN
= 70MHz 67.5 dBFS
f
IN
= 5MHz 67.5 70.3 dBFS
SINAD Signal-to-Noise and Distortion f
IN
= 32.5MHz 69 dBFS
f
IN
= 70MHz 67 dBFS
5MHz Full-Scale Signal Applied to 1 Channel;Crosstalk –85 dBcMeasurement Taken on the Channel with No Input Signal
f
1
= 4MHz at –7dBFSTwo-Tone, Third-OrderIMD3 90.9 dBFSIntermodulation Distortion
f
2
= 5MHz at –7dBFS
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Analog
Input
CLK
DATA[D11:D0]
DV
OE
DATA D11:D0
tOE
tOE
tDV
t1t2
tC
tA
N + 1
N + 2 N + 4
N + 3
N
TIMING CHARACTERISTICS
(1)
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TIMING DIAGRAM
Typical values at T
A
= +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
65MSPS With PLL ON
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time
(2)
2 3.2 ns
t
2
Data Hold Time
(3)
6.3 8.5 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time
(4)
0.5 2 3 ns
Data Valid (DV) Duty Cycle 30 40 55 %
t
DV
Input Clock Rising to DV Fall Edge 10 11.5 14 ns
(1) Specifications assured by design and characterization; not production tested.(2) Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.(3) Measured from the 50% point of the falling edge of DV to the data becoming invalid.(4) Measured between 20% to 80% of logic levels.
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ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TIMING CHARACTERISTICS (continued)Typical values at T
A
= +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
50MSPS With PLL ON
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 3.2 4.5 ns
t
2
Data Hold Time 10 11 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3 ns
Data Valid (DV) Duty Cycle 30 40 55 %
t
DV
Input Clock Rising to DV Fall Edge 11.5 13.5 15.5 ns
40MSPS With PLL ON
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 3.7 5.5 ns
t
2
Data Hold Time 11.5 13.5 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3 ns
Data Valid (DV) Duty Cycle 30 40 55 %
t
DV
Input Clock Rising to DV Fall Edge 13.5 16 18.5 ns
30MSPS With PLL OFF
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 8 10 ns
t
2
Data Hold Time 14 19 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3.5 ns
Data Valid (DV) Duty Cycle 30 45 55 %
t
DV
Input Clock Rising to DV Fall Edge 16 19 21 ns
20MSPS With PLL ON
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 10 12 ns
t
2
Data Hold Time 20 25 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3.5 ns
Data Valid (DV) Duty Cycle 30 45 55 %
t
DV
Input Clock Rising to DV Fall Edge 20 25 30 ns
20MSPS With PLL OFF
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 10 12 ns
t
2
Data Hold Time 20 25 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3.5 ns
Data Valid (DV) Duty Cycle 30 45 55 %
t
DV
Input Clock Rising to DV Fall Edge 20 25 30 ns
2MSPS With PLL OFF
t
A
Aperture Delay 2.1 ns
Aperture Jitter 1.0 ps
t
1
Data Setup Time 150 200 ns
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SERIAL INTERFACE TIMING
NOTE: Data is shifted in MSB first.
Start Sequence
t1t7
t6
D7
(MSB) D6 D5 D4 D3 D2 D1 D0
t2
t3
t4
t5
CLK
SEN
SCLK
SDATA
Outputs change on
next rising clock edge
after SEN goes high.
Data latched on
each rising edge of SCLK.
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TIMING CHARACTERISTICS (continued)Typical values at T
A
= +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
t
2
Data Hold Time 200 250 ns
t
D
Data Latency 6 Clocks
t
DR
, t
DF
Data Rise/Fall Time 0.5 2 3.5 ns
Data Valid (DV) Duty Cycle 30 45 55 %
t
DV
Input Clock Rising to DV Fall Edge 200 225 250 ns
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
Serial CLK Period 50 nst
2
Serial CLK High Time 20 nst
3
Serial CLK Low Time 20 nst
4
Data Setup Time 5 nst
5
Data Hold Time 5 nst
6
SEN Fall to SCLK Rise 8 nst
7
SCLK Rise to SEN Rise 8 ns
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ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
SERIAL REGISTER MAP: Shown for the Case Where Serial Interface is Used
(1)
ADDRESS DATA DESCRIPTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 X X X 0Normal Mode
0 0 0 0 X X X 1Power-Down Both Channels
0 0 0 0 X X 0X Straight Offset Binary Output
0 0 0 0 X X 1X Binary Two's Complement Output
0000X0X X Channel B Digital Outputs Enabled
0000X1X X Channel B Digital Outputs Tri-Stated
00000X X X Channel A Digital Outputs Enabled
00001X X X Channel A Digital Outputs Tri-Stated
00100 0 0 0 Normal Mode
00100 1 0 0 All Digital Outputs Set to '1'
00101 0 0 0 All Digital Outputs Set to '0'
00110 0 X 0 Normal Mode
00111 X X 0 Channel A Powered Down
0011X 1 X 0 Channel B Powered Down
0 0 1 1 X X 00 PLL Enabled (default)
0 0 1 1 X X 10 PLL Disabled
(1) X = don't care.
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RECOMMENDED POWER-UP SEQUENCING
t1
t3
t5t6
t4t7
t8
t2
AVDD (3V to 3.6V)
VDRV (3V to 3.6V)
Device Ready
For ADC Operation
Device Ready
For ADC Operation
Device Ready
For Serial Register Write
Start of Clock
AVDD
VDRV
SEL
SEN
CLK
NOTE: 10µs < t1< 50ms; 10µs < t2< 50ms; −10ms < t3< 10ms; t4> 10ms; t5> 100ns; t6> 100ns; t7> 10ms; and t8> 100µs.
STPD Device Fully
Powers Down Device Fully
Powers Up
500µs
1µs
NOTE: The shown power−up time is based on 1µF bypass capacitors on the reference pins.
See the Theory of Operation section for details.
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
Shown for the case where the serial interface is used.
POWER-DOWN TIMING
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PIN CONFIGURATION
Top View TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
AGND
AVDD
STPD/SDATA
GND
VDRV
OEA/SCLK
MSBI/SEN
VDRV
OVRA
D11_A (MSB)
D10_A
D9_A
D8_A
D7_A
D6_A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEL
AGND
AVDD
GND
VDRV
OEB
GND
VDRV
OVRB
D0_B (LSB)
D1_B
D2_B
D3_B
D4_B
D5_B
D6_B
AGND
INB+
INB−
AGND
ISET
AGND
AGND
AVDD
INT/EXT
AGND
REFB
REFT
CM
INA−
INA+
AGND
D7_B
D8_B
D9_B
D10_B
D11_B (MSB)
DVB
GND
CLK
GND
DVA
D0_A (LSB)
D1_A
D2_A
D3_A
D4_A
D5_A
64 63 62 61 60 59 58 57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
ADS5232
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
PIN DESCRIPTIONSNAME PIN # I/O DESCRIPTION
AGND 2, 47–49, 55, 58, 59, 61, 64 Analog Ground
AVDD 3, 46, 57 Analog Supply
CLK 24 I Clock Input
CM 52 O Common-Mode Voltage Output
D0_A (LSB) 27 O Data Bit 12 (D0), Channel A
D1_A 28 O Data Bit 11 (D1), Channel A
D2_A 29 O Data Bit 10 (D2), Channel A
D3_A 30 O Data Bit 9 (D3), Channel A
D4_A 31 O Data Bit 8 (D4), Channel A
D5_A 32 O Data Bit 7 (D5), Channel A
D6_A 33 O Data Bit 6 (D6), Channel A
D7_A 34 O Data Bit 5 (D7), Channel A
D8_A 35 O Data Bit 4 (D8), Channel A
D9_A 36 O Data Bit 3 (D9), Channel A
D10_A 37 O Data Bit 2 (D10), Channel A
D11_A (MSB) 38 O Data Bit 1 (D11), Channel A
D0_B (LSB) 10 O Data Bit 12 (D0), Channel B
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ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
PIN DESCRIPTIONS (continued)NAME PIN # I/O DESCRIPTION
D1_B 11 O Data Bit 11 (D1), Channel B
D2_B 12 O Data Bit 10 (D2), Channel B
D3_B 13 O Data Bit 9 (D3), Channel B
D4_B 14 O Data Bit 8 (D4), Channel B
D5_B 15 O Data Bit 7 (D5), Channel B
D6_B 16 O Data Bit 6 (D6), Channel B
D7_B 17 O Data Bit 5 (D7), Channel B
D8_B 18 O Data Bit 4 (D8), Channel B
D9_B 19 O Data Bit 3 (D9), Channel B
D10_B 20 O Data Bit 2 (D10), Channel B
D11_B (MSB) 21 O Data Bit 1 (D11), Channel B
DV
A
26 O Data Valid, Channel A
DV
B
22 O Data Valid, Channel B
GND 4, 7, 23, 25, 44 Output Buffer Ground
IN
A
50 I Analog Input, Channel A
IN
A
51 I Complementary Analog Input, Channel A
IN
B
63 I Analog Input, Channel B
IN
B
62 I Complementary Analog Input, Channel B
Reference Select; 0 = External (Default), 1 = Internal; Force high to set for internal referenceINT/ EXT 56 I
operation.
I
SET
60 O Bias Current Setting Resistor of 56.2k Ωto Ground
When SEL = 0, MSBI (Most Significant Bit Invert)MSBI/SEN 41 I 1 = Binary Two's Complement, 0 = Straight Offset Binary (Default)When SEL = 1, SEN (Serial Write Enable)
When SEL = 0, OE
A
(Output Enable Channel A)OE
A
/SCLK 42 I 0 = Enabled (Default), 1 = Tri-StateWhen SEL = 1, SCLK (Serial Write Clock)
OE
B
6 I Output Enable, Channel B (0 = Enabled [Default], 1 = Tri-State)
OVR
A
39 O Over-Range Indicator, Channel A
OVR
B
9 O Over-Range Indicator, Channel B
REF
B
54 I/O Bottom Reference/Bypass (2 Ωresistor in series with a 0.1 µF capacitor to ground)
REF
T
53 I/O Top Reference/Bypass (2 Ωresistor in series with a 0.1 µF capacitor to ground)
Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OE
A
, andSTPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serialinterface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. SerialSEL 1 I
registers can be programmed using these three signals. When used in this mode of operation, it isessential to provide a low-going pulse on SEL in order to reset the serial interface registers as soonas the device is powered up. SEL therefore also has the functionality of a RESET signal.
When SEL = 0, STPD (Power Down)STPD/SDATA 45 I 0 = Normal Operation (Default), 1 = EnabledWhen SEL = 1, SDATA (Serial Write Data)
VDRV 5, 8, 40, 43 Output Buffer Supply
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DEFINITION OF SPECIFICATIONS
Minimum Conversion RateAnalog Bandwidth
Signal-to-Noise and Distortion (SINAD)
Aperture Delay
SINAD 10Log10 PS
PNPD
Aperture Uncertainty (Jitter)
Clock Duty Cycle
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
SNR 10Log10 PS
PN
Spurious-Free Dynamic RangeEffective Number of Bits (ENOB)
Two-Tone, Third-Order Intermodulation
ENOB SINAD 1.76
6.02
Integral Nonlinearity (INL)
Maximum Conversion Rate
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
This is the minimum sampling rate where the ADCstill works.The analog input frequency at which the spectralpower of the fundamental frequency (as determinedby FFT analysis) is reduced by 3dB.
SINAD is the ratio of the power of the fundamental(P
S
) to the power of all the other spectral componentsincluding noise (P
N
) and distortion (P
D
), but notThe delay in time between the rising edge of the input
including DC.sampling clock and the actual time at which thesampling occurs.
SINAD is either given in units of dBc (dB to carrier)The sample-to-sample variation in aperture delay.
when the absolute power of the fundamental is usedas the reference, or dBFS (dB to full-scale) when thepower of the fundamental is extrapolated to thefull-scale range of the converter.Pulse width high is the minimum amount of time thatthe ADCLK pulse should be left in logic ‘1’ state toachieve rated performance. Pulse width low is theminimum time that the ADCLK pulse should be left in
SNR is the ratio of the power of the fundamental (P
S
)a low state (logic ‘0’). At a given clock rate, these
to the noise floor power (P
N
), excluding the power atspecifications define an acceptable clock duty cycle.
DC and the first eight harmonics.
An ideal ADC exhibits code transitions that areexactly 1 LSB apart. DNL is the deviation of any
SNR is either given in units of dBc (dB to carrier)single LSB transition at the digital output from an
when the absolute power of the fundamental is usedideal 1 LSB step at the analog input. If a device
as the reference, or dBFS (dB to full-scale) when theclaims to have no missing codes, it means that all
power of the fundamental is extrapolated to thepossible codes (for a 12-bit converter, 4096 codes)
full-scale range of the converter.are present over the full operating range.
The ratio of the power of the fundamental to theThe ENOB is a measure of converter performance as
highest other spectral component (either spur orcompared to the theoretical limit based on
harmonic). SFDR is typically given in units of dBc (dBquantization noise.
to carrier).
Distortion
Two-tone IMD3 is the ratio of power of thefundamental (at frequencies f
1
and f
2
) to the power ofINL is the deviation of the transfer function from a
the worst spectral component of third-orderreference line measured in fractions of 1 LSB using a
intermodulation distortion at either frequency 2f
1
– f
2best straight line or best fit determined by a least
or 2f
2
– f
1
. IMD3 is either given in units of dBc (dB tosquare curve fit. INL is independent from effects of
carrier) when the absolute power of the fundamentaloffset, gain or quantization errors.
is used as the reference, or dBFS (dB to full-scale)when the power of the fundamental is extrapolated tothe full-scale range of the converter.The encode rate at which parametric testing isperformed. This is the maximum sampling rate wherecertified operation is given.
14
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TYPICAL CHARACTERISTICS
Amplitude (dBFS)
Input Frequency (MHz)
0
−20
−40
−60
−80
−100
−120 019.5 266.5 13 32.5
fIN = 1MHz
SNR = 71.4dBFS
SINAD = 71.3dBFS
SFDR = 87.5dBc
Amplitude (dBFS)
Input Frequency (MHz)
0
−20
−40
−60
−80
−100
−120 019.5 266.5 13 32.5
fIN = 5MHz
SNR = 71.4dBFS
SINAD = 71.3dBFS
SFDR = 84.5dBc
Amplitude (dBFS)
Input Frequency (MHz)
0
−20
−40
−60
−80
−100
−120 019.5 266.5 13 32.5
fIN = 32.5MHz
SNR =70.6dBFS
SINAD = 70.4dBFS
SFDR = 88.6dBc
Amplitude (dBFS)
Input Frequency (MHz)
0
−20
−40
−60
−80
−100
−120 019.5 266.5 13 32.5
fIN = 70MHz
SNR = 67.7dBFS
SINAD = 67.6dBFS
SFDR = 83.9dBc
DNL (LSB)
Code
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4 02048 30721024 4096
fIN = 5MHz
Amplitude (dBFS)
Input Frequency (MHz)
0
−20
−40
−60
−80
−100
−120 019.5 266.5 13 32.5
f1= 4MHz (−7dBFS)
f2= 5MHz (−7dBFS)
IMD = −97.9dBFS
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 1. Figure 2.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 3. Figure 4.
INTERMODULATION DISTORTION DIFFERENTIAL NONLINEARITY
Figure 5. Figure 6.
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INL (LSB)
Code
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0 02048 30721024 4096
fIN = 5MHz
IAVDD, IDVDD (mA)
Sample Rate (MHz)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
020 25 30 35 40 45 50 55 60 65 70
fIN = 5MHz
IAVDD
IVDRV
SNR (dBFS), SFDR (dBc)
Input Frequency (MHz)
110
100
90
80
70
60
50
40
30
020 8040 60 100
SNR
SFDR
SNR, SINAD (dBFS), SFDR (dBc)
Clock Frequency (MHz)
95
90
85
80
75
70
65
60
55 20 25 30 35 40 45 50 55 60 65 70
SNR
SFDR
SINAD
fIN = 5MHz
SNR (dBFS), SFDR (dBc)
Input Frequency (MHz)
110
100
90
80
70
60
50
40
30
040 60 8020 100
SNR
SFDR
External Reference:
REF = 2V
T
REF = 1V
B
SNR (dBFS), SFDR (dBc)
Duty Cycle (%)
95
90
85
80
75
70
65
60 30 35 50 55 60 6540 45 70
fIN = 5MHz
SNR
SFDR
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS (continued)T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
INTEGRAL NONLINEARITY IAVDD, IVDRV vs CLOCK FREQUENCY
Figure 7. Figure 8.
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY DYNAMIC PERFORMANCE vs INPUT FREQUENCY
Figure 9. Figure 10.
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLEDYNAMIC PERFORMANCE vs INPUT FREQUENCY WITH PLL ENABLED (default)
Figure 11. Figure 12.
16
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SNR (dBFS), SFDR (dBc)
Temperature (C)
95
90
85
80
75
70
65
60
55−40 −15 +60+10 +35 +85
fIN = 5MHz
SNR
SFDR
Power Dissipation (mW)
Temperature (C)
405
390
375
360
345
330−40 +10 +35 +60
−15 +85
fIN = 5MHz
SNR, SFDR (dBc), SNR (dBFS)
Input Amplitude (dBFS)
100
90
80
70
60
50
40
30
20
10
0−70 −60 −30 −20 −10
−50 −40 0
fIN = 5MHz
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
Samples
Code
4000
3500
3000
2500
2000
1500
1000
500
0
N−5
N−4
N−3
N−2
N−1
N
N + 1
N + 2
N + 3
N + 4
N + 5
SNR, SFDR (dBc), SNR (dBFS)
Input Amplitude (dBFS)
100
90
80
70
60
50
40
30
20
10
0−70 −60 −30 −20 −10
−50 −40 0
fIN = 32.5MHz
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS (continued)T
MIN
= –40°C and T
MAX
= +85°C. Typical values are at T
A
= +25°C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
POWER DISSIPATION vs TEMPERATUREDYNAMIC PERFORMANCE vs TEMPERATURE
Figure 13. Figure 14.
OUTPUT NOISE SWEPT INPUT POWER
Figure 15. Figure 16.
SWEPT INPUT POWER
Figure 17.
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APPLICATION INFORMATION
THEORY OF OPERATION INPUT CONFIGURATION
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
The ADS5232 is a dual-channel, simultaneous The analog input for the ADS5232 consists of asampling analog-to-digital converter (ADC). Its low differential sample-and-hold architecture implementedpower and high sampling rate of 65MSPS is achieved using a switched capacitor technique; see Figure 18 .using a state-of-the-art switched capacitor pipeline The sampling circuit consists of a low-pass RC filterarchitecture built on an advanced low-voltage CMOS at the input to filter out noise components thatprocess. The ADS5232 operates from a +3.3V supply potentially could be differentially coupled on the inputvoltage for both its analog and digital supply pins. The inputs are sampled on two 4pF capacitors.connections. The ADC core of each channel consists The RLC model is illustrated in Figure 18 .of a combination of multi-bit and single-bit internalpipeline stages. Each stage feeds its data into thedigital error correction logic, ensuring excellentdifferential linearity and no missing codes at the12-bit level. The conversion process is initiated by the
If the application requires a signal conversion from arising edge of the external clock. Once the signal is
single-ended source to drive the ADS5232captured by the input sample-and-hold amplifier, the
differentially, an RF transformer could be a goodinput sample is sequentially converted within the
solution. The selected transformer must have apipeline stages. This process results in a data latency
center tap in order to apply the common-mode DCof six clock cycles, after which the output data is
voltage (V
CM
) necessary to bias the converter inputs.available as a 12-bit parallel word, coded in either
AC grounding the center tap will generate thestraight offset binary (SOB) or binary two's
differential signal swing across the secondarycomplement (BTC) format. Since a common clock
winding. Consider a step-up transformer to takecontrols the timing of both channels, the analog
advantage of signal amplification without thesignal is sampled simultaneously. The data on the
introduction of another noise source. Furthermore,parallel ports is updated simultaneously as well.
the reduced signal swing from the source may lead toFurther processing can be timed using the individual
improved distortion performance. The differentialdata valid output signal of each channel. The
input configuration may provide a noticeableADS5232 features internal references that are
advantage for achieving good SFDR performancetrimmed to ensure a high level of accuracy and
over a wide range of input frequencies. In this mode,matching. The internal references can be disabled to
both inputs (IN and IN) of the ADS5232 see matchedallow for external reference operation.
impedances.
Figure 19 illustrates the schematic for the suggestedtransformer-coupled interface circuit. The componentvalues of the RC low-pass filter may be optimizeddepending on the desired roll-off frequency.
18
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5nH
to 9nH
3.2pF
to 4.8pF
IN OUT
INP1.5pF to
2.5pF
1Ω
15Ω
to 25Ω
5nH
to 9nH
INN1.5pF to
2.5pF
1Ω
15Ω
to 25Ω60Ω
to 120Ω
1.5pF
to 1.9pF
IN OUT
3.2pF
to 4.8pF
IN OUT
15Ω
to 25Ω15Ω
to 25Ω60Ω
to 120Ω
IN OUT
IN
OUT
15Ωto 35Ω
IN OUT
IN OUT
OUTP
OUTN
Switches that are ON
in SAMPLE phase.
Switches that are ON
in HOLD phase.
VIN IN
IN CM
+1.5V
24.9Ω
24.9Ω
0.1µF
22pF
RT
1:n
0.1µF
RG
R2
R1
OPA690 49.9Ω
1/2
ADS5232
One Channel of Two
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
Figure 18. Input Circuitry
Figure 19. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer
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DC-Coupled Input with Differential Amplifier
REFERENCE CIRCUIT
Internal Reference
1µF
CF
CF
1/2
ADS5232
THS4503
RISO
RISO
RS
VS
RG
RT
RF
RF
VOCM
10µF 0.1µF
0.1µF
IN
IN
CM
RG
AVDD
+5V
REFTCM REFB
ISET
INT/EXTADS5232
0.1µF 2.2µF
+ +
2Ω2Ω
56kΩ
AVDD
2.2µF 0.1µF
Input Over-Voltage Recovery
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
Applications that have a requirement for DC-couplinga differential amplifier, such as the THS4503, can beused to drive the ADS5232; this design is shown in
All bias currents required for the proper operation ofFigure 20 . The THS4503 amplifier easily allows a
the ADS5232 are set using an external resistor at I
SETsingle-ended to differential conversion, which reduces
(pin 60), as shown in Figure 21 . Using a 56.2k Ωcomponent cost.
resistor on I
SET
generates an internal referencecurrent of about 20 µA. This current is mirroredinternally to generate the bias current for the internalblocks. While a 5% resistor tolerance is adequate,deviating from this resistor value alters and degradesdevice performance. For example, using a largerexternal resistor at I
SET
reduces the reference biascurrent and thereby scales down the device operatingpower.
Figure 20. Using the THS4503 with the ADS5232
In addition, the V
OCM
pin on the THS4503 can bedirectly tied to the common-mode pin (CM) of theADS5232 to set up the necessary bias voltage for theconverter inputs. In the circuit example shown inFigure 20 , the THS4503 is configured for unity gain. Ifrequired, a higher gain can easily be achieved as wellby adding small capacitors (such as 10pF) in parallelwith the feedback resistors to create a low-pass filter.Since the THS4503 is driving a capacitive load, small
Figure 21. Internal Reference Circuitseries resistors in the output ensure stable operation.Further details of this and the overall operation of theTHS4503 may be found in its product data sheet
As part of the internal reference circuit, the ADS5232(available for download at www.ti.com ). In general,
provides a common-mode voltage output at pin 52,differential amplifiers provide a high-performance
CM. This common-mode voltage is typically +1.5V.driver solution for baseband applications, and other
While this is similar to the common-mode voltagedifferential amplifier models may be selected
used internally within the ADC pipeline core, thedepending on the system requirements.
CM-pin has an independent buffer amplifier, whichcan deliver up to ±2mA of current to an externalcircuit for proper input signal level shifting andbiasing. In order to obtain optimum dynamicThe differential full-scale input range supported by the
performance, the analog inputs should be biased toADS5232 is 2V
PP
. For a nominal value of V
CM
the recommended common-mode voltage (1.5V).(+1.5V), IN and IN can swing from 1V to 2V. The
While good performance can be maintained over aADS5232 is especially designed to handle an
certain CM-range, larger deviations may compromiseover-voltage differential peak-to-peak voltage of 4V
device performance and could also negatively affect(2.5V and 0.5V swings on IN and IN). If the input
the overload recovery behavior. Using the internalcommon-mode voltage is not considerably different
reference mode requires the INT/ EXT pin to befrom V
CM
during overload (less than 300mV),
forced high, as shown in Figure 21 .recovery from an over-voltage input condition isexpected to be within three clock cycles. All of the
The ADS5232 requires solid high-frequencyamplifiers in the sample-and-hold stage and the ADC
bypassing on both reference pins, REF
T
and REF
B
;core are especially designed for excellent recovery
see Figure 21 . Use ceramic 0.1 µF capacitors (sizefrom an overload signal.
0603, or smaller), located as close as possible to thepins.
20
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External Reference
SNR 20LOG10 1
2fINtJA
(1)
PLL CONTROL
OUTPUT INFORMATION
CLOCK INPUT
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
dominant in maintaining a good signal-to-noise ratio(SNR). This condition is particularly critical inThe ADS5232 also supports the use of external
IF-sampling applications; for example, where thereference voltages. External reference voltage mode
sampling frequency is lower than the input frequencyinvolves applying an external top reference at REF
T
(under-sampling). The following equation can be used(pin 53) and a bottom reference at REF
B
(pin 54).
to calculate the achievable SNR for a given inputSetting the ADS5232 for external reference mode
frequency and clock jitter (t
JA
in ps
RMS
):also requires taking the INT/ EXT pin low. In thismode, the internal reference buffer is tri-stated. Sincethe switching current for the two ADC channelscomes from the externally-forced references, it is
The ADS5232 will enter into a power-down mode ifpossible for the device performance to be slightly
the sampling clock rate drops below a limit oflower than when the internal references are used. It
approximately 2MSPS. If the sampling rate isshould be noted that in external reference mode, V
CM
increased above this threshold, the ADS5232 willand I
SET
continue to be generated from the internal
automatically resume normal operation.bandgap voltage, as they are in the internal referencemode. Therefore, it is important to ensure that thecommon-mode voltage of the externally-forcedreference voltages matches to within 50mV of V
CM
The ADS5232 has an internal PLL that is enabled by(+1.5V
DC
).
default. The PLL enables a wide range of clock dutycycles. Good performance is obtained for duty cyclesThe external reference circuit must be designed to
up to 40%–60%, though the ensured electricaldrive the internal reference impedance seen between
specifications presume that the duty cycle is betweenthe REF
T
and REF
B
pins. To establish the drive
45%–55%. The PLL automatically limits the minimumrequirements, consider that the external reference
frequency of operation to 20MSPS. For operationcircuit needs to supply an average switching current
below 20MSPS, the PLL can be disabled byof at least 1mA. This dynamic switching current
programming the internal registers through the serialdepends on the actual device sampling rate and the
interface. With the PLL disabled, the clock speed cansignal level. The external reference voltages can vary
go down to 2MSPS. With the PLL disabled, the clockas long as the value of the external top reference
duty cycle needs to be constrained closer to 50%.stays within the range of +1.875V to +2.0V, and theexternal bottom reference stays within +1.0V to+1.125V. Consequently, the full-scale input range canbe set between 1.5V
PP
and 2V
PP
(FSR = 2x [REF
T
–
The ADS5232 provides two channels with 12 dataREF
B
] ).
outputs (D11 to D0, with D11 being the MSB and D0the LSB), data-valid outputs (DV
A
, DV
B
, pin 26 andpin 22, respectively), and individual out-of-rangeindicator output pins (OVR
A
/OVR
B
, pin 39 and pin 9,The ADS5232 requires a single-ended clock source.
respectively).The clock input, CLK, represents a CMOS-compatiblelogic input with an input impedance of about 5pF. For
The output circuitry of the ADS5232 has beenhigh input frequency sampling, it is recommended to
designed to minimize the noise produced byuse a clock source with very low jitter. A low-jitter
transients of the data switching, and in particular itsclock is essential in order to preserve the excellent ac
coupling to the ADC analog circuitry.performance of the ADS5232. The converter itself isspecified for a low 1.0ps (rms) jitter. Generally, as theinput frequency increases, clock jitter becomes more
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DATA OUTPUT FORMAT (MSBI)
OUTPUT LOADING
OUTPUT ENABLE ( OE)
SERIAL INTERFACE
OVER-RANGE INDICATOR (OVR)
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
range. It will change to high if the applied signalexceeds the full-scale range. It should be noted thatThe ADS5232 makes two data output formats
each of the OVR outputs is updated along with theavailable: the Straight Offset Binary code (SOB) or
data output corresponding to the particular sampledthe Binary Two's Complement code (BTC). The
analog input voltage. Therefore, the OVR state isselection of the output coding is controlled by the
subject to the same pipeline delay as the digital dataMSBI (pin 41). Because the MSBI pin has an internal
(six clock cycles).pull-down, the ADS5232 will operate with the SOBcode as its default setting. Forcing the MSBI pin highwill enable BTC coding. The two code structures areidentical, with the exception that the MSB is inverted
It is recommended that the capacitive loading on thefor BTC format; as shown in Table 1 .
data output lines be kept as low as possible,preferably below 15pF. Higher capacitive loading willcause larger dynamic currents as the digital outputsare changing. Such high current surges can feedDigital outputs of the ADS5232 can be set to
back to the analog portion of the ADS5232 andhigh-impedance (tri-state), exercising the output
adversely affect device performance. If necessary,enable pins, OE
A
(pin 42), and OE
B
(pin 6). Internal
external buffers or latches close to the converterpull-downs configure the output in enable mode for
output pins may be used to minimize the capacitivenormal operation. Applying a logic high voltage will
loading.disable the outputs. Note that the OE-function is notdesigned to be operated dynamically (that is, as afast multiplexer) because it may lead to corruptconversion results. Refer to the Electrical
The ADS5232 has a serial interface that can be usedCharacteristics table to observe the specified tri-state
to program internal registers. The serial interface isenable and disable times.
disabled if SEL is connected to 0.
When the serial interface is to be enabled, SELserves the function of a RESET signal. After theIf the analog input voltage exceeds the full-scale supplies have stabilized, it is necessary to give therange set by the reference voltages, an over-range device a low-going pulse on SEL. This results in allcondition exists. The ADS5232 incorporates a internal registers resetting to their default value of 0function that monitors the input voltage and detects (inactive). Without a reset, it is possible that registersany such out-of-range condition. This operation may be in their non-default state on power-up. Thisfunctions for each of the two channels independently. condition may cause the device to malfunction.The current state can be read at the over-rangeindicator pins (pins 9 and 39). This output is lowwhen the input voltage is within the defined input
Table 1. Coding Table for Differential Input Configuration and 2V
PP
Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0) BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT D11............D0 D11............D0
+FS (IN = +2V, IN = +1V) 1111 1111 1111 0111 1111 1111+1/2 FS 1100 0000 0000 0100 0000 0000Bipolar Zero (IN = IN = CMV) 1000 0000 0000 0000 0000 0000–1/2 FS 0100 0000 0000 1100 0000 0000–FS (IN = +1V, IN = +2V) 0000 0000 0000 1000 0000 0000
22
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POWER-DOWN MODE
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
capacitances on REF
T
and REF
B
less than 1 µF, thereference voltages settle to within 1% of theirThe ADS5232 has a power-down pin, STPD (pin 45).
steady-state values in less than 500 µs. Either of theThe internal pull-down is in default mode for the
two channels can also be selectively powered-downdevice during normal operation. Forcing the STPD pin
through the serial interface when it is enabled.high causes the device to enter into power-downmode. In power-down mode, the reference and clock The ADS5232 also has an internal circuit thatcircuitry as well as all the channels are powered monitors the state of stopped clocks. If ADCLK isdown. Device power consumption drops to less than stopped for longer than 250ns, or if it runs at a speed90mW. As previously mentioned, the ADS5232 also less than 2MHz, this monitoring circuit generates aenters into a power-down mode if the clock speed logic signal that puts the device in a partialdrops below 2MSPS (see the Clock Input section). power-down state. As a result, the powerconsumption of the device is reduced when CLK isWhen STPD is pulled high, the internal buffers driving
stopped. The recovery from such a partialREF
T
and REF
B
are tri-stated and the outputs are
power-down takes approximately 100 µs. Thisforced to a voltage roughly equal to half of the
constraint is described in Table 2 .voltage on AV
DD
. Speed of recovery from thepower-down mode depends on the value of theexternal capacitance on the REF
T
and REF
B
pins. For
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION TYP REMARKS
Recovery from power-down mode (STPD = 1 to STPD = 0). 500 µs Capacitors on REF
T
and REF
B
less than 1 µF.Recovery from momentary clock stoppage ( < 250ns). 10 µsRecovery from extended clock stoppage ( > 250ns). 100 µs
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LAYOUT AND DECOUPLING
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
output buffer supply pins, VDRV. In order to minimizeCONSIDERATIONS the lead and trace inductance, the capacitors shouldbe located as close to the supply pins as possible.Proper grounding and bypassing, short lead length,
Where double-sided component mounting is allowed,and the use of ground planes are particularly
they are best placed directly under the package. Inimportant for high frequency designs. Achieving
addition, larger bipolar decoupling capacitors (2.2 µFoptimum performance with a fast sampling converter
to 10 µF), effective at lower frequencies, may also besuch as the ADS5232 requires careful attention to the
used on the main supply pins. They can be placed onprinted circuit board (PCB) layout to minimize the
the PCB in proximity (< 0.5") to the ADC.effects of board parasitics and to optimize componentplacement. A multilayer board usually ensures best If the analog inputs to the ADS5232 are drivenresults and allows convenient component placement. differentially, it is especially important to optimizetowards a highly symmetrical layout. Small traceThe ADS5232 should be treated as an analog
length differences may create phase shifts,component and the supply pins connected to clean
compromising a good distortion performance. For thisanalog supplies. This layout ensures the most
reason, the use of two single op amps rather thanconsistent performance results, since digital supplies
one dual amplifier enables a more symmetrical layoutoften carry a high level of switching noise, which
and a better match of parasitic capacitances. The pincould couple into the converter and degrade device
orientation of the ADS5232 quad-flat package followsperformance. As mentioned previously, the output
aflow-through design, with the analog inputs locatedbuffer supply pins (VDRV) should also be connected
on one side of the package while the digital outputsto a low-noise supply. Supplies of adjacent digital
are located on the opposite side. This designcircuits may carry substantial current transients. The
provides a good physical isolation between thesupply voltage should be filtered before connecting to
analog and digital connections. While designing thethe VDRV pin of the converter. All ground pins should
layout, it is important to keep the analog signal tracesdirectly connect to an analog ground.
separated from any digital lines to prevent noisecoupling onto the analog portion.Because of its high sampling frequency, theADS5232 generates high frequency current transients
Single-ended clock lines must be short and shouldand noise (clock feed-through) that are fed back into
not cross any other signal traces.the supply and reference lines. If not sufficientlybypassed, this feed-through adds noise to the Short circuit traces on the digital outputs will minimizeconversion process. All AV
DD
pins may be bypassed capacitive loading. Trace length should be kept shortwith 0.1 µF ceramic chip capacitors (size 0603, or to the receiving gate (< 2") with only one CMOS gatesmaller). A similar approach may be used on the connected to one digital output.
24
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PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS5232IPAG ACTIVE TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5232IPAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5232IPAGT ACTIVE TQFP PAG 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5232IPAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5232IPAGT TQFP PAG 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5232IPAGT TQFP PAG 64 250 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,17
0,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,05
0,95
11,80
12,20
1,20 MAX
10,20 SQ
17
32
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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