SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The SN54ABT841 and SN74ABT841A 10-bit
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The ten transparent D-type latches provide true
data at their outputs.
A buffered output-enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT841A is characterized for operation from –40°C to 85°C.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN54ABT841 . . . JT OR W PACKAGE
SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
SN54ABT841 . . . FK PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3Q
4Q
5Q
NC
6Q
7Q
8Q
3D
4D
5D
NC
6D
7D
8D
426
14 15 16 17 18
9D
10D
GND
NC
LE
10Q
9Q
2D
1D
OE
NC
1Q
2Q
VCC
NC – No internal connection
SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUT
OE LE DQ
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
EN
1
7
6D 8
7D 9
8D 10
9D
1D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D 4
3D 5
4D 6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
C1
13
LE
11
10D 10Q
14
logic diagram (positive logic)
OE
To Seven Other Channels
1
13
223
LE
1D
C1
1D 1Q
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT841 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT841A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT841 SN74ABT841A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate 5 5 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT841 SN74ABT841A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
IIVCC = 0 to 5.5 V, VI = VCC or GND ±1±1±1µA
IOZPU‡VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZPD‡VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA
IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA
V55VI0
Outputs high 1** 250** 280 250 µA
ICC VCC = 5.5 V, IO = 0,
VI=V
CC or GND
Outputs low 24** 38** 4538mA
VI
=
VCC
or
GND
Outputs disabled 0.5** 250** 280 250 µA
#
VCC
=
5.5 V,
Outputs enabled 1.5 1.5 1.5 mA
∆ICC
#
VCC
=
5
.
5
V
,
One input at 3.4 V, Outputs disabled 250** 280 250 µA
Other inputs at VCC or GND Control inputs 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V 4 pF
CoVO = 2.5 V or 0.5 V 7 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT841A.
†All typical values are at VCC = 5 V.
‡This parameter is characterized, but not production tested.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This limit may vary among suppliers.
#This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°CSN54ABT841 SN74ABT841A UNIT
MIN MAX MIN MAX MIN MAX
twPulse duration, LE high or low 3.3 3.3 3.3 ns
t
Setu
p
time data before LE↓
High 2.5 2.5 2.5
ns
t
su
Set
u
p
time
,
data
before
LE↓
Low 1.5 1.5 1.5
ns
th
Hold time data after LE↓
High 1.5 1.5 1.5
ns
t
h
Hold
time
,
data
after
LE↓
Low 1.5 2 1.5
ns
SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT841
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1†4.1 5.5 1†6.8
ns
tPHL
D
Q
1.5†4 5.5 1.5†6.8
ns
tPLH
LE
Q
1.6†4.1 6.6† 1.6† 7.4
ns
tPHL
LE
Q
2†4.6 6.2 2†6.8
ns
tPZH
OE
Q
1 3 4.9†1 5.8
ns
tPZL
OE
Q
2.2 4.1 5.7†2.2 6.5
ns
tPHZ
OE
Q
2†4.7 6.2 2†7.2
ns
tPLZ
OE
Q
1.5†4.6 6.1 1.5†6.6
ns
†This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT841A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1.4†4.1 5.5 1.4†6.2†
ns
tPHL
D
Q
1.5†4 5.5 1.5†6.2
ns
tPLH
LE
Q
2.1†4.1 5.9†2.1†6.5†
ns
tPHL
LE
Q
2.4†4.6 6.2 2.4†6.7
ns
tPZH
OE
Q
1 3 4.7†1 5.3†
ns
tPZL
OE
Q
2.2 4.1 5.7†2.2 6.3†
ns
tPHZ
OE
Q
2.6†4.7 6.2 2.6†7.1
ns
tPLZ
OE
Q
1.9†4.6 6.1 1.9†6.5
ns
†This data sheet limit may vary among suppliers.
SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS196D – FEBRUAR Y 1991 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2. 5 n s, t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9676901Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9676901Q3A
SNJ54ABT
841FK
5962-9676901QKA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QK
A
SNJ54ABT841W
5962-9676901QLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QL
A
SNJ54ABT841JT
SN74ABT841ADBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI -40 to 85
SN74ABT841ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841ADW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A
SN74ABT841ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A
SN74ABT841ADWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A
SN74ABT841ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A
SN74ABT841ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A
SN74ABT841ANT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT841ANT
SN74ABT841ANTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT841ANT
SN74ABT841APW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74ABT841APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841APWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI -40 to 85
SN74ABT841APWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SN74ABT841APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A
SNJ54ABT841FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9676901Q3A
SNJ54ABT
841FK
SNJ54ABT841JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QL
A
SNJ54ABT841JT
SNJ54ABT841W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QK
A
SNJ54ABT841W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT841 :
•Catalog: SN74ABT841
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT841ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74ABT841ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74ABT841APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT841ADBR SSOP DB 24 2000 367.0 367.0 38.0
SN74ABT841ADWR SOIC DW 24 2000 367.0 367.0 45.0
SN74ABT841APWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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