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FEATURES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCC
PC3OUT
SIGIN
PC2OUT
R2
R1
DEMOUT
VCOIN
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74LV4046AHIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
•Choice of Three Phase Comparators •ESD Protection Exceeds JESD 22– Exclusive OR – 2000-V Human-Body Model (A114-A)– Edge-Triggered J-K Flip-Flop – 200-V Machine Model (A115-A)– Edge-Triggered RS Flip-Flop – 1000-V Charged-Device Model (C101)•Excellent VCO Frequency Linearity•VCO-Inhibit Control for ON/OFF Keying andfor Low Standby Power Consumption•Optimized Power-Supply Voltage Range From3 V to 5.5 V•Wide Operating Temperature Range . . . –40 °Cto 125 °C•Latch-Up Performance Exceeds 250 mA PerJESD 17
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and theCD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO)and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are commonto each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) tosmall voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the inputamplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCOlinearity is achieved by the use of linear operational amplifier techniques.
ORDERING INFORMATION
(1)
T
A
PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 50 SN74LV4046ANSSOP – NS 74LV4046AReel of 2000 SN74LV4046ANSRTube of 40 SN74LV4046ADSOIC – D LV4046A–40 °C to 125 °C Reel of 2500 SN74LV4046ADRTube of 90 SN74LV4046APWTSSOP – PW LW046AReel of 2000 SN74LV4046APWRTVSOP – DGV Reel of 2000 SN74LV4046ADGVR LW046A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 PCP
OUT
Phase comparator pulse output2 PC1
OUT
Phase comparator 1 output3 COMP
IN
Comparator input4 VCO
OUT
VCO output5 INH Inhibit input6 C1
A
Capacitor C1 connection A7 C1
B
Capacitor C1 connection B8 GND Ground (0 V)9 VCO
IN
VCO input10 DEM
OUT
Demodulator output11 R
1
Resistor R1 connection12 R
2
Resistor R2 connection13 PC2
OUT
Phase comparator 2 output14 SIG
IN
Signal input15 PC3
OUT
Phase comparator 3 output16 V
CC
Positive supply voltage
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
DC supply voltage range –0.5 7 VV
I
Input voltage range –0.5 V
CC
+ 0.5 VV
O
Output voltage range –0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –20 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output curent V
O
= 0 to V
CC
±35 mAI
CC
DC V
CC
or ground current ±70 mAD package 73DGV package 120θ
JA
Package thermal impedance
(2)
°C/WNS package 64PW package 108T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The package thermal impedance is calculated in accordance with JESD 51-7.
PARAMETER MIN MAX UNIT
T
A
Operating free-air temperature –40 125 °CV
CC
Supply voltage 3 5.5 VV
I
, V
O
DC input or output voltage 0 V
CC
V
2
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Electrical Specifications
SN74LV4046AHIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
TEST CONDITIONSPARAMETER V
CC
(V) MIN TYP MAX UNITV
I
(V) I
O
(mA)
VCO
3 to 3.6 V
CC
×0.7V
IH
High-level input voltage INH V4.5 to 5.5 V
CC
×0.73 to 5.5 V
CC
×0.3V
IL
Low-level input voltage INH V4.5 to 5.5 V
CC
×0.33 to 3.6 V
CC
– 0.1CMOS –0.05High-level
V
OH
VCO
OUT
V
IL
or V
IH
4.5 to 5.5 V
CC
– 0.1 Voutput voltage
TTL –12 4.5 to 5.5 3.83 to 3.6 0.1CMOS 0.05VCO
OUT
4.5 to 5.5 0.1Low-level
V
OL
V
IL
or V
IH
VTTL 12 4.5 to 5.5 0.55output voltage
C1A, C1B
12 4.5 to 5.5 0.65(test purposes only)I
I
Input leakage current INH, VCO
IN
V
CC
or GND 5.5 ±1µAR1 range
(1)
3 to 5.5 3 50 k ΩR2 range
(1)
3 to 5.5 3 50 k Ω3 to 3.6 40C1 capacitance range No Limit pF4.5 to 5.5 403 to 3.6 1.1 1.9Operating voltage Over the range specifiedVCO
IN
Vrange for R1 for linearity
(2)
4.5 to 5.5 1.1 3.2
Phase Comparator
3 to 3.6 V
CC
×0.7DC-coupled high-level SIG
IN
,V
IH
input voltage COMP
IN
4.5 to 5.5 V
CC
×0.73 to 3.6 V
CC
×0.3SIG
IN
,V
IL
DC-coupled low-level input voltage VCOMP
IN
4.5 to 5.5 V
CC
×0.3–0.05 3 to 5.5 V
CC
– 0.1CMOSHigh-level PCP
OUT
,V
OH
V
IL
or V
IH
–6 3 to 3.6 2.48 Voutput voltage PCN
OUT
TTL –12 4.5 to 5.5 3.83 to 3.6 0.10.02CMOSLow-level PCP
OUT
,
4.5 to 5.5 0.1V
OL
V
IL
or V
IH
Voutput voltage PCN
OUT
4 4.5 to 5.5 0.4TTL
3 to 3.6 ±11SIG
IN
,I
I
Input leakage current V
CC
or GND µACOMP
IN
4.5 to 5.5 ±29I
OZ
3-state off-state current PC2
OUT
V
IL
or V
IH
3 to 5.5 ±5µA3 800SIG
IN
, V
I
at self-bias operatingR
I
Input resistance k ΩCOMP
IN
point, V
I
= 0.5 V
4.5 250
Demodulator
R
S
> 300 k Ω, Leakage 3 to 3.6 50 300R
S
Resistor range current can influence k Ω4.5 to 5.5 50 300V
DEMOUT
V
I
= V
VCOIN
= V
CC/2
, 3 to 3.6 ±30V
OFF
Offset voltage VCO
IN
to V
DEM
Values taken over R
S
mV4.5 to 5.5 ±20rangePins 3, 5, and 14 at V
CC
,I
CC
Quiescent device current Pin 9 at GND, I
I
at pins 3 5.5 50 µAand 14 to be excluded
(1) The value for R1 and R2 in parallel should exceed 2.7 k Ω.(2) The maximum operating voltage can be as high as V
CC
– 0.9 V; however, this may result in an increased offset voltage.
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Switching Specifications
SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
C
L
= 50 pF, Input t
r
, t
f
= 6 ns
V
CCPARAMETER TEST CONDITIONS MIN TYP MAX UNIT(V)
Phase Comparator
3 to 3.6 135SIG
IN
, COMP
IN
tot
PLH
, t
PHL
Propagation delay nsPC1
OUT
4.5 to 5.5 503 to 3.6 300SIGIN, COMP
IN
tot
PLH
, t
PHL
Propagation delay nsPCP
OUT
4.5 to 5.5 603 to 3.6 200SIG
IN
, COMP
IN
tot
PLH
, t
PHL
Propagation delay nsPC3
OUT
4.5 to 5.5 503 to 3.6 75t
THL
, t
TLH
Output transition time ns4.5 to 5.5 153 to 3.6 270SIG
IN
, COMP
IN
tot
PZH
, t
PZL
3-state output enable time nsPC2
OUT
4.5 to 5.5 543 to 3.6 320SIG
IN
, COMP
IN
tot
PHZ
, t
PLZ
3-state output disable time nsPC2OUT
4.5 to 5.5 653 to 3.6 11(P-P) at SIG
IN
orAC-coupled input sensitivity V
I(P-P)
mVCOMP
IN
4.5 to 5.5 15
VCO
V
I
= VCO
IN
= 1/2 V
CC
, 3 to 3.6 0.11R
1
= 100 k Ω,∆f/ ∆T Frequency stability with temperature change %/ °CR
2
=∞,
4.5 to 5.5 0.11C
1
= 100 pFC
1
= 50 pF, 3 to 3.6 24R
1
= 3.5 k Ω,
4.5 to 5.5 24R
2
=∞f
MAX
Maximum frequency MHzC
1
= 0 pF, 3 to 3.6 38R
1
= 9.1 k Ω,
4.5 to 5.5 38R2 = ∞C
1
= 40 pF, 3 to 3.6 7 10R
1
= 3 k Ω,
4.5 to 5.5 12 17Center frequency (duty 50%) MHzR
2
=∞,
4.5
(1)
15
(1)
17.5
(1)VCO
IN
= V
CC
/2C
1
= 100 pF, 3 to 3.6 0.4∆fVCO Frequency linearity R
1
= 100 k Ω, %4.5 to 5.5 0.4R
2
=∞
3 to 3.6 400C
1
= 1 nF,Offset frequency kHzR
2
= 220 k Ω
4.5 to 5.5 400
Demodulator
C
1
= 100 pF, 3 8C
2
= 100 pF,V
OUT
vs f
IN
R
1
= 100 k Ω, mV/kHz4.5 330R
2
=∞,R
3
= 100 k Ω
(1) Data is specified at 25 °C
4
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APPLICATION INFORMATION
VCC
VDEMOUT (AV)
1/2 VCC
0φDEMOUT–3605053605
VCC
VDEMOUT (AV)
1/2 VCC
0φDEMOUT
059051805
VCC
GND
SIGIN
COMPIN
VCOOUT
PC1OUT
VCOIN
SIGIN
COMPIN
VCOOUT
PC2OUT
VCOIN
VCC
GND
PCPOUT
High-Impedance Off State
SIGIN
COMPIN
VCOOUT
PC3OUT
VCOIN VCC
GND
SN74LV4046AHIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
AVERAGE OUTPUT VOLTAGE AVERAGE OUTPUT VOLTAGEvs vsINPUT PHASE DIFFERENCE INPUT PHASE DIFFERENCE
Figure 1. Phase Comparator 1: Figure 2. Phase Comparator 2:V
DEMOUT
= V
PC1OUT
= (V
CC
/π) (SIG
IN
– COMP
IN
); V
DEMOUT
= V
PC2OUT
= (V
CC
/4) (SIG
IN
– COMP
IN
);DEMOUT = (SIG
IN
– COMP
IN
) DEMOUT = (SIG
IN
– COMP
IN
)
Figure 3. Typical Waveforms for PLL Using Figure 4. Typical Waveforms for PLL UsingPhase Comparator 1, Loop Locked at f
o
Phase Comparator 2, Loop Locked at f
o
AVERAGE OUTPUT VOLTAGE
vsINPUT PHASE DIFFERENCE
Figure 5. Phase Comparator 3: Figure 6. Typical Waveforms for PLL UsingV
DEMOUT
= V
PC3OUT
= (V
CC
/2 π) (SIG
IN
– COMP
IN
); Phase Comparator 3, Loop Locked at f
oDEMOUT = (SIG
IN
– COMP
IN
)
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SIGIN, COMPIN
PCPOUT, PC1OUT, VS
tPHL tPLH
tTHL tTLH
VS
PC3OUT
Inputs
Outputs
SIGIN
Inputs
COMPIN
Inputs
PC2OUT
Output
VS
tPZH
VS
tPHZ
tPZL tPLZ
VS
90%
10%
SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOPWITH VCO
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 7. Input-to-Output Propagation Delays and Figure 8. 3-State Enable and Disable Times for PC2
OUTOutput Transition Times
C
PD
(1)
CHIP SECTION C
PD
UNIT
Comparator 1 120
pFVCO 120
(1) R1 between 3 k Ωand 50 k ΩR2 between 3 k Ωand 50 k ΩR1 + R2 parallel value > 2.7 k ΩC1 > 40 pF
6
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV4046AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74LV4046ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74LV4046ANS ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ANSG4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ANSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046APW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046APWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4046APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2007
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV4046ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV4046ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV4046ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV4046APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV4046ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74LV4046ADR SOIC D 16 2500 333.2 345.9 28.6
SN74LV4046ANSR SO NS 16 2000 367.0 367.0 38.0
SN74LV4046APWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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