_aiEceE OJbniEea~a= qj Device Features Single Chip Bluetooth System Low power 1.8V operation Small footprint in 96-ball VFBGA and LGA packages (6x6mm 8x8mm and 10x10mm) Fully qualified Bluetooth component 0.18m CMOS technology Production Information Data Sheet for: BC212013 (UART only version) BC212015 (USB and UART version) Support for 8Mbit external flash Minimum external components March 2003 General Description Applications BlueCore2-External is a single chip radio and baseband IC for Bluetooth 2.4GHz systems. It is implemented in 0.18m CMOS technology. PCs Cellular Handsets Cordless Headsets Personal Digital Assistants (PDAs) Computer Accessories (Compact flash Cards, PCMCIA Cards, SD Cards and USB Dongles) Mice, Keyboards and Joysticks Digital Cameras and Camcorders When used with external flash containing the CSR Bluetooth software stack, it provides a fully compliant Bluetooth system for data and voice communications. BlueCore2-External has been designed to reduce the number of external RF components required, which ensures module production costs are minimised. Up to 8Mbit FLASH ROM SPI RAM The device incorporates auto calibration and built-in self-test routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth specification v1.1. UART/USB RF IN 2.4 GHz Radio DSP RF OUT I/O PIO MCU PCM XTAL BlueCore2-External Block Diagram BC212015-ds-001f Production Information Page 1 of 36 _aiEceEOJbniEea~a Product Data Sheet Full speed BluetoothTM operation with full piconet support Table of Contents Table of Contents 1 2 3 4 5 6 6.4 Baseband and Logic ............................................................................................................................... 15 6.4.1 Memory Management Unit ....................................................................................................... 15 6.4.2 Burst Mode Controller............................................................................................................... 15 6.4.3 Physical Layer Hardware Engine DSP ..................................................................................... 16 6.4.4 RAM.......................................................................................................................................... 16 6.4.5 External Memory Driver ............................................................................................................ 16 6.4.6 USB .......................................................................................................................................... 16 6.4.7 Synchronous Serial Interface.................................................................................................... 16 6.4.8 UART........................................................................................................................................ 16 6.4.9 Audio PCM Interface................................................................................................................. 16 6.5 Microcontroller ........................................................................................................................................ 17 6.5.1 Programmable I/O .................................................................................................................... 17 CSR Bluetooth Software Stacks ................................................................................................................. 18 7.1 BlueCore HCI Stack................................................................................................................................ 18 7.1.1 Key Features of the HCI Stack ................................................................................................. 19 7.2 BlueCore RFCOMM Stack ...................................................................................................................... 21 7.2.1 Key Features of the BlueCore2-External RFCOMM Stack ....................................................... 21 7.3 BlueCore Virtual Machine Stack ............................................................................................................. 22 7.4 Host-Side Software ................................................................................................................................. 23 7.5 Device Firmware Upgrade ...................................................................................................................... 23 7.6 Additional Software for Other Embedded Applications ........................................................................... 23 8 7.7 CSR Development Systems.................................................................................................................... 23 External Interfaces ....................................................................................................................................... 24 8.1 Transmitter/Receiver Inputs and Outputs ............................................................................................... 24 8.2 Asynchronous Serial Data Port (UART) and USB Port ........................................................................... 24 8.3 PCM CODEC Interface ........................................................................................................................... 24 8.4 Serial Peripheral Interface ...................................................................................................................... 25 8.5 Parallel PIO Port ..................................................................................................................................... 25 2 8.6 I C Interface ............................................................................................................................................ 25 9 Schematic ..................................................................................................................................................... 26 10 Package Dimensions ................................................................................................................................... 27 10.1 96-Ball VFBGA....................................................................................................................................... 27 10.2 96-Ball LGA............................................................................................................................................ 28 11 12 13 14 15 10.3 96-Ball LFBGA ....................................................................................................................................... 29 Ordering Information ................................................................................................................................... 30 Contact Information ..................................................................................................................................... 31 Document References ................................................................................................................................. 32 Acronyms and Definitions........................................................................................................................... 33 Record of Changes ...................................................................................................................................... 36 BC212015-ds-001f Production Information Page 2 of 36 _aiEceEOJbniEea~a Product Data Sheet 7 Key Features .................................................................................................................................................. 3 Device Pinout Diagram .................................................................................................................................. 4 Device Terminal Functions ........................................................................................................................... 5 Electrical Characteristics .............................................................................................................................. 9 Device Diagram ............................................................................................................................................ 14 Description of Functional Blocks ............................................................................................................... 15 6.1 RF Receiver ............................................................................................................................................ 15 6.1.1 Low Noise Amplifier .................................................................................................................. 15 6.1.2 Analogue to Digital Converter ................................................................................................... 15 6.2 RF Transmitter ........................................................................................................................................ 15 6.2.1 IQ Modulator ............................................................................................................................. 15 6.2.2 Power Amplifier ........................................................................................................................ 15 6.3 RF Synthesiser ....................................................................................................................................... 15 Key Features 1 Key Features Radio Baseband and Software Operation with common TX/RX terminals simplifies external matching circuitry and eliminates external antenna switch Extensive built-in self-test minimises production test time No external trimming is required in production Full RF reference designs are available External 8Mbit flash for complete system solution and application flexibility 32kbyte on-chip RAM allows full speed Bluetooth data transfer, mixed voice and data, plus full 7 slave piconet operation Dedicated logic for forward error correction, header error control, access code correlation, demodulation, cyclic redundancy check, encryption bitstream generation, whitening and transmit pulse shaping Transcoders for A-law, -law and linear voice from host and A-law, -law and CVSD voice over air Transmitter Up to +6dBm RF transmit power with level control from the on-chip 6-bit DAC over a dynamic range greater than 30dB Supports Class 2 and Class 3 radios without the need for an external power amplifier or TX/RX switch Supports Class 1 radios with an external power amplifier provided by a power control terminal controlled by an internal 8-bit voltage DAC and an external RF TX/RX switch Receiver Physical Interfaces Synchronous serial interface up to 4Mbaud UART interface with programmable Baud rate up to 1.5MBaud Full speed USB interface supports OHCI and UHCI host interfaces. Compliant with USB v1.1 Synchronous bi-directional serial programmable audio interface Optional I2CTM compatible interface Integrated channel filters Digital demodulator for improved sensitivity and co-channel rejection Digitised RSSI available in real time over the HCI interface Bluetooth Stack Running on an Internal Microcontroller Fast AGC for enhanced dynamic range CSR's Bluetooth Protocol Stack runs on-chip in a variety of configurations: Synthesiser Fully integrated synthesiser; no external VCO varactor diode or resonator Compatible with crystals between 8 and 32MHz (in multiples of 250kHz) or an external clock Auxiliary Features Crystal oscillator with built-in digital trimming Power management includes digital shut down and wake up commands and an integrated low power oscillator for ultra-low Park/Sniff/Hold mode power consumption Device can be used with an external Master oscillator and provides a `clock request signal' to control external clock source Uncommitted 8-bit ADC and 8-bit DAC are available to application programs BC212015-ds-001f Standard HCI (UART or USB) Fully embedded to RFCOMM, thus reducing host CPU load Package Options 96-ball LFBGA 10x10x1.4mm 0.80mm pitch 96-ball VFBGA 8x8x1.0mm 0.65mm pitch 96-ball VFBGA 6x6x1.0mm 0.50mm pitch 96-ball VFLGA 6x6x0.65mm 0.50mm pitch Production Information Page 3 of 36 _aiEceEOJbniEea~a Product Data Sheet Device Pinout 2 Device Pinout Diagram Orientation from top of device 1 2 3 4 5 6 7 8 9 10 11 A _aiEceEOJbniEea~a Product Data Sheet B C D E F G H J K L Figure 2.1: BlueCore2-External Device Pinout Diagram Notes: Device pinout diagram is the same for: 10x10mm LFBGA (BN) 8x8x1mm VFBGA package (DN) 6x6x1mm VFBGA package (EN) 6x6x0.6mm LGA package (LN) BC212015-ds-001f Production Information Page 4 of 36 Device Terminal Functions 3 Device Terminal Functions Radio Ball Pad Type Description RF_IN E1 Analogue Single ended receiver input PIO[0]/RXEN C1 Bi-directional with weak internal pull-up/down Control output for external LNA (if fitted) PIO[1]/TXEN C2 Bi-directional with weak internal pull-up/down Control output for external PA Class 1 applications only TX_A G1 Analogue Transmitter output/Switched Receiver input F1 Analogue Complement of TX_A AUX_DAC D2 Analogue Voltage DAC output Synthesiser and Oscillator Ball Pad Type Description XTAL_IN L1 Analogue For crystal or external clock input XTAL_OUT L2 Analogue Drive for crystal LOOP_FILTER J1 Analogue Connection to external PLL loop filter External Memory Port Ball Pad Type Description REB D10 WEB E10 Read enable for external memory (active low) Write enable for external memory (active low) CSB C10 CMOS output, tristatable with internal weak pull-up CMOS output, tristatable with internal weak pull-up CMOS output, tristatable with internal weak pull-up Address Lines Ball Pad Type Description A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] D9 E9 E11 F9 F10 F11 G9 G10 G11 H9 H10 H11 J8 J9 J10 J11 K9 K10 K11 CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable CMOS output, tristatable Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line BC212015-ds-001f Chip select for external memory (active low) Production Information Page 5 of 36 _aiEceEOJbniEea~a Product Data Sheet TX_B Device Terminal Functions Data Bus Ball D[0] K8 D[1] L9 D[2] L10 D[3] L11 D[4] L8 D[5] J7 D[6] K7 D[7] L7 D[8] J6 D[9] K6 D[10] L6 D[11] J5 D[12] K5 D[13] L5 D[14] J4 D[15] K4 PCM Interface Ball PCM_OUT B9 PCM_IN B10 PCM_SYNC B11 PCM_CLK B8 USB and UART Ball Pad Type Description UART_TX C8 CMOS output UART data output active high UART_RX C9 CMOS input with weak internal pull-down UART data input active high UART_RTS B7 CMOS output, tristatable with internal pull-up UART request to send active low UART_CTS B6 CMOS input with weak internal pull-down UART clear to send active low USB_D+ (1) A7 Bi-directional USB data plus A6 Bi-directional USB data minus BC212015-ds-001f Description Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Pad Type Data line Data line Data line Data line Data line Data line Data line _aiEceEOJbniEea~a Product Data Sheet USB_D- (1) Pad Type Data line Data line Data line Data line Data line Data line Data line Data line Data line Description CMOS output, tristatable with internal weak pull-down CMOS input, with internal weak pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Synchronous data output Synchronous data input Synchronous data SYNC Synchronous data clock Production Information Page 6 of 36 Device Terminal Functions Ball Pad Type Description RESET F3 CMOS input with weak internal pull-down Reset if high. Input debounced so must be high for >5ms to cause a reset SPI_CSB A4 CMOS input with weak internal pull-up Chip select for Synchronous Serial Interface active low SPI_CLK B5 CMOS input with weak internal pull-down Serial Peripheral Interface clock SPI_MOSI A5 CMOS input with weak internal pull-down Serial Peripheral Interface data input SPI_MISO B4 CMOS output, tristatable with weak internal pulldown Serial Peripheral Interface data output TEST_EN G3 CMOS input with strong internal pull-down For test purposes only (leave unconnected) PIO Port(3) Ball Pad Type Description PIO[2]/ USB_PULL_UP (1) (2) B3 PIO[3]/USB_WAKE_ UP/RAM_CSB (1) (2) B2 PIO[4]/USB_ON (1) (2) B1 PIO[5]/USB_DETACH (1) (2) A3 PIO[6]/CLK_REQ C3 PIO[7] E3 PIO[8] D3 PIO[9] C4 PIO[10] C5 PIO[11] C6 AIO[0] K3 AIO[1] AIO[2] Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down Bi-directional with programmable weak internal pull-up/down PIO or USB pull-up (via 1.5k resistor to USB_D+) PIO or output goes high to wake up PC when in USB mode or external RAM chip select PIO or USB on (input senses when VBUS is high, wakes BlueCore2-External) PIO line or chip detaches from USB when this input is high PIO line or clock request output to enable external clock for external clock line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Bi-directional Programmable input/output line L4 Bi-directional Programmable input/output line J3 Bi-directional Programmable input/output line Notes: (1) USB functions are available on BC212015 only. USB functions can be software mapped to any PIO terminal. (3) All PIO's are configured as inputs with weak pull-downs at reset. (2) BC212015-ds-001f Production Information Page 7 of 36 _aiEceEOJbniEea~a Product Data Sheet Test and Debug Device Terminal Functions Power Supplies and Control VDD_RADIO Ball D1 H3 Pad Type Description VDD Positive supply connection for RF circuitry VDD_VCO H1 VDD Positive supply for VCO and synthesiser circuitry VDD_ANA K1 VDD Positive supply for analogue circuitry A8 VDD Positive supply for internal digital circuitry VDD_PIO A1 VDD Positive supply for PIO and AUX DAC VDD_PADS A10 VDD Positive supply for all other input/output VDD_MEM D11 VDD Positive supply for external memory port and AIO VSS Ground connections for RF circuitry VSS Ground connections for VCO and synthesiser VSS Ground connections for analogue circuitry E2 VSS_RADIO F2 G2 VSS_VCO VSS_ANA J2 H2 L3 K2 VSS_CORE A9 VSS Ground connection for internal digital circuitry VSS_PIO A2 VSS Ground connection for PIO and AUX DAC VSS_PADS A11 VSS Ground connection for input/output except memory port VSS_MEM C11 VSS Ground connection for external memory port VSS C7 VSS Ground connection for internal package shield BC212015-ds-001f Production Information Page 8 of 36 _aiEceEOJbniEea~a Product Data Sheet VDD_CORE Electrical Characteristics 4 Electrical Characteristics Absolute Maximum Ratings Min Max Storage Temperature -40C +150C Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA, VDD_CORE -0.40V 1.90V Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM -0.40V 3.60V Min Max -40C 105C Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA, VDD_CORE 1.70V 1.90V Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM 1.70V 3.60V Recommended Operating Conditions Operating Condition Operating Temperature Range (1) Note: (1) The device functions across this range. See long form data book for guaranteed performance over temperature. BC212015-ds-001f Production Information Page 9 of 36 _aiEceEOJbniEea~a Product Data Sheet Rating Electrical Characteristics Input/Output Terminal Characteristics Digital Terminals Min Typ Max Unit (VDD=3.0V) -0.4 - +0.8 V (VDD=1.8V) -0.4 - +0.4 V 0.7VDD - VDD+0.4 V - - 0.2 V VOL output logic level low, (lO = 4.0mA), VDD=1.8V - - 0.4 V VOH output logic level high, (lO = -4.0mA), VDD=3.0V VDD-0.2 - - V VOH output logic level high, (lO = -4.0mA), VDD=1.8V VDD-0.4 - - V Strong pull-up -100 -20 -10 A Strong pull-down Input Voltage VIL input logic level low VIH input logic level high Output Voltage VOL output logic level low, (lO = 4.0mA), VDD=3.0V +10 +20 +100 A Weak pull-up -5 -1 0 A Weak pull-down 0 +1 +5 A I/O pad leakage current -1 0 +1 A CI Input Capacitance 2.5 - 10 pF Min Typ Max Unit - 0.3VDD_PADS 0.7VDD_PADS - - V V VSS_PADS< VIN< VDD_PADS(1) -1 - 1 A CI Input capacitance 2.5 - 10 pF Output levels to correctly terminated USB Cable VOL input logic level low VOH input logic level high 0 2.8 - 0.2 VDD_PADS V V Input/Output Terminal Characteristics (Continued) USB Terminals Input threshold VIL input logic level low VIH input logic level high Input leakage current Notes: VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative. (1) Internal USB pull-up disabled BC212015-ds-001f Production Information Page 10 of 36 _aiEceEOJbniEea~a Product Data Sheet Input and Tristate Current with: Electrical Characteristics Input/Output Terminal Characteristics (Continued) Auxiliary DAC, 8-Bit Resolution Min Resolution Average output step size(1) Output Voltage Voltage range (IO=0) Current range 12.5 14.5 monotonic(1) - Max Unit 8 17 Bits mV VDD_PIO +0.1 0.2 VDD_PIO +1 +120 +2 10 5 V mA V V A mV LSB s s Input/Output Terminal Characteristics (Continued) Crystal Oscillator Min Typ Max Unit Crystal frequency (2) 8.0 - 32.0 MHz 5 6.2 8 pF - 0.1 - pF 2.0 - - mS 870 1500 2400 Digital trim range (3) Trim step size (3) Transconductance Negative resistance (4) Input/Output Terminal Characteristics (Continued) Power-on reset Min Typ Max Unit VDD falling threshold 1.40 1.50 1.60 V VDD rising threshold 1.50 1.60 1.70 V Hysteresis 0.05 0.10 0.15 V Notes: VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT. Current drawn into a pin is defined as positive, current supplied out of a pin is defined as negative. (1) Specified for an output voltage between 0.2V and VDD_PIO -0.2V (2) Integer multiple of 250kHz. (3) The difference between the internal capacitance at minimum and maximum settings of the internal digital trim. (4) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF BC212015-ds-001f Production Information Page 11 of 36 _aiEceEOJbniEea~a Product Data Sheet Minimum output voltage (IO=100A) Maximum output voltage (IO=10mA) High Impedance leakage current Offset Integral non-linearity(1) Starting time (50pF load) Settling time (50pF load) VSS_PIO -10 0 VDD_PIO-0.3 -1 -220 -2 - Typ Electrical Characteristics Radio Characteristics, VDD = 1.8V Sensitivity at 0.1% BER Maximum received signal at 0.1% BER Initial carrier frequency tolerance 20dB bandwidth for modulated carrier Frequency (GHz) Min Typ Max 2.402 - -83 - 2.441 - -85 - 2.480 - -85 - 2.402 - - - 2.441 - - - 2.480 - - - 2.402 - 6.0 - Bluetooth Specification Unit dBm -70 dBm dBm dBm -20 dBm dBm dBm (2) 2.441 - 6.0 - 2.480 - 6.0 - dBm 2.402 - 12 - kHz -6 to +4 75 dBm 2.441 - 10 - 2.480 - 9 - kHz 2.402 - 879 - kHz 2.441 - 816 - 2.480 1000 kHz kHz kHz - 819 - RF power control range - 35 - 16 dB RF power range control resolution - 1.8 - - dB Notes: (1) BlueCore2-External firmware maintains the transmit power to be within the Bluetooth specification v1.1 limits. (2) Class 2 RF transmit power range, Bluetooth specification v1.1 BC212015-ds-001f Production Information Page 12 of 36 _aiEceEOJbniEea~a Product Data Sheet RF transmit power (1) Temperature = +20C Electrical Characteristics Average Current Consumption (1) VDD=1.8V Temperature = 20C Avg Unit SCO connection HV3 (40ms interval Sniff Mode) (Slave) 26.0 mA SCO connection HV3 (40ms interval Sniff Mode) (Master) 26.0 mA SCO connection HV1 (Slave) 53.0 mA SCO connection HV1 (Master) 53.0 mA ACL data transfer 115.2kbps UART (Master) 15.5 mA ACL data transfer 720kbps USB (Slave) 53.0 mA ACL data transfer 720kbps USB (Master) 53.0 mA ACL connection, Sniff Mode 40ms interval, 38.4kbps UART 4.0 mA ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART 0.5 mA Parked Slave, 1.28s beacon interval, 38.4kbps UART 0.6 mA 0.047 mA 20.0 A Standby Mode (Connected to host, no RF activity) Deep Sleep Mode (2) Notes: (1) Current consumption is the sum of both BC212013B or BC212015B and the flash. (2) Current consumption is for the BC212013B and BC212015B devices only. A 3.0V Flash VREG 1.8V BlueCore2 Figure 4.1: Current Measurement Circuit BC212015-ds-001f Production Information Page 13 of 36 _aiEceEOJbniEea~a Product Data Sheet Mode BC212015-ds-001f Production Information PIO[1]/TXEN AUX_DAC TX_B XTAL_IN TX_A XTAL_OUT IQ DEMOD AUX DAC PA -45 IQ MOD RF Transmitter +45 VCO Fref /N/N+1 RF synthesiser RF Synthesiser RSSI DAC ADC Demodulator Memory management unit Event timer Microcontroller RISC micro-controller Baseband and Logic Burst mode controller Interrupt controller Physical layer hardware engine DSP VDD_CORE RF Receiver LNA VDD_ANA USB Programmable I/O External Memory Driver Audio PCM Interface UART Synchronous Serial Interface VDD_PADS RF_IN VDD_MEM Clock generation RESET AIO[0] AIO[1] AIO[2] VSS_PADS TEST_EN VSS_MEM VSS_CORE VSS_ANA LOOP_FILTER VSS_VCO VDD_VCO VSS_RADIO VDD_RADIO VSS Figure 5.1: BlueCore2-External Device Diagram Page 14 of 36 _aiEceEOJbniEea~a Product Data Sheet PIO[0]/RXEN Memory mapped control/ status 16 19 PIO[2]/USB_PULL_UP PIO[3]/USB_WAKE_UP/RAM_CSB PIO[4]/USB_ON PIO[5]/USB_DETACH PIO[6]/CLK_REQ PIO[7] PIO[8] PIO[9] PIO[10] PIO[11] VDD_PIO D[15:0] A[18:0] WEB REB CSB PCM_CLK PCM_SYNC PCM_OUT PCM_IN UART_CTS UART_RTS UART_RX UART_TX SPI_MISO SPI_MOSI SPI_CLK SPI_CSB USB_D- USB_D+ 5 RAM Device Diagram Device Diagram VSS_PIO Functional Blocks 6 6.1 Description of Functional Blocks RF Receiver The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore2-External to exceed the Bluetooth requirements for co-channel and adjacent channel rejection. Low Noise Amplifier The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1 Bluetooth operation; differential mode is used for Class 2 operation. 6.1.2 Analogue to Digital Converter The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference limited environments. 6.2 RF Transmitter 6.2.1 IQ Modulator The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot which results in a controlled modulation index. A digital baseband transmit filter provides the required spectral shaping. 6.2.2 Power Amplifier The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore2-External to be used in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control allows a simple implementation for Class 1 with an external RF PA. 6.3 RF Synthesiser The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator (VCO) screening can, varactor tuning diodes or LC resonators. 6.4 Baseband and Logic 6.4.1 Memory Management Unit The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient use of the available Random Access Memory (RAM) and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers. 6.4.2 Burst Mode Controller During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception. BC212015-ds-001f Production Information Page 15 of 36 _aiEceEOJbniEea~a Product Data Sheet 6.1.1 Functional Blocks 6.4.3 Physical Layer Hardware Engine DSP Dedicated logic is used to perform the following: Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding A-law/-law/linear voice data (from host) A-law/-law/Continuously Variable Slope Delta (CVSD) (over the air) Voice interpolation for lost packets Rate mismatches 6.4.4 RAM 32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack. 6.4.5 External Memory Driver The External Memory Driver interface can be used to connect to the external Flash memory and also to the optional external RAM for memory intensive applications. 6.4.6 USB This is a full speed Universal Serial Bus interface for communicating with other compatible digital devices. BlueCore2-External acts as a USB peripheral, responding to requests from a Master host controller such as a PC. 6.4.7 Synchronous Serial Interface This is a synchronous serial port interface for interfacing with other digital devices. The SPI port can be used for software debugging and for programming the external Flash memory. 6.4.8 UART This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices. 6.4.9 Audio PCM Interface The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM encoded audio data over Bluetooth. BC212015-ds-001f Production Information Page 16 of 36 _aiEceEOJbniEea~a Product Data Sheet The following voice data translations and operations are performed by firmware: Functional Blocks 6.5 Microcontroller The microcontroller, interrupt controller and event timer run the Bluetooth software stack and control the radio and host interfaces. A 16-bit Reduced Instruction Set Computer (RISC) microcontroller is used for low power consumption and efficient use of memory. 6.5.1 Programmable I/O BlueCore2-External has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are controlled by firmware running on the device. _aiEceEOJbniEea~a Product Data Sheet BC212015-ds-001f Production Information Page 17 of 36 CSR Bluetooth Software Stacks 7 CSR Bluetooth Software Stacks BlueCore2-External is supplied with Bluetooth stack firmware which runs on the internal RISC microcontroller. This is compliant with the Bluetooth specification v1.1. The BlueCore2-External software architecture allows Bluetooth processing overheads to be shared in different ways between the internal RISC microcontroller and the host processor. The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor. Running the upper stack on BlueCore2-External reduces (or eliminates, in the case of a virtual machine (VM) application) the need for host-side software and processing time. Running the upper layers on the host processor allows greater flexibility. BlueCore HCI Stack External Flash HCI LM LC 32KB RAM Baseband Micro UART Host Host I/O USB Radio PCM I/O Figure 7.1: BlueCore HCI Stack In this implementation the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI). All upper layers must be provided by the Host processor. BC212015-ds-001f Production Information Page 18 of 36 _aiEceEOJbniEea~a Product Data Sheet 7.1 CSR Bluetooth Software Stacks 7.1.1 Key Features of the HCI Stack Standard Bluetooth Functionality The firmware has been written against the Bluetooth Core Specification v1.1. Bluetooth components: Baseband (including LC), LM and HCI Standard USB v1.1 and UART (H4) HCI Transport Layers All standard radio packet types Full Bluetooth data rate, up to 723.2kb/s asymmetric(1) Operation with up to 7 active slaves (1) Maximum number of simultaneous active ACL connections: 7(2) Maximum number of simultaneous active SCO connections: 3(2) Operation with up to 3 SCO links, routed to one or more slaves Role switch: can reverse Master/Slave relationship All standard SCO voice codings, plus "transparent SCO" Standard operating modes: page, inquiry, page-scan and inquiry-scan All standard pairing, authentication, link key and encryption operations Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including "Forced Hold" Dynamic control of peers' transmit power via LMP Master/Slave switch Broadcast Channel quality driven data rate All standard Bluetooth Test Modes Standard firmware upgrade via USB (DFU) The firmware's supported Bluetooth features are detailed in the standard PICS documents, available from www.csr.com. Note: (1) Maximum allowed by Bluetooth specification v1.1. (2) BlueCore2-External supports all combinations of active ACL and SCO channels for both Master and Slave operation, as specified by the Bluetooth specification v1.1. BC212015-ds-001f Production Information Page 19 of 36 _aiEceEOJbniEea~a Product Data Sheet CSR Bluetooth Software Stacks Extra Functionality The firmware extends the standard Bluetooth functionality with the following features: Supports BlueCore Serial Protocol (BCSP) - a proprietary, reliable alternative to the standard Bluetooth H4 UART Host Transport. Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set (called BCCMD - "BlueCore Command"), provides: Access to the chip's general-purpose PIO port Access to the chip's Bluetooth clock - this can help transfer connections to other Bluetooth devices The negotiated effective encryption key length on established Bluetooth links Access to the firmware's random number generator Controls to set the default and maximum transmit powers - these can help minimise interference between overlapping, fixed-location piconets Dynamic UART configuration Radio transmitter enable/disable - a simple command connects to a dedicated hardware switch that determines whether the radio can transmit The firmware can read the voltage on a pair of the chip's external pins. This is normally used to build a battery monitor, using either VM or host code. A block of BCCMD commands provides access to the chip's "persistent store" configuration database (PS). The database sets the device's Bluetooth address, Class of Device, radio (transmit class) configuration, SCO routing, LM, USB and DFU constants, etc. A UART "break" condition can be used in three ways: Presenting a UART break condition to the chip can force the chip to perform a hardware reboot Presenting a break condition at boot time can hold the chip in a low power state, preventing normal initialisation while the condition exists With BCSP, the firmware can be configured to send a break to the host before sending data - normally used to wake the host from a deep sleep state The DFU standard has been extended with public/private key authentication, allowing manufacturers to control the firmware that can be loaded onto their Bluetooth modules. A modified version of the DFU protocol allows firmware upgrade via the chip's UART. A block of "radio test" or BIST commands allows direct control of the chip's radio. This aids the development of modules' radio designs, and can be used to support Bluetooth qualification. Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific code. Although the VM is mainly used with BlueLab and "RFCOMM builds" (alternative firmware builds providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such as flashing LED's via the chip's PIO port. Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly reduce power consumption when the software goes idle. SCO channels are normally routed over HCI (over BCSP). However, a single SCO channel can be routed over the chip's single PCM port (at the same time as routing up to two other SCO channels over HCI). [Future versions of the BC02x firmware will be able to exploit the hardware's ability to route up to three SCO channels through the single PCM port.] BC212015-ds-001f Production Information Page 20 of 36 _aiEceEOJbniEea~a Product Data Sheet CSR Bluetooth Software Stacks 7.2 BlueCore RFCOMM Stack RFCOMM SDP External Flash L2CAP LM LC 32KB RAM Baseband Micro Host Host I/O USB Radio PCM I/O Figure 7.2: BlueCore RFCOMM Stack In this version of the firmware the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the HCI only stack. 7.2.1 Key Features of the BlueCore2-External RFCOMM Stack Interfaces to Host RFCOMM, an RS-232 serial cable emulation protocol SDP, a service database look-up protocol Connectivity Maximum number of active slaves: 3 Maximum number of simultaneous active ACL connections: 3 Maximum number of simultaneous active SCO connections: 3 Data Rate: up to 350 Kb/s Security Full support for all Bluetooth security features up to and including strong (128-bit) encryption. Power Saving Full support for all Bluetooth power saving modes (Park, Sniff and Hold). Data Integrity CQDDR increases the effective data rate in noisy environments. RSSI used to minimise interference to other radio devices using the ISM band. BC212015-ds-001f Production Information Page 21 of 36 _aiEceEOJbniEea~a Product Data Sheet UART CSR Bluetooth Software Stacks 7.3 BlueCore Virtual Machine Stack External Flash VM Application Software RFCOMM SDP L2CAP LM LC 32KB RAM Baseband Micro Host I/O Radio PCM I/O Figure 7.3: Virtual Machine This version of the stack firmware requires no host processor. All software layers, including application software, run on the internal RISC processor in a protected user software execution environment known as a Virtual Machine (VM). The user may write custom application code to run on the BlueCore VM using BlueLabTM software development kit (SDK) supplied with the BlueLab and Casira development kits, available separately from CSR. This code will then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations. The execution environment is structured so the user application does not adversely affect the main software routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is changed. Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other profiles without the requirement of a host controller. BlueLab is supplied with example code including a full implementation of the headset profile. Note: Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack. BC212015-ds-001f Production Information Page 22 of 36 _aiEceEOJbniEea~a Product Data Sheet UART Host CSR Bluetooth Software Stacks 7.4 Host-Side Software BlueCore2-External can be ordered with companion host-side software: BlueCore2-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-side stack together with IC hardware described in this document. BlueCore2-Mobile includes software for a full host-side stack designed for modern ARM based mobile handsets together with IC hardware described in this document. 7.5 Device Firmware Upgrade 7.6 Additional Software for Other Embedded Applications When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore2-External, a UART software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher Bluetooth stack layers running on the host. The code is provided as `C' source or object code. 7.7 CSR Development Systems CSR's BlueLab, Casira and MicroSira development kits are available to allow the evaluation of the BlueCore2-External hardware and software, and as toolkits for developing on-chip and host software. BC212015-ds-001f Production Information Page 23 of 36 _aiEceEOJbniEea~a Product Data Sheet BlueCore2-External is supplied with boot loader software which implements a Device Firmware Upgrade (DFU) capability. This allows new firmware to be uploaded to the external Flash memory through BlueCore2-External's UART or USB ports. External Interfaces 8 External Interfaces 8.1 Transmitter/Receiver Inputs and Outputs Terminals TX_A and TX_B form a balanced current output. They require a DC path to VDD and should be connected through a balun to the antenna. The output impedance is capacitive and remains constant, irrespective of whether the transmitter is enabled or disabled. For Class 2 operation these terminals also act as differential receive input terminals with an internal TX/RX switch. For Class 1 operation the RF_IN ball is provided which is single-ended. A swing of up to 0.5V root mean squared (rms) can be tolerated at this terminal. An external antenna switch can be connected to RF_IN. Asynchronous Serial Data Port (UART) and USB Port UART_TX, UART_RX, UART_RTS and UART_CTS form a conventional asynchronous serial data port. The interface is designed to operate correctly when connected to other UART devices such as the 16550A. The signalling levels are 0V and VDD_PADS and are inverted with respect to the signaling on an RS232 cable. The interface is programmable over a variety of bit rates; no, even or odd parity; one or two stop bits and hardware flow control on or off. The default condition on power-up is pre-assigned in the external Flash. The maximum UART data rate is 1.5 MBaud. Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and is active low. UART_CTS is an input and is active low. These signals operate according to normal industry convention. The port carries a number of logical channels: HCI data (both SCO and ACL), HCI commands and events, L2CAP API, RFCOMM API, SDP and device management. For the UART, these are combined into a robust tunnelling protocol, BlueCore Serial Protocol (BCSP), where each channel has its own software flow control and cannot block other data channels. In addition, the Bluetooth specification v1.1, HCI UART Transport Layer (part H4) format is supported. Full speed USB (12Mbit/s) is supported in accordance with the Bluetooth specification v1.1, HCI USB Transport Layer (H2). USB_D+ and USB_D- are available on dedicated terminals. Both Open Host Controller Interface (OHCI) and Universal Host Controller Interfaces (UHCI) are supported. The firmware in Flash can be downloaded through the USB or UART ports by DFU if the CSR supplied boot loader is first programmed. Firmware shipped with BlueCore2-External includes security features to prevent misuse of this upgrade facility. 8.3 PCM CODEC Interface PCM_OUT, PCM_IN, PCM_CLK and PCM_SYNC carry up to three bi-directional channels of voice data, each at 8ksamples/s. The format of the PCM samples can be 8-bit A-law, 8-bit -law, 13-bit linear or 16-bit linear. The PCM_CLK and PCM_SYNC terminals can be configured as inputs or outputs, depending on whether BlueCore2-External is the Master or Slave of the PCM interface. BlueCore2-External interfaces directly to PCM audio devices includes the following: Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices OKI MSM7705 four channel A-law and -law CODEC Motorola MC145481 8-bit A-law and -law CODEC Motorola MC145483 13-bit linear CODEC BlueCore2-External is also compatible with the Motorola SSITM interface BC212015-ds-001f Production Information Page 24 of 36 _aiEceEOJbniEea~a Product Data Sheet 8.2 External Interfaces 8.4 Serial Peripheral Interface BlueCore2-External is a slave device that uses terminals SPI_MOSI, SPI_MISO, SPI_CLK and SPI_CSB. This interface is used for program emulation/debug and IC test. It is also the means by which the external Flash may be programmed `in situ' before any 'boot' program is loaded. Note: The designer should be aware that no security protection is built into the hardware or firmware associated with this port, so the terminals should not be permanently connected in a PC application. 8.5 Parallel PIO Port BlueCore2-External has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2]. These are used to access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip bandgap reference voltage, the other two may be configured to provide additional functionality. Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for battery voltage measurement. Signals selectable at these pins include the bandgap reference voltage and a variety of clock signals; 48, 24, 16, 8 MHz and the Xtal clock frequency. When used with analogue signals the voltage range is constrained by the analogue supply voltage (1.8V). These pins may also be configured to drive out digital level signals (clocks) generated from within the analogue part of the device, the output voltage levels are determined by VDD_MEM which may be either 1.8V or 3.0V, dependant upon the external flash. 8.6 I2C Interface PIO[3] and PIO[2] can be used to form a Master I2C interface. The interface is formed using software to drive these lines. Therefore it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (LCD), keyboard scanner or EEPROM. BC212015-ds-001f Production Information Page 25 of 36 _aiEceEOJbniEea~a Product Data Sheet Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:0] are powered from VDD_PIO and AIO[2:0] are powered from VDD_MEM. PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general use. Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] can be configured as a request line for an external clock source. This is useful when the clock to BlueCore2-External is provided from a system application specific integrated circuit (ASIC). PIO[2] can be configured as a chip select for additional external RAM. RF IN/OUT Z=50 3V3 GND T1 3 1 T2 GND 3 1 CE VIN VOUT U3 XC6209B182MR MDR741F C13 2u2 2 4 F1 GND 2 BYP 4 5 1V8 1 C14 2u2 15p 3n9 L1 T1 HHM-1517 2 6 C1 3 4 5 1V8 C3 1p8 C2 1p8 L3 3n9 L2 3n9 H3 VDD_RADIO D1 VDD_RADIO R3 180k TX_B TX_A AUX_DAC RF_IN C15 220p (COG) F1 G1 D2 E1 C5 10n K1 VDD_ANA C10 47p H1 VDD_VCO C4 15p LOOP_FILTER J1 R1 0R 3V3 H6 VSS H1 VSS 1V8 C6 10n C7 10n 1V8 R2 2R2 C8 10n 3V3 BlueCore2 External B3 NC C4 NC D4 NC D3 NC 1V8 RY/BYB A3 VSS_VCO H2 A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] K11 K10 K9 J11 J10 J9 J8 H11 H10 H9 G11 G10 G9 F11 F10 F9 E11 E9 D9 C3 B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1 FLASH MEMORY A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS_VCO VSS VSS_ANA VSS_RADIO VSS_RADIO VSS_RADIO VSS_CORE VSS_PADS VSS_PIO VSS_MEM J2 C7 L3 F2 G2 E2 A9 A11 A2 C11 A1 VDD_PIO A10 VDD_PADS A8 VDD_CORE D11 VDD_MEM L1 XTAL_IN C11 3p3 XT1 16MHz TSX-10 C12 10p L2 XTAL_OUT K2 VSS_ANA D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] K4 J4 L5 K5 J5 L6 K6 J6 L7 K7 J7 L8 L11 L10 L9 K8 G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2 PIO[11] PIO[10] PIO[9] PIO[8] PIO[7] PIO[6] PIO[5] PIO[4] PIO[3] PIO[2] PIO[1] PIO[0] C6 C5 C4 D3 E3 C3 A3 B1 B2 B3 C2 C1 G4 VCC F6 BYTEB B4 RESETB 3V3 C16 47n U1 G3 K3 L4 F3 J3 C9 10n 3V3 R5 470k C17 1u NOTES NOTE: R1 MAY BE A SMALL INDUCTOR (e.g. 3.9nH, 6.8nH) GROUND USB_D+, USB_D- IF UNUSED 22k R4 TO EXTERNAL CODEC TEST_EN AIO[0] AIO[1] RST AIO[2] 12 MBIT/S USB TO PC A6 USB_DA7 USB_D+ BRING OUT TO TEST PADS FOR PROGRAMMING UART CONNECTION (BCSP, H4 or USER DATA) USER ASSIGNABLE GENERAL PURPOSE I/O B11 PCM_SYNC B8 PCM_CLK B10 PCM_IN B9 PCM_OUT B5 SPI_CLK B4 SPI_MISO A5 SPI_MOSI A4 SPI_CSB C9 UART_RX C8 UART_TX B6 UART_CTS B7 UART_RTS MBM29LV800BA-90PBT U2 DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Production Information _aiEceEOJbniEea~a Product Data Sheet BC212015-ds-001f C10 CSB D10 REB E10 WEB 9 F1 CEB G1 OEB A4 WEB 1V8 Schematic Schematic Figure 9.1: Example Application Circuit Note: For a full BlueCore2-External reference design contact your local CSR representative. Page 26 of 36 Package Dimensions 10 Package Dimensions 10.1 96-Ball VFBGA Top View Bottom View D D1 PIN 1 CORNER PIN A1 A A C D D E E F 10X e E1 E B C F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 11 10 9 7 8 6 5 4 3 2 1 Ob 1 DETAIL K 3 0.1 Z (A3) A (A2) SEE DETAIL K A1 Z 2 SEATING PLANE BC212015DN and BC212013DN DIM MIN MAX A 0.8 1 A1 0.2 0.3 b 0.45 REF 1 2 0.35 0.25 8 BSC D E 8 BSC e 0.65 BSC D1 6.5 BSC E1 6.5 BSC 8x8x1mm VFBGA NOTES 0.22 REF A2 A3 3 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z. DATUM Z IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. VFBGA 96 BALLS 8X8X1mm (JEDEC MO-225) BC212015EN and BC212013EN DIM MIN MAX A 0.8 1 A1 0.2 0.3 b 0.45 REF D 1 2 0.35 0.25 6 BSC E 6 BSC e 0.5 BSC D1 5 BSC E1 5 BSC UNIT MM 6x6x1mm VFBGA NOTES 0.22 REF A2 A3 0.08 Z 3 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z. DATUM Z IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. VFBGA 96 BALLS 6X6X1mm (JEDEC MO-225) UNIT MM Figure 10.1: BlueCore2-External VFBGA Package Dimensions BC212015-ds-001f Production Information Page 27 of 36 _aiEceEOJbniEea~a Product Data Sheet B Package Dimensions 10.2 96-Ball LGA Top View Bottom View D PIN 1 CORNER PIN A1 A A B B C C D D E E E1 E F 10X e F G G H H J K K L L 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 Ob 1 DETAIL K 1 A 0.1 Z (A2) (A1) SEE DETAIL K METAL LEAD BC212015LN and BC212013LN DIM MIN TYP MAX A 0.6 0.65 A1 0.22 REF 0.32 b 0.15 D 0.37 0.08 Z 6x6x0.6mm LGA NOTES 1 A2 Z SEATING PLANE PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.42 0.25 6 BSC E 6 BSC e 0.5 BSC D1 5 BSC E1 5 BSC LGA 96 BALLS 6X6X0.6mm (JEDEC MO-222) UNIT MM Figure 10.2: BlueCore2-External LGA Package Dimensions BC212015-ds-001f Production Information Page 28 of 36 _aiEceEOJbniEea~a Product Data Sheet J Package Dimensions 10.3 96-Ball LFBGA Top View Bottom View D PIN 1 CORNER PIN A1 A A B B C C D D E E E1 E F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 11 10 9 7 8 6 5 4 3 2 1 Ob 1 DETAIL K 3 0.1 Z (A3) A (A2) SEE DETAIL K A1 Z 2 SEATING PLANE BC212015BN DIM MIN MAX A --- 1.4 A1 0.3 0.4 A2 b D 0.8 REF 0.35 10x10x1.4mm LFBGA NOTES 1 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z. 2 DATUM Z IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3 PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.26 REF A3 0.08 Z 0.45 10 BSC E 10 BSC e 0.8 BSC D1 8 BSC E1 8 BSC LFBGA 96 BALLS 10X10X1.4mm (JEDEC MO-210) UNIT MM Figure 10.3: BlueCore2-External LFBGA Package Dimensions BC212015-ds-001f Production Information Page 29 of 36 _aiEceEOJbniEea~a Product Data Sheet F 10X e Ordering Information 11 Ordering Information BlueCore2-External Standard Packaging Options Firmware: HCI/on-chip RFCOMM Package Interface Version UART and USB Size (mm) Shipment Method 96-ball VFBGA 6x6x1 Tape and reel BC212013BEN-E4 6x6x1 Tape and reel BC212013BRN-E4 96-ball LGA 6x6x0.65 Tape and reel BC212013BLN-E4 96-ball LFBGA 10x10x1.4 Tape and reel BC212015BBN-E4 96-ball VFBGA 8x8x1 Tape and reel BC212015BDN-E4 96-ball VFBGA 6x6x1 Tape and reel BC212015BEN-E4 6x6x1 Tape and reel BC212015BRN-E4 6x6x0.65 Tape and reel BC212015BLN-E4 96-ball VFBGA Lead Free 96-ball VFBGA Lead Free 96-ball LGA Additional Software Options: BlueCore2-External is available with additional software options. These are shown in table below. To order these versions attach the appropriate order code to the main packaging order number, e.g., BC212013BDN-E4-0112. Additional Software Options Product Family Description Order Code BlueCore2-Ext-PC Bluetooth for Windows v1.2 English -0112 BlueCore2-Ext-Embedded Bluetooth Embedded v1.2 -4012 BlueCore2-Ext-BCHS(1) BlueCore Host Software -8010 Note: (1) Only available for UART interface versions. Packaging Option 2kpcs Taped and Reeled BC212015-ds-001f Production Information Page 30 of 36 _aiEceEOJbniEea~a Product Data Sheet UART Order Number Type Contact Information 12 Contact Information CSR UK Cambridge Science Park Milton Road Cambridge, CB4 0WH United Kingdom Tel: +44 (0) 1223 692 000 Fax: +44 (0) 1223 692 001 e-mail: sales@csr.com CSR Denmark Novi Science Park Niels Jernes Vej 10 9220 Aalborg East Denmark Tel: +45 72 200 380 Fax: +45 96 354 599 e-mail: sales@csr.com CSR Japan CSR KK Miyasaka LK Bld. 3F 43-23, 3 Chome Shimorenjaku Mitaka-shi, Tokyo Japan 181-0013 Tel: +81 0422 40 4760 Fax: +81 0422 40 4765 e-mail: sales@csr.com CSR Singapore Blk 5, Ang Mo Kio Industrial Park 2A, AMK Tech II, #07-08 Singapore 567760 Tel: +65 6484 2212 Fax: +65 6484 2219 e-mail: sales@csr.com CSR Korea Room 1111 Keumgang Venturetel, #1108, Beesan-dong, DongAn-ku, Anyang-city, Kyunggi-do 431-050, Korea Tel: +82 31 389 0541 Fax: +82 31 389 0545 e-mail: sales@csr.com To contact a CSR representative, go to www.csr.com/contacts.htm BC212015-ds-001f Production Information Page 31 of 36 _aiEceEOJbniEea~a Product Data Sheet CSR U.S. 1651 N. Collins Blvd. Suite 210 Richardson TX75080 Tel: +1 (972) 238 2300 Fax: +1 (972) 231 1440 e-mail: sales@csr.com Document References 13 Document References Document References Version Specification of the Bluetooth system v1.1, 22 February 2001 Universal Serial Bus Specification v1.1, 23 September 1998 _aiEceEOJbniEea~a Product Data Sheet BC212015-ds-001f Production Information Page 32 of 36 Acronyms and Definitions 14 Acronyms and Definitions Definition: BlueCore Bluetooth Group term for CSR's range of Bluetooth chips. A set of technologies providing audio and data transfer over short-range radio connections Asynchronous Connection-Less. A Bluetooth data packet. Alternating Current Analogue to Digital Converter Automatic Gain Control Audio encoding standard Application Programming Interface Application Specific Integrated Circuit BlueCoreTM Serial Protocol Bit Error Rate. Used to measure the quality of a link Ball Grid Array Built-In Self-Test Bill of Materials. Component part list Burst Mode Controller Basic. Represents theoretical exact dimension or dimension target. Carrier Over Interferer Complementary Metal Oxide Semiconductor Coder Decoder Central Processing Unit Channel Quality Driven Data Rate Chip Select Cambridge Silicon Radio Clear to Send Continuous Variable Slope Delta Modulation Digital to Analogue Converter Decibels relative to 1mW Direct Current Device Firmware Upgrade Frequency Shift Keying General Circuit Interface. Standard synchronous 2B+D ISDN timing interface Global System for Mobile communications Host Controller Interface Application's microcontroller Bluetooth integrated chip Header Value In-Phase and Quadrature Modulation Inquiry Access Code Intermediate Frequency Integrated Services Digital Network Industrial, Scientific and Medical kilosamples per second Logical Link Control and Adaptation Protocol (protocol layer) Link Controller Liquid Crystal Display Land Grid Array Low Noise Amplifier Least-Significant Bit Encoding standard Memory Management Unit Master In Serial Out Open Host Controller Interface ACL AC ADC AGC A-law API ASIC BCSP BER BGA BIST BOM BMC BSC C/I CMOS CODEC CPU CQDDR CSB CSR CTS CVSD DAC dBm DC DFU FSK GCI GSM HCI Host Host Controller HV IQ Modulation IAC IF ISDN ISM ksamples/s L2CAP LC LCD LGA LNA LSB -law MMU MISO OHCI BC212015-ds-001f Production Information Page 33 of 36 _aiEceEOJbniEea~a Product Data Sheet Term: Acronyms and Definitions BC212015-ds-001f Power Amplifier Printed Circuit Board Pulse Code Modulation. Refers to digital voice data Personal Digital Assistant Parallel Input Output Phase Lock Loop parts per million Persistent Store Key Random Access Memory Not Read enable Reference. Represents dimension for reference use only. Radio Frequency Protocol layer providing serial port emulation over L2CAP Reduced Instruction Set Computer root mean squared Read Only Memory Receive Signal Strength Indication Ready To Send Receive or Receiver Synchronous Connection-Oriented. Voice oriented Bluetooth packet Secure Digital Software Development Kit Service Discovery Protocol Special Interest Group Short Message Service System On Chip Serial Peripheral Interface Serial Port Profile Static Random Access Memory Supplementary Services Signal Strength Indication Secure Sockets Layer System Under Test Software Shared Wireless Access Protocol Terminal Adaptor Terminal Adaptor Equipment To Be Defined Transmit or Transmitter Universal Asynchronous Receiver Transmitter Universal Serial Bus or Upper Side Band (depending on context) Voltage Controlled Oscillator Very Fine Ball Grid Array Virtual Machine Wideband Code Division Multiple Access Write Enable world wide web Production Information Page 34 of 36 _aiEceEOJbniEea~a Product Data Sheet PA PCB PCM PDA PIO PLL ppm PS Key RAM REB REF RF RFCOMM RISC rms ROM RSSI RTS RX SCO SD SDK SDP SIG SMS SOC SPI SPP SRAM SS SSI SSL SUT SW SWAP TA TAE TBD TX UART USB VCO VFBGA VM W-CDMA WEB www Status of Information Status of Information The progression of CSR Product Data Sheets follows the following format: Advance Information Information for designers on the target specification for a CSR product in development. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-Production Information Production Information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions. The status of this Data Sheet is Production Information. Life Support Policy and Use in Safety-Critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Trademarks, Patents and Licenses BlueCoreTM, BlueLabTM, CasiraTM, CompactSiraTM and MicroSiraTM are trademarks of CSR Ltd. BluetoothTM and the Bluetooth logos are trademarks owned by Bluetooth SIG Inc, USA and licensed to CSR. Windows, Windows 98, Windows 2000, Windows XP and Windows NT are registered trademarks of the Microsoft Corporation. 2 I CTM is a trademark of Philips Corporation. All other product, service and company names are trademarks, registered trademarks or service marks of their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR Ltd. CSR Ltd reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. BC212015-ds-001f Production Information Page 35 of 36 _aiEceEOJbniEea~a Product Data Sheet Final pinout and mechanical dimensions. All electrical specifications may be changed by CSR without notice. Record of Changes 15 Record of Changes Date: Revision: Reason for Change: a Original publication of document. 20 OCT 2001 b Application information added. 27 MAR 2002 c Amendments made to ordering codes. 5 MAY 2002 d Production information added. 28 JUNE 2002 e RF characteristics, current consumption and 10x10 packaging information added in line with BlueCore2-External Data Book. 28 MARCH 2003 f Changes made to 10 x 10 package order code _aiEceE OJbniEea~a=mecCiAi=a~i~=pUEEi qj BC212015-ds-001f March 2003 BC212015-ds-001f Production Information Page 36 of 36 _aiEceEOJbniEea~a Product Data Sheet 12 SEPT 2001