BlueCore 2 External - Cambridge Silicon Radio

BC212015-ds-001f Production Information

Page 1 of 36

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

General Description Applications

BlueCore2-External is a single chip radio and

baseband IC for Bluetooth 2.4GHz systems.

It is implemented in 0.18µm CMOS technology.

When used with external flash containing the CSR

Bluetooth software stack, it provides a fully

compliant Bluetooth system for data and voice

communications.

 PCs

 Cellular Handsets

 Cordless Headsets

 Personal Digital Assistants (PDAs)

 Computer Accessories (Compact flash

Cards, PCMCIA Cards, SD Cards and USB

Dongles)

 Mice, Keyboards and Joysticks

 Digital Cameras and Camcorders

RAM

DSP

MCU

I/O

2.4 GHz

Radio

XTAL

SPI

UART/USB

PIO

PCM

8Mbit

FLASH

ROM

RF OUT

RF IN

Up to

BlueCore2-External has been designed to reduce

the number of external RF components required,

which ensures module production costs are

minimised.

The device incorporates auto calibration and

built-in self-test routines to simplify development,

type approval and production test. All hardware

and device firmware is fully compliant with the

Bluetooth specification v1.1.

BlueCore2-External Block Diagram

Device Features

 Low power 1.8V operation

 Small footprint in 96-ball VFBGA

and LGA packages (6x6mm 8x8mm

and 10x10mm)

 Fully qualified Bluetooth component

 0.18µm CMOS technology

 Full speed BluetoothTM operation

with full piconet support

 Support for 8Mbit external flash

 Minimum external components

_äìÉ`çêÉqjOJbñíÉêå~ä=

Single Chip Bluetooth System

Production Information Data Sheet for:

BC212013

(UART only version)

BC212015

(USB and UART version)

March 2003

Table of Contents

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Table of Contents

1 Key Features .................................................................................................................................................. 3

2 Device Pinout Diagram.................................................................................................................................. 4

3 Device Terminal Functions ........................................................................................................................... 5

4 Electrical Characteristics .............................................................................................................................. 9

5 Device Diagram ............................................................................................................................................ 14

6 Description of Functional Blocks ............................................................................................................... 15

6.1 RF Receiver ............................................................................................................................................ 15

6.1.1 Low Noise Amplifier .................................................................................................................. 15

6.1.2 Analogue to Digital Converter................................................................................................... 15

6.2 RF Transmitter ........................................................................................................................................ 15

6.2.1 IQ Modulator............................................................................................................................. 15

6.2.2 Power Amplifier ........................................................................................................................ 15

6.3 RF Synthesiser ....................................................................................................................................... 15

6.4 Baseband and Logic ............................................................................................................................... 15

6.4.1 Memory Management Unit ....................................................................................................... 15

6.4.2 Burst Mode Controller............................................................................................................... 15

6.4.3 Physical Layer Hardware Engine DSP ..................................................................................... 16

6.4.4 RAM.......................................................................................................................................... 16

6.4.5 External Memory Driver............................................................................................................ 16

6.4.6 USB .......................................................................................................................................... 16

6.4.7 Synchronous Serial Interface.................................................................................................... 16

6.4.8 UART........................................................................................................................................ 16

6.4.9 Audio PCM Interface................................................................................................................. 16

6.5 Microcontroller ........................................................................................................................................ 17

6.5.1 Programmable I/O .................................................................................................................... 17

7 CSR Bluetooth Software Stacks ................................................................................................................. 18

7.1 BlueCore HCI Stack................................................................................................................................ 18

7.1.1 Key Features of the HCI Stack ................................................................................................. 19

7.2 BlueCore RFCOMM Stack...................................................................................................................... 21

7.2.1 Key Features of the BlueCore2-External RFCOMM Stack ....................................................... 21

7.3 BlueCore Virtual Machine Stack ............................................................................................................. 22

7.4 Host-Side Software ................................................................................................................................. 23

7.5 Device Firmware Upgrade ...................................................................................................................... 23

7.6 Additional Software for Other Embedded Applications ........................................................................... 23

7.7 CSR Development Systems.................................................................................................................... 23

8 External Interfaces....................................................................................................................................... 24

8.1 Transmitter/Receiver Inputs and Outputs ............................................................................................... 24

8.2 Asynchronous Serial Data Port (UART) and USB Port ........................................................................... 24

8.3 PCM CODEC Interface ........................................................................................................................... 24

8.4 Serial Peripheral Interface ...................................................................................................................... 25

8.5 Parallel PIO Port ..................................................................................................................................... 25

8.6 I2C Interface ............................................................................................................................................ 25

9 Schematic ..................................................................................................................................................... 26

10 Package Dimensions ................................................................................................................................... 27

10.1 96-Ball VFBGA....................................................................................................................................... 27

10.2 96-Ball LGA............................................................................................................................................ 28

10.3 96-Ball LFBGA....................................................................................................................................... 29

11 Ordering Information ................................................................................................................................... 30

12 Contact Information ..................................................................................................................................... 31

13 Document References ................................................................................................................................. 32

14 Acronyms and Definitions........................................................................................................................... 33

15 Record of Changes ...................................................................................................................................... 36

Key Features

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

1 Key Features

Radio

 Operation with common TX/RX terminals

simplifies external matching circuitry and

eliminates external antenna switch

 Extensive built-in self-test minimises production

test time

 No external trimming is required in production

 Full RF reference designs are available

Transmitter

 Up to +6dBm RF transmit power with level

control from the on-chip 6-bit DAC over a

dynamic range greater than 30dB

 Supports Class 2 and Class 3 radios without the

need for an external power amplifier or TX/RX

switch

 Supports Class 1 radios with an external power

amplifier provided by a power control terminal

controlled by an internal 8-bit voltage DAC and

an external RF TX/RX switch

Receiver

 Integrated channel filters

 Digital demodulator for improved sensitivity and

co-channel rejection

 Digitised RSSI available in real time over the

HCI interface

 Fast AGC for enhanced dynamic range

Synthesiser

 Fully integrated synthesiser; no external VCO

varactor diode or resonator

 Compatible with crystals between 8 and 32MHz

(in multiples of 250kHz) or an external clock

Auxiliary Features

 Crystal oscillator with built-in digital trimming

 Power management includes digital shut down

and wake up commands and an integrated low

power oscillator for ultra-low Park/Sniff/Hold

mode power consumption

 Device can be used with an external Master

oscillator and provides a ‘clock request signal’ to

control external clock source

 Uncommitted 8-bit ADC and 8-bit DAC are

available to application programs

Baseband and Software

 External 8Mbit flash for complete system solution

and application flexibility

 32kbyte on-chip RAM allows full speed Bluetooth

data transfer, mixed voice and data, plus full 7

slave piconet operation

 Dedicated logic for forward error correction,

header error control, access code correlation,

demodulation, cyclic redundancy check,

encryption bitstream generation, whitening and

transmit pulse shaping

 Transcoders for A-law, µ-law and linear voice

from host and A-law, µ-law and CVSD voice over

air

Physical Interfaces

 Synchronous serial interface up to 4Mbaud

 UART interface with programmable Baud rate up

to 1.5MBaud

 Full speed USB interface supports OHCI and

UHCI host interfaces. Compliant with USB v1.1

 Synchronous bi-directional serial programmable

audio interface

 Optional I2CTM compatible interface

Bluetooth Stack Running on an

Internal Microcontroller

CSR’s Bluetooth Protocol Stack runs on-chip in a

variety of configurations:

 Standard HCI (UART or USB)

 Fully embedded to RFCOMM, thus reducing host

CPU load

Package Options

 96-ball LFBGA 10x10x1.4mm 0.80mm pitch

 96-ball VFBGA 8x8x1.0mm 0.65mm pitch

 96-ball VFBGA 6x6x1.0mm 0.50mm pitch

 96-ball VFLGA 6x6x0.65mm 0.50mm pitch

Device Pinout

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

2 Device Pinout Diagram

Orientation from top of device

Figure 2.1: BlueCore2-External Device Pinout Diagram

Notes:

Device pinout diagram is the same for:

10x10mm LFBGA (BN)

8x8x1mm VFBGA package (DN)

6x6x1mm VFBGA package (EN)

6x6x0.6mm LGA package (LN)

Device Terminal Functions

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

3 Device Terminal Functions

Radio Ball Pad Type Description

RF_IN E1 Analogue Single ended receiver input

PIO[0]/RXEN C1

Bi-directional with weak

internal pull-up/down Control output for external LNA (if fitted)

PIO[1]/TXEN C2

Bi-directional with weak

internal pull-up/down

Control output for external PA Class 1

applications only

TX_A G1 Analogue Transmitter output/Switched Receiver input

TX_B F1 Analogue Complement of TX_A

AUX_DAC D2 Analogue Voltage DAC output

Synthesiser and

Oscillator Ball Pad Type Description

XTAL_IN L1 Analogue For crystal or external clock input

XTAL_OUT L2 Analogue Drive for crystal

LOOP_FILTER J1 Analogue Connection to external PLL loop filter

External Memory

Port Ball Pad Type Description

REB D10

CMOS output, tristatable

with internal weak pull-up

Read enable for external memory (active

low)

WEB E10

CMOS output, tristatable

with internal weak pull-up

Write enable for external memory (active

low)

CSB C10

CMOS output, tristatable

with internal weak pull-up Chip select for external memory (active low)

Address Lines Ball Pad Type Description

A[0] D9 CMOS output, tristatable Address line

A[1] E9 CMOS output, tristatable Address line

A[2] E11 CMOS output, tristatable Address line

A[3] F9 CMOS output, tristatable Address line

A[4] F10 CMOS output, tristatable Address line

A[5] F11 CMOS output, tristatable Address line

A[6] G9 CMOS output, tristatable Address line

A[7] G10 CMOS output, tristatable Address line

A[8] G11 CMOS output, tristatable Address line

A[9] H9 CMOS output, tristatable Address line

A[10] H10 CMOS output, tristatable Address line

A[11] H11 CMOS output, tristatable Address line

A[12] J8 CMOS output, tristatable Address line

A[13] J9 CMOS output, tristatable Address line

A[14] J10 CMOS output, tristatable Address line

A[15] J11 CMOS output, tristatable Address line

A[16] K9 CMOS output, tristatable Address line

A[17] K10 CMOS output, tristatable Address line

A[18] K11 CMOS output, tristatable Address line

Device Terminal Functions

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Data Bus Ball Pad Type Description

D[0] K8

Bi-directional with weak

internal pull-down Data line

D[1] L9

Bi-directional with weak

internal pull-down Data line

D[2] L10

Bi-directional with weak

internal pull-down Data line

D[3] L11

Bi-directional with weak

internal pull-down Data line

D[4] L8

Bi-directional with weak

internal pull-down Data line

D[5] J7

Bi-directional with weak

internal pull-down Data line

D[6] K7

Bi-directional with weak

internal pull-down Data line

D[7] L7

Bi-directional with weak

internal pull-down Data line

D[8] J6

Bi-directional with weak

internal pull-down Data line

D[9] K6

Bi-directional with weak

internal pull-down Data line

D[10] L6

Bi-directional with weak

internal pull-down Data line

D[11] J5

Bi-directional with weak

internal pull-down Data line

D[12] K5

Bi-directional with weak

internal pull-down Data line

D[13] L5

Bi-directional with weak

internal pull-down Data line

D[14] J4

Bi-directional with weak

internal pull-down Data line

D[15] K4

Bi-directional with weak

internal pull-down Data line

PCM Interface Ball Pad Type Description

PCM_OUT B9

CMOS output, tristatable

with internal weak pull-down Synchronous data output

PCM_IN B10

CMOS input, with internal

weak pull-down Synchronous data input

PCM_SYNC B11

Bi-directional with weak

internal pull-down Synchronous data SYNC

PCM_CLK B8

Bi-directional with weak

internal pull-down Synchronous data clock

USB and UART Ball Pad Type Description

UART_TX C8 CMOS output UART data output active high

UART_RX C9

CMOS input with weak

internal pull-down UART data input active high

UART_RTS B7

CMOS output, tristatable

with internal pull-up UART request to send active low

UART_CTS B6

CMOS input with weak

internal pull-down UART clear to send active low

USB_D+ (1) A7 Bi-directional USB data plus

USB_D- (1) A6 Bi-directional USB data minus

Device Terminal Functions

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Test and Debug Ball Pad Type Description

RESET F3

CMOS input with weak

internal pull-down

Reset if high. Input debounced so must be

high for >5ms to cause a reset

SPI_CSB A4

CMOS input with weak

internal pull-up

Chip select for Synchronous Serial Interface

active low

SPI_CLK B5

CMOS input with weak

internal pull-down Serial Peripheral Interface clock

SPI_MOSI A5

CMOS input with weak

internal pull-down Serial Peripheral Interface data input

SPI_MISO B4

CMOS output, tristatable

with weak internal pull-

down

Serial Peripheral Interface data output

TEST_EN G3

CMOS input with strong

internal pull-down For test purposes only (leave unconnected)

PIO Port(3) Ball Pad Type Description

PIO[2]/

USB_PULL_UP (1) (2) B3

Bi-directional with

programmable weak

internal pull-up/down

PIO or USB pull-up (via 1.5kΩ resistor to

USB_D+)

PIO[3]/USB_WAKE_

UP/RAM_CSB (1) (2) B2

Bi-directional with

programmable weak

internal pull-up/down

PIO or output goes high to wake up PC when

in USB mode or external RAM chip select

PIO[4]/USB_ON (1) (2) B1

Bi-directional with

programmable weak

internal pull-up/down

PIO or USB on (input senses when VBUS is

high, wakes BlueCore2-External)

PIO[5]/USB_DETACH

(1) (2) A3

Bi-directional with

programmable weak

internal pull-up/down

PIO line or chip detaches from USB when

this input is high

PIO[6]/CLK_REQ C3

Bi-directional with

programmable weak

internal pull-up/down

PIO line or clock request output to enable

external clock for external clock line

PIO[7] E3

Bi-directional with

programmable weak

internal pull-up/down

Programmable input/output line

PIO[8] D3

Bi-directional with

programmable weak

internal pull-up/down

Programmable input/output line

PIO[9] C4

Bi-directional with

programmable weak

internal pull-up/down

Programmable input/output line

PIO[10] C5

Bi-directional with

programmable weak

internal pull-up/down

Programmable input/output line

PIO[11] C6

Bi-directional with

programmable weak

internal pull-up/down

Programmable input/output line

AIO[0] K3 Bi-directional Programmable input/output line

AIO[1] L4 Bi-directional Programmable input/output line

AIO[2] J3 Bi-directional Programmable input/output line

Notes:

(1) USB functions are available on BC212015 only.

(2) USB functions can be software mapped to any PIO terminal.

(3) All PIO’s are configured as inputs with weak pull-downs at reset.

Device Terminal Functions

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Power Supplies

and Control Ball Pad Type Description

VDD_RADIO D1

H3 VDD Positive supply connection for RF circuitry

VDD_VCO H1 VDD Positive supply for VCO and synthesiser

circuitry

VDD_ANA K1 VDD Positive supply for analogue circuitry

VDD_CORE A8 VDD Positive supply for internal digital circuitry

VDD_PIO A1 VDD Positive supply for PIO and AUX DAC

VDD_PADS A10 VDD Positive supply for all other input/output

VDD_MEM D11 VDD Positive supply for external memory port and

AIO

VSS_RADIO

VSS Ground connections for RF circuitry

VSS_VCO J2

H2 VSS Ground connections for VCO and

synthesiser

VSS_ANA L3

K2 VSS Ground connections for analogue circuitry

VSS_CORE A9 VSS Ground connection for internal digital

circuitry

VSS_PIO A2 VSS Ground connection for PIO and AUX DAC

VSS_PADS A11 VSS Ground connection for input/output except

memory port

VSS_MEM C11 VSS Ground connection for external memory port

VSS C7 VSS Ground connection for internal package

shield

Electrical Characteristics

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

4 Electrical Characteristics

Absolute Maximum Ratings

Rating Min Max

Storage Temperature -40°C +150°C

Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,

VDD_CORE -0.40V 1.90V

Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM -0.40V 3.60V

Recommended Operating Conditions

Operating Condition Min Max

Operating Temperature Range(1) -40°C 105°C

Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,

VDD_CORE 1.70V 1.90V

Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM 1.70V 3.60V

Note:

(1) The device functions across this range. See long form data book for guaranteed performance over

temperature.

Electrical Characteristics

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Input/Output Terminal Characteristics

Digital Terminals Min Typ Max Unit

Input Voltage

-0.4 - +0.8 V VIL input logic level low (VDD=3.0V)

(VDD=1.8V) -0.4 - +0.4 V

VIH input logic level high 0.7VDD - VDD+0.4 V

Output Voltage

VOL output logic level low, (lO = 4.0mA), VDD=3.0V - - 0.2 V

VOL output logic level low, (lO = 4.0mA), VDD=1.8V - - 0.4 V

VOH output logic level high, (lO = -4.0mA), VDD=3.0V VDD-0.2 - - V

VOH output logic level high, (lO = -4.0mA), VDD=1.8V VDD-0.4 - - V

Input and Tristate Current with:

Strong pull-up -100 -20 -10 µA

Strong pull-down +10 +20 +100 µA

Weak pull-up -5 -1 0 µA

Weak pull-down 0 +1 +5 µA

I/O pad leakage current -1 0 +1 µA

CI Input Capacitance 2.5 - 10 pF

Input/Output Terminal Characteristics (Continued)

USB Terminals Min Typ Max Unit

Input threshold

VIL input logic level low - - 0.3VDD_PADS V

VIH input logic level high 0.7VDD_PADS - - V

Input leakage current

VSS_PADS< VIN< VDD_PADS(1) -1 - 1

µA

CI Input capacitance 2.5 - 10 pF

Output levels to correctly terminated USB

Cable

VOL input logic level low 0 - 0.2 V

VOH input logic level high 2.8 - VDD_PADS V

Notes:

VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise

VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise

Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.

(1) Internal USB pull-up disabled

Electrical Characteristics

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Input/Output Terminal Characteristics (Continued)

Auxiliary DAC, 8-Bit Resolution Min Typ Max Unit

Resolution - - 8 Bits

Average output step size(1) 12.5 14.5 17 mV

Output Voltage monotonic(1)

Voltage range (IO=0) VSS_PIO - VDD_PIO V

Current range -10 - +0.1 mA

Minimum output voltage (IO=100µA) 0 - 0.2 V

Maximum output voltage (IO=10mA) VDD_PIO-0.3 - VDD_PIO V

High Impedance leakage current -1 - +1 µA

Offset -220 - +120 mV

Integral non-linearity(1) -2 - +2 LSB

Starting time (50pF load) - - 10 µs

Settling time (50pF load) - - 5 µs

Input/Output Terminal Characteristics (Continued)

Crystal Oscillator Min Typ Max Unit

Crystal frequency (2) 8.0 - 32.0 MHz

Digital trim range (3) 5 6.2 8 pF

Trim step size (3) - 0.1 - pF

Transconductance 2.0 - - mS

Negative resistance (4) 870 1500 2400

Ω

Input/Output Terminal Characteristics (Continued)

Power-on reset Min Typ Max Unit

VDD falling threshold 1.40 1.50 1.60 V

VDD rising threshold 1.50 1.60 1.70 V

Hysteresis 0.05 0.10 0.15 V

Notes:

VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise

VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise

The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.

Current drawn into a pin is defined as positive, current supplied out of a pin is defined as negative.

(1) Specified for an output voltage between 0.2V and VDD_PIO -0.2V

(2) Integer multiple of 250kHz.

(3) The difference between the internal capacitance at minimum and maximum settings of the internal digital

trim.

(4) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF

Electrical Characteristics

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Radio Characteristics, VDD = 1.8V Temperature = +20°C

Frequency

(GHz) Min Typ Max Bluetooth

Specification Unit

2.402 - -83 - dBm

2.441 - -85 - dBm

Sensitivity at 0.1% BER

2.480 - -85 -

≤-70

dBm

2.402 - - - dBm

2.441 - - - dBm

Maximum received signal at 0.1%

BER

2.480 - - -

≥-20

dBm

2.402 - 6.0 - dBm

2.441 - 6.0 - dBm

RF transmit power (1)

2.480 - 6.0 -

-6 to +4(2)

dBm

2.402 - 12 - kHz

2.441 - 10 - kHz

Initial carrier frequency tolerance

2.480 - 9 -

±75

kHz

2.402 - 879 - kHz

2.441 - 816 - kHz

20dB bandwidth for modulated

carrier

2.480 - 819 -

≤1000

kHz

RF power control range - 35 - ≥16 dB

RF power range control resolution - 1.8 - - dB

Notes:

(1) BlueCore2-External firmware maintains the transmit power to be within the Bluetooth specification v1.1 limits.

(2) Class 2 RF transmit power range, Bluetooth specification v1.1

Electrical Characteristics

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_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Average Current Consumption (1)

VDD=1.8V Temperature = 20°C

Mode Avg Unit

SCO connection HV3 (40ms interval Sniff Mode) (Slave) 26.0 mA

SCO connection HV3 (40ms interval Sniff Mode) (Master) 26.0 mA

SCO connection HV1 (Slave) 53.0 mA

SCO connection HV1 (Master) 53.0 mA

ACL data transfer 115.2kbps UART (Master) 15.5 mA

ACL data transfer 720kbps USB (Slave) 53.0 mA

ACL data transfer 720kbps USB (Master) 53.0 mA

ACL connection, Sniff Mode 40ms interval, 38.4kbps UART 4.0 mA

ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART 0.5 mA

Parked Slave, 1.28s beacon interval, 38.4kbps UART 0.6 mA

Standby Mode (Connected to host, no RF activity) 0.047 mA

Deep Sleep Mode(2) 20.0

µA

Notes:

(1) Current consumption is the sum of both BC212013B or BC212015B and the flash.

(2) Current consumption is for the BC212013B and BC212015B devices only.

Figure 4.1: Current Measurement Circuit

Flash

BlueCore2

VREG

3.0V 1.8V

Device Diagram

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5 Device Diagram

Microcontroller

Interrupt

controller

Event

timer

RISC

micro-controller

Programmable

I/O

PIO[5]/USB_DETACH

PIO[6]/CLK_REQ

PIO[7]

PIO[2]/USB_PULL_UP

PIO[3]/USB_WAKE_UP/RAM_CS

PIO[4]/USB_ON

VSS_MEM

VSS_PADS

VSS_CORE

Baseband and Logic

UART_TX

UART_RX

UART_RTS

UART_CTS

SPI_CSB

SPI_CLK

SPI_MOSI

SPI_MISO

USB_D+

USB_D-

Synchronous

Serial

Interface

USB

UART

Memory

management

unit

Burst

mode

controller

RAM

Memory

mapped

control/

status

Physical

layer

DSP

hardware

engine

RESET

VDD_ANA

XTAL_OUT

XTAL_IN

Clock

generation

DD_RADIO

RSSI

PIO[0]/RXEN

RF_IN

TX_A

TX_B

PIO[1]/TXEN

LNA

IQ DEMOD

synthesiser

/N/N+1

VCO

LOOP_FILTE

ADC

Demodulator

VSS_ANA

VSS_RADIO

+45

-45

RF Receiver

RF Transmitter

IQ MOD

AUX_DAC

RF Synthesiser

Fref

External

Memory

Driver

CSB

A[18:0]

D[15:0]

WEB

REB

PCM_OUT

PCM_IN

PCM_SYNC

Audio

PCM

Interface

VDD_PADS

VDD_MEM

VDD_CORE

AUX

DAC

VSS_VCO

AIO[0]

AIO[1]

AIO[2]

VSS_PIO

PCM_CLK

DAC

TEST_EN

PIO[8]

PIO[9]

PIO[10]

PIO[11]

VDD_PIO

VSS

VDD_VCO

Figure 5.1: BlueCore2-External Device Diagram

Functional Blocks

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6 Description of Functional Blocks

6.1 RF Receiver

The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be

integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input

allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband

Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a

digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent

performance in the presence of noise allows BlueCore2-External to exceed the Bluetooth requirements for

co-channel and adjacent channel rejection.

6.1.1 Low Noise Amplifier

The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for

Class 1 Bluetooth operation; differential mode is used for Class 2 operation.

6.1.2 Analogue to Digital Converter

The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC

samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is

changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This

improves the dynamic range of the receiver, improving performance in interference limited environments.

6.2 RF Transmitter

6.2.1 IQ Modulator

The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot which

results in a controlled modulation index. A digital baseband transmit filter provides the required spectral shaping.

6.2.2 Power Amplifier

The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore2-External to be

used in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control allows a simple

implementation for Class 1 with an external RF PA.

6.3 RF Synthesiser

The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled

Oscillator (VCO) screening can, varactor tuning diodes or LC resonators.

6.4 Baseband and Logic

6.4.1 Memory Management Unit

The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data

which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient

use of the available Random Access Memory (RAM) and is performed by a hardware MMU to minimise the

overheads on the processor during data/voice transfers.

6.4.2 Burst Mode Controller

During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information

previously loaded into memory-mapped registers by the software and payload data/voice taken from the

appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped

registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention

required by the processor during transmission and reception.

Functional Blocks

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6.4.3 Physical Layer Hardware Engine DSP

Dedicated logic is used to perform the following:

 Forward error correction

 Header error control

 Cyclic redundancy check

 Encryption

 Data whitening

 Access code correlation

 Audio transcoding

The following voice data translations and operations are performed by firmware:

 A-law/µ-law/linear voice data (from host)

 A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air)

 Voice interpolation for lost packets

 Rate mismatches

6.4.4 RAM

32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to hold voice/data for each

active connection and the general purpose memory required by the Bluetooth stack.

6.4.5 External Memory Driver

The External Memory Driver interface can be used to connect to the external Flash memory and also to the

optional external RAM for memory intensive applications.

6.4.6 USB

This is a full speed Universal Serial Bus interface for communicating with other compatible digital devices.

BlueCore2-External acts as a USB peripheral, responding to requests from a Master host controller such as a

PC.

6.4.7 Synchronous Serial Interface

This is a synchronous serial port interface for interfacing with other digital devices. The SPI port can be used for

software debugging and for programming the external Flash memory.

6.4.8 UART

This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other

serial devices.

6.4.9 Audio PCM Interface

The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM

encoded audio data over Bluetooth.

Functional Blocks

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6.5 Microcontroller

The microcontroller, interrupt controller and event timer run the Bluetooth software stack and control the radio

and host interfaces. A 16-bit Reduced Instruction Set Computer (RISC) microcontroller is used for low power

consumption and efficient use of memory.

6.5.1 Programmable I/O

BlueCore2-External has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are

controlled by firmware running on the device.

CSR Bluetooth Software Stacks

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7 CSR Bluetooth Software Stacks

BlueCore2-External is supplied with Bluetooth stack firmware which runs on the internal RISC microcontroller.

This is compliant with the Bluetooth specification v1.1.

The BlueCore2-External software architecture allows Bluetooth processing overheads to be shared in different

ways between the internal RISC microcontroller and the host processor. The upper layers of the Bluetooth stack

(above HCI) can be run either on-chip or on the host processor.

Running the upper stack on BlueCore2-External reduces (or eliminates, in the case of a virtual machine (VM)

application) the need for host-side software and processing time. Running the upper layers on the host processor

allows greater flexibility.

7.1 BlueCore HCI Stack

Figure 7.1: BlueCore HCI Stack

In this implementation the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI).

All upper layers must be provided by the Host processor.

Baseband Micro

PCM I/O

Host I/O

32KB RAM

HCI

Radio

Host

External Flash

UART

USB

CSR Bluetooth Software Stacks

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7.1.1 Key Features of the HCI Stack

Standard Bluetooth Functionality

The firmware has been written against the Bluetooth Core Specification v1.1.

 Bluetooth components: Baseband (including LC), LM and HCI

 Standard USB v1.1 and UART (H4) HCI Transport Layers

 All standard radio packet types

 Full Bluetooth data rate, up to 723.2kb/s asymmetric(1)

 Operation with up to 7 active slaves (1)

 Maximum number of simultaneous active ACL connections: 7(2)

 Maximum number of simultaneous active SCO connections: 3(2)

 Operation with up to 3 SCO links, routed to one or more slaves

 Role switch: can reverse Master/Slave relationship

 All standard SCO voice codings, plus “transparent SCO”

 Standard operating modes: page, inquiry, page-scan and inquiry-scan

 All standard pairing, authentication, link key and encryption operations

 Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including “Forced Hold”

 Dynamic control of peers’ transmit power via LMP

 Master/Slave switch

 Broadcast

 Channel quality driven data rate

 All standard Bluetooth Test Modes

 Standard firmware upgrade via USB (DFU)

The firmware’s supported Bluetooth features are detailed in the standard PICS documents, available from

www.csr.com.

Note:

(1) Maximum allowed by Bluetooth specification v1.1.

(2) BlueCore2-External supports all combinations of active ACL and SCO channels for both Master and Slave

operation, as specified by the Bluetooth specification v1.1.

CSR Bluetooth Software Stacks

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Extra Functionality

The firmware extends the standard Bluetooth functionality with the following features:

 Supports BlueCore Serial Protocol (BCSP) – a proprietary, reliable alternative to the standard Bluetooth

H4 UART Host Transport.

 Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set

(called BCCMD – “BlueCore Command”), provides:

 Access to the chip’s general-purpose PIO port

 Access to the chip’s Bluetooth clock – this can help transfer connections to other Bluetooth devices

 The negotiated effective encryption key length on established Bluetooth links

 Access to the firmware’s random number generator

 Controls to set the default and maximum transmit powers – these can help minimise interference

between overlapping, fixed-location piconets

 Dynamic UART configuration

 Radio transmitter enable/disable – a simple command connects to a dedicated hardware switch that

determines whether the radio can transmit

 The firmware can read the voltage on a pair of the chip’s external pins. This is normally used to build a

battery monitor, using either VM or host code.

 A block of BCCMD commands provides access to the chip’s “persistent store” configuration database

(PS). The database sets the device’s Bluetooth address, Class of Device, radio (transmit class)

configuration, SCO routing, LM, USB and DFU constants, etc.

 A UART “break” condition can be used in three ways:

 Presenting a UART break condition to the chip can force the chip to perform a hardware reboot

 Presenting a break condition at boot time can hold the chip in a low power state, preventing normal

initialisation while the condition exists

 With BCSP, the firmware can be configured to send a break to the host before sending data –

normally used to wake the host from a deep sleep state

 The DFU standard has been extended with public/private key authentication, allowing manufacturers to

control the firmware that can be loaded onto their Bluetooth modules.

 A modified version of the DFU protocol allows firmware upgrade via the chip’s UART.

 A block of “radio test” or BIST commands allows direct control of the chip’s radio. This aids the

development of modules’ radio designs, and can be used to support Bluetooth qualification.

 Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific

code. Although the VM is mainly used with BlueLab and “RFCOMM builds” (alternative firmware builds

providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such

as flashing LED’s via the chip’s PIO port.

 Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly

reduce power consumption when the software goes idle.

 SCO channels are normally routed over HCI (over BCSP). However, a single SCO channel can be

routed over the chip’s single PCM port (at the same time as routing up to two other SCO channels over

HCI). [Future versions of the BC02x firmware will be able to exploit the hardware's ability to route up to

three SCO channels through the single PCM port.]

CSR Bluetooth Software Stacks

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7.2 BlueCore RFCOMM Stack

Figure 7.2: BlueCore RFCOMM Stack

In this version of the firmware the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This

reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the

HCI only stack.

7.2.1 Key Features of the BlueCore2-External RFCOMM Stack

Interfaces to Host

 RFCOMM, an RS-232 serial cable emulation protocol

 SDP, a service database look-up protocol

Connectivity

 Maximum number of active slaves: 3

 Maximum number of simultaneous active ACL connections: 3

 Maximum number of simultaneous active SCO connections: 3

 Data Rate: up to 350 Kb/s

Security

 Full support for all Bluetooth security features up to and including strong (128-bit) encryption.

Power Saving

 Full support for all Bluetooth power saving modes (Park, Sniff and Hold).

Data Integrity

 CQDDR increases the effective data rate in noisy environments.

 RSSI used to minimise interference to other radio devices using the ISM band.

L2CAP

External Flash

RFCOMM SDP

Baseband Micro

PCM I/O

Host I/O

32KB RAM

Radio

Host

UART

USB

CSR Bluetooth Software Stacks

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7.3 BlueCore Virtual Machine Stack

Figure 7.3: Virtual Machine

This version of the stack firmware requires no host processor. All software layers, including application software,

run on the internal RISC processor in a protected user software execution environment known as a Virtual

Machine (VM).

The user may write custom application code to run on the BlueCore VM using BlueLabTM software development

kit (SDK) supplied with the BlueLab and Casira development kits, available separately from CSR. This code will

then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for

various operations.

The execution environment is structured so the user application does not adversely affect the main software

routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the

application is changed.

Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other

profiles without the requirement of a host controller. BlueLab is supplied with example code including a full

implementation of the headset profile.

Note:

Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.

L2CAP

External Flash

RFCOMM SDP

Baseband Micro

PCM I/O

Host I/O

32KB RAM

Radio

Host

UART

VM Application Software

CSR Bluetooth Software Stacks

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7.4 Host-Side Software

BlueCore2-External can be ordered with companion host-side software:

BlueCore2-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-side

stack together with IC hardware described in this document.

BlueCore2-Mobile includes software for a full host-side stack designed for modern ARM based mobile handsets

together with IC hardware described in this document.

7.5 Device Firmware Upgrade

BlueCore2-External is supplied with boot loader software which implements a Device Firmware Upgrade (DFU)

capability. This allows new firmware to be uploaded to the external Flash memory through BlueCore2-External's

UART or USB ports.

7.6 Additional Software for Other Embedded Applications

When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore2-External, a UART

software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher

Bluetooth stack layers running on the host. The code is provided as ‘C’ source or object code.

7.7 CSR Development Systems

CSR’s BlueLab, Casira and MicroSira development kits are available to allow the evaluation of the

BlueCore2-External hardware and software, and as toolkits for developing on-chip and host software.

External Interfaces

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8 External Interfaces

8.1 Transmitter/Receiver Inputs and Outputs

Terminals TX_A and TX_B form a balanced current output. They require a DC path to VDD and should be

connected through a balun to the antenna. The output impedance is capacitive and remains constant,

irrespective of whether the transmitter is enabled or disabled. For Class 2 operation these terminals also act as

differential receive input terminals with an internal TX/RX switch.

For Class 1 operation the RF_IN ball is provided which is single-ended. A swing of up to 0.5V root mean squared

(rms) can be tolerated at this terminal. An external antenna switch can be connected to RF_IN.

8.2 Asynchronous Serial Data Port (UART) and USB Port

UART_TX, UART_RX, UART_RTS and UART_CTS form a conventional asynchronous serial data port. The

interface is designed to operate correctly when connected to other UART devices such as the 16550A. The

signalling levels are 0V and VDD_PADS and are inverted with respect to the signaling on an RS232 cable. The

interface is programmable over a variety of bit rates; no, even or odd parity; one or two stop bits and hardware

flow control on or off. The default condition on power-up is pre-assigned in the external Flash.

The maximum UART data rate is 1.5 MBaud. Two-way hardware flow control is implemented by UART_RTS and

UART_CTS. UART_RTS is an output and is active low. UART_CTS is an input and is active low. These signals

operate according to normal industry convention.

The port carries a number of logical channels: HCI data (both SCO and ACL), HCI commands and events,

L2CAP API, RFCOMM API, SDP and device management. For the UART, these are combined into a robust

tunnelling protocol, BlueCore Serial Protocol (BCSP), where each channel has its own software flow control and

cannot block other data channels. In addition, the Bluetooth specification v1.1, HCI UART Transport Layer (part

H4) format is supported.

Full speed USB (12Mbit/s) is supported in accordance with the Bluetooth specification v1.1, HCI USB Transport

Layer (H2). USB_D+ and USB_D- are available on dedicated terminals. Both Open Host Controller Interface

(OHCI) and Universal Host Controller Interfaces (UHCI) are supported.

The firmware in Flash can be downloaded through the USB or UART ports by DFU if the CSR supplied boot

loader is first programmed. Firmware shipped with BlueCore2-External includes security features to prevent

misuse of this upgrade facility.

8.3 PCM CODEC Interface

PCM_OUT, PCM_IN, PCM_CLK and PCM_SYNC carry up to three bi-directional channels of voice data, each at

8ksamples/s. The format of the PCM samples can be 8-bit A-law, 8-bit µ-law, 13-bit linear or 16-bit linear. The

PCM_CLK and PCM_SYNC terminals can be configured as inputs or outputs, depending on whether

BlueCore2-External is the Master or Slave of the PCM interface.

BlueCore2-External interfaces directly to PCM audio devices includes the following:

 Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices

 OKI MSM7705 four channel A-law and µ-law CODEC

 Motorola MC145481 8-bit A-law and µ-law CODEC

 Motorola MC145483 13-bit linear CODEC

 BlueCore2-External is also compatible with the Motorola SSITM interface