¼
¼
¼
SIN
SCLK
LAT
BLANK
SOUT
GND
VCC
TLC5928
IC1
OUT0 OUT15
VCC
¼ ¼
VLED VLED
¼
¼
SIN
SCLK
LAT
BLANK
RIREF
IREF
SOUT
TLC5928
ICn
OUT0 OUT15
DATA
SCLK
BLANK
ERROR
READ
¼
VLED VLED
RIREF
IREF
Controller
GND
VCC
VCC
3
LAT
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
16-Channel, Constant-Current LED Driver with LED Open Detection
Check for Samples: TLC5928
1FEATURES APPLICATIONS
•LED Video Displays
23•16 Channels, Constant-Current Sink Output
with On/Off Control •Message Boards
•Illumination
•35-mA Capability (Constant-Current Sink)
•10-ns High-Speed Constant-Current Switching DESCRIPTION
Transient Time The TLC5928 is a 16-channel, constant-current sink
•Low On-Time Error LED driver. Each channel can be turned on/off by
•LED Power-Supply Voltage up to 17 V writing serial data to an internal register. The
•VCC = 3.0 V to 5.5 V constant-current value of all 16 channels is set by a
•Constant-Current Accuracy: single external resistor.
–Channel-to-Channel = ±1% The TLC5928 has two error detection circuits: one for
LED open detection (LOD) and one for a pre-thermal
–Device-to-Device = ±1% warning (PTW). LOD detects a broken or
•CMOS Logic Level I/O disconnected LED and LEDs shorted to GND while
•35-MHz Data Transfer Rate the constant-current output is on. PTW indicates a
•20-ns BLANK Pulse Width high temperature condition.
•Readable Error Information:
–LED Open Detection (LOD)
–Pre-Thermal Warning (PTW)
•Operating Temperature: –40°C to +85°C
Typical Application Circuit (Multiple Daisy-Chained TLC5928s)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
TLC5928DBQR Tape and Reel, 2500
TLC5928 SSOP-24/QSOP-24 TLC5928DBQ Tube, 50
TLC5928PWR Tape and Reel, 2000
TLC5928 TSSOP-24 TLC5928PW Tube, 60
TLC5928PWPR Tape and Reel, 2000
TLC5928 HTSSOP-24 PowerPAD™TLC5928PWP Tube, 60
TLC5928RGER Tape and Reel, 3000
TLC5928 QFN-24 TLC5928RGE Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER TLC5928 UNIT
VCC Supply voltage: VCC –0.3 to +6.0 V
IOUT Output current (dc) OUT0 to OUT15 40 mA
VIN Input voltage range SIN, SCLK, LAT, BLANK, IREF –0.3 to VCC + 0.3 V
SOUT –0.3 to VCC + 0.3 V
VOUT Output voltage range OUT0 to OUT15 –0.3 to +18 V
TJ(MAX) Operating junction temperature +150 °C
TSTG Storage temperature range –55 to +150 °C
Human body model (HBM) 2 kV
ESD rating Charged device model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS OPERATING FACTOR TA<+25°C TA= +70°C TA= +85°C
PACKAGE ABOVE TA= +25°C POWER RATING POWER RATING POWER RATING
SSOP-24/QSOP-24 14.3 mW/°C 1782 mW 1140 mW 927 mW
TSSOP-24 9.6 mW/°C 1194 mW 764 mW 621 mW
HTSSOP-24(1) 28.9 mW/°C 3611 mW 2311 mW 1878 mW
QFN-24(2) 24.8 mW/°C 3106 mW 1988 mW 1615 mW
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) The package thermal impedance is calculated in accordance with JESD51-5.
2Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
RECOMMENDED OPERATING CONDITIONS
At TA=–40°C to +85°C, unless otherwise noted. TLC5928
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC Supply voltage 3.0 5.5 V
VOVoltage applied to output OUT0 to OUT15 17 V
VIH High-level input voltage 0.7 ×VCC VCC V
VIL Low-level input voltage GND 0.3 ×VCC V
IOH High-level output current SOUT –1 mA
IOL Low-level output current SOUT 1 mA
IOLC Constant output sink current OUT0 to OUT15 2 35 mA
TAOperating free-air temperature range –40 +85 °C
TJOperating junction temperature range –40 +125 °C
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK) Data shift clock frequency SCLK 35 MHz
TWH0 SCLK 10 ns
TWL0 SCLK 10 ns
TWH1 Pulse duration LAT 20 ns
TWH2 BLANK 20 ns
TWL2 BLANK 20 ns
TSU0 SIN–SCLK↑4 ns
Setup time
TSU1 LAT↑–SCLK↑100 ns
TH0 SIN–SCLK↑3 ns
Hold time
TH1 LAT↑–SCLK↑10 ns
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLC5928
D(%)= -1
IOUTn
(I +I +...+I +I )
OUT0 OUT1 OUT15OUT14
16
´100
D(%)=
IdealOutputCurrent
-(IdealOutputCurrent)
(I +I +...I +I )
OUT0 OUT1 OUT14 OUT15
16 ´100
I =42 ´
OUT(IDEAL)
1.20
RIREF
100
(I atV =3.0V)
OUTn CC
(I atV =5.5V) (I atV =3.0V)
OUTn CC OUTn CC
-
5.5V 3V-
D(%/V)= ´
100
3V 1V-
´
(I atV =1V)
OUTn OUTn
(I atV =3V) (I atV =1V)-
OUTn OUTn OUTn OUTn
D(%/V)=
.
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA=–40°C to +85°C. Typical values at VCC = 3.3 V and TA= +25°C, unless otherwise noted.
TLC5928
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH =–1 mA at SOUT VCC –0.4 VCC V
VOL Low-level output voltage IOL = 1 mA at SOUT 0 0.4 V
IIN Input current VIN = VCC or GND at SIN, SCLK, LAT, and BLANK –1 1 mA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
ICC1 1 2 mA
RIREF = 27 kΩ
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
ICC2 4.5 8 mA
RIREF = 3 kΩ
Supply current (VCC)SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
ICC3 7 18 mA
RIREF = 3 kΩ
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
ICC4 16 40 mA
RIREF = 1.5 kΩ
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
IOLC Constant output current 31 34 37 mA
(see Figure 6), at OUT0 to OUT15
All OUTn for constant-current driver, all outputs off
IOLKG Output leakage current BLANK = high, VOUTn = VOUTfix = 17 V, RIREF = 1.5 kΩ0.1 mA
(see Figure 6), at OUT0 to OUT15
Constant-current error All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
ΔIOLC ±1±3 %
(channel-to-channel)(1) at OUT0 to OUT15
Constant-current error All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
ΔIOLC1 ±1±6 %
(device-to-device)(2) at OUT0 to OUT15
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
ΔIOLC2 Line regulation(3) ±0.5 ±1 %/V
at OUT0 to OUT15
All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V,
ΔIOLC3 Load regulation(4) ±1±3 %/V
RIREF = 1.5 kΩ, at OUT0 to OUT15
T(PTW) Pre-thermal warning threshold Junction temperature(5) +125 +138 +150 °C
VLOD LED open detection threshold All OUTn = ON 0.25 0.30 0.35 V
VIREF Reference voltage output RIREF = 1.5 kΩ1.16 1.20 1.24 V
(1) The deviation of each output from the average of OUT0–OUT15 constant-current. Deviation is calculated by the formula:
(2) The deviation of the OUT0–OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
Ideal current is calculated by the formula:
(3) Line regulation is calculated by this equation:
(4) Load regulation is calculated by the equation:
(5) Not tested. Specified by design.
4Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
VCC
VCC
SCLK
SIN
LAT
BLANK
IREF
GND
GND
16
16
16
MSB
MSB
0 15
LSB
SOUT
OUT0 OUT1 OUT14 OUT15
16-ChannelConstantCurrentSinkDriver
SIDLatch
Thermal
Detection
On/OffControlShiftRegister
(1Bitx16Channels)
16
0 15
LSB
On/OffControlDataLatch
(1Bitx16Channels)
16-ChannelLEDOpenDetection
¼
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA=–40°C to +85°C, CL= 15 pF, RL= 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values at
VCC = 3.3 V and TA= +25°C, unless otherwise noted. TLC5928
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 SOUT (see Figure 5) 5 15 ns
Rise time
tR1 OUTn (see Figure 4) 10 30 ns
tF0 SOUT (see Figure 5) 5 15 ns
Fall time
tF1 OUTn (see Figure 4) 10 30 ns
tD0 SCLK↑to SOUT 8 20 ns
LAT↑or BLANK↓to OUTn sink current on
tD1 12 30 ns
Propagation delay time (see Figure 10)
LAT↑or BLANK↑to OUTn sink current off
tD2 12 30 ns
(see Figure 10)
On/off latch data = all '1', 20 ns BLANK low level
tON_ERR Output on-time error(1) –8 +8 ns
one-shot pulse input (see Figure 4)
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON –BLANK low level one-shot pulse width (TWL2).
tOUT_ON indicates the actual on-time of the constant-current driver.
FUNCTIONAL BLOCK DIAGRAM
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLC5928
GND
SIN
SCLK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
SOUT
BLANK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TLC5928
GND
SIN
SCLK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
SOUT
BLANK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ThermalPad
(BottomSide)
TLC5928
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
DEVICE INFORMATION
SSOP-24/QSOP-24 AND TSSOP-24 HTSSOP-24 PowerPAD
DBQ AND PW PACKAGES PWP PACKAGE
(TOP VIEW) (TOP VIEW)
QFN-24
RGE PACKAGE
(TOP VIEW)
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB pattern.
6Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
TERMINAL FUNCTIONS
TERMINAL
DBQ/PW/
NAME PWP RGE I/O DESCRIPTION
Serial data input for driver on/off control. When SIN = high level, data '1'are written into LSB
SIN 2 23 I of the on/off control shift register at the rising edge of SCLK.
Serial data shift clock. Schmitt buffer input. All data in the on/off control shift register are
SCLK 3 24 I shifted toward the MSB by 1-bit synchronization of SCLK. A rising edge on SCLK is allowed
100 ns after a rising edge of LAT.
Edge triggered latch. The data in the on/off control data shift register are transferred to the
on/off control data latch at this rising edge. At the same time, the data in the on/off control shift
LAT 4 1 I register are replaced with LED open detection (LOD) and pre-thermal warning (PTW) data.
LAT must be toggled only once after the shift data are updated to avoid the on/off control latch
data being replaced with LOD and PTW data in the shift register.
Blank, all outputs. When BLANK = high level, all constant-current outputs (OUT0–OUT15) are
forced off. When BLANK = low level, all constant-current outputs are controlled by the on/off
BLANK 21 18 I control data in the data latch. LOD and PTW data are latched into the SID data latch at the
rising edge of BLANK and are present at the output of the SID data latch when BLANK is low.
Constant-current value setting, OUT0–OUT15 sink constant-current is set to desired value by
IREF 23 20 I/O connection to an external resistor between IREF and GND.
Serial data output. This output is connected to the MSB of the on/off data shift register. SOUT
SOUT 22 19 O data changes at the rising edge of SCLK.
Constant-current output. Each output can be tied together with others to increase the
OUT0 5 2 O constant-current. Different voltages can be applied to each output.
OUT1 6 3 O Constant-current output
OUT2 7 4 O Constant-current output
OUT3 8 5 O Constant-current output
OUT4 9 6 O Constant-current output
OUT5 10 7 O Constant-current output
OUT6 11 8 O Constant-current output
OUT7 12 9 O Constant-current output
OUT8 13 10 O Constant-current output
OUT9 14 11 O Constant-current output
OUT10 15 12 O Constant-current output
OUT11 16 13 O Constant-current output
OUT12 17 14 O Constant-current output
OUT13 18 15 O Constant-current output
OUT14 19 16 O Constant-current output
OUT15 20 17 O Constant-current output
VCC 24 21 —Power-supply voltage
GND 1 22 —Power ground
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLC5928
VCC
INPUT
GND
VCC
SOUT
GND
OUTn
GND
VCC
VCC
GND
IREF OUTn
RIREF
RL
CL
(1) VLED
VCC
VCC
GND
SOUT
CL
(1)
¼¼
VCC
RIREF
VOUTFIX
VOUTn
OUT0VCC
OUTn
OUT15GND
IREF
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Figure 1. SIN, SCLK, LAT, BLANK Figure 2. SOUT
Figure 3. OUT0 Through OUT15
TEST CIRCUITS
(1) CLincludes measurement probe and jig capacitance. (1) CLincludes measurement probe and jig capacitance.
Figure 4. Rise Time and Fall Time Test Circuit for Figure 5. Rise Time and Fall Time Test Circuit for
OUTn SOUT
Figure 6. Constant-Current Test Circuit for OUTn
8Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
T ,T,T ,T ,T :
WH0 WH1WL0 WH2 WL2
INPUT(1)
CLOCK
INPUT(1)
DATA/CONTROL
INPUT(1)
T ,T ,T ,T :
SU0 SU1 H0 H1
TSU TH
VCC
VCC
GND
VCC
GND
GND
50%
50%
50%
TWH TWL
t ,t ,t ,t ,t ,t ,t :
R0 R1 F0 F1 D0 D1 D2
INPUT(1) 50%
50%
90%
10%
OUTPUT
tD
t ort
R F
V orV
OL OUTn
V orV
OH OUTn
GND
VCC
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
TIMING DIAGRAMS
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLC5928
tD0
SIN
OUTn(1)
OUTn(2)
OUTn(3)
OUTn(4)
ON
OFF
LAT
On/OffControl
LatchData(Internal)
SOUT
SCLK
ShiftRegister
LSBData(Internal)
ON
BLANK
ON
OFF OFF
ON
ON
OFF
ON
ON
OFF OFF
OFF
ON
OFF
tWH2
TWH0
TH1
TWH1
13 14 15 16
1 2 3 4 5 1 2 3 4 5 6
TSU0
TH0
TWL0
t /t
R0 F0
tD2
tD1
tWL2
tOUTON
ShiftRegister
LSB+1Data(Internal)
ShiftRegister
MSBData(Internal)
ShiftRegister
MSB-1Data(Internal)
DATA
0A
DATA
0A
LOD
0
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
3B
DATA
2B
DATA
1B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
LOD0AorPTW_A
DATA
0B
DATA
1A
LOD
1
LOD
0
DATA
15B
DATA
14B
DATA
13B
DATA
4B
DATA
3B
DATA
2B
LOD
0A
DATA
15C
DATA
14C
DATA
13C
DATA
12C
LOD1AorPTW_A
DATA
14A
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
1
LOD
0
DATA
15B
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD
9A
LOD14AorPTW_A
DATA
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD15AorPTW_A
DATA
15B
DATA
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD15AorPTW_A
DATA
15B
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
PreviousOn/OffLatchData Latest LatchDataOn/Off
TSU1
tD1 tD2
tD1
tR1
tF1
¼
¼
¼
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1'to '0'at the second LAT signal.
(3) On/off latched data are changed from '0'to '1'at the second LAT signal.
(4) On/off latched data are '0'.
Figure 9. Timing Diagram
10 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
100000
10000
1000
0510 15 20 35
OutputCurrent(mA)
ReferenceResistor( )W
25
1440
5040
3360
2520
1680
25200
10080
30
2016
4000
3000
2000
1000
0
-40 -20 020 40 60 80
Free-AirTemperature( C)°
PowerDissipationRate(mW)
100
TLC5928PW
TLC5928DBQ
TLC5928PWP
TLC5928RGE
40
35
30
25
20
15
10
5
0
00.5 1.0 1.5 2.0 2.5 3.0
OutputVoltage(V)
OutputCurrent(mA)
T =+25 C°
AI =35mA
O
I =30mA
O
I =20mA
O
I =10mA
O
I =5mA
O
I =2mA
O
40
39
38
37
36
35
34
33
32
31
30
00.5 1.0 1.5 2.0 2.5 3.0
OutputVoltage(V)
OutputCurrent(mA)
I =30mA
O
T = 40- °C
A
T =+25 C°
A
T =+85 C°
A
4
3
2
1
0
1
2
3
4
-
-
-
-
-40 -20 020 40 60 80 100
AmbientTemperature( C)°
DI (%)
OLC
I =35mA
O
V =5V
CC
V =3.3V
CC
4
3
2
1
0
1
2
3
4
-
-
-
-
010 20 30 40
OutputCurrent(mA)
DI (%)
OLC
T =+25 C°
A
V =5V
CC
V =3.3V
CC
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA= +25°C, unless otherwise noted.
REFERENCE RESISTOR POWER DISSIPATION RATE
vs OUTPUT CURRENT vs FREE-AIR TEMPERATURE
Figure 10. Figure 11.
OUTPUT CURRENT vs OUTPUT CURRENT vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 12. Figure 13.
ΔIOLC vs AMBIENT TEMPERATURE ΔIOLC vs OUTPUT CURRENT
Figure 14. Figure 15.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TLC5928
Time(12.5ns/div)
CH1(2V/div)
CH2(2V/div)
CH3(2V/div)
CH3-OUT15
(BLANK=20ns)
C 2-OUT0
(BLANK=20ns)
H
CH1-BLANK
(20ns)
I =35mA
T =+25 C
R =130
C =15pF
VLED=5.5V
°
W
OLC
A
L
L
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA= +25°C, unless otherwise noted.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
Figure 16.
12 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
R (k )=W
IREF
V (V)
IREF
I (mA)
OLC
´42
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V) (1)
IOLC must be set in the range of 2 mA to 35 mA. The constant sink current characteristic for the external resistor
value is shown in Figure 10.Table 1 describes the constant-current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLCMax (mA, Typical) RIREF (kΩ)
35 1.44
30 1.68
25 2.02
20 2.52
15 3.36
10 5.04
5 10.1
2 25.2
CONSTANT-CURRENT DRIVER ON/OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' and
remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2.
Table 2. On/Off Control Data Truth Table
ON/OFF CONTROL LATCH DATA CONSTANT-CURRENT OUTPUT STATUS
0 Off
1 On
When the IC is initially powered on, the data in the on/off control shift register and data latch are not set to the
respective default value. Therefore, the on/off control data must be written to the data latch before turning the
constant-current output on. BLANK should be at a high level when powered on because the constant-current
may be turned on as a result of random data in the on/off control latch.
The on/off data corresponding to any unconnected OUTn outputs should be set to ‘0’before turning on the
remaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TLC5928
¼
On/OffControlShiftRegister(1Bit 16Channels)´
On/OffControlDataLatch(1Bit 16Channels)´16Bits
ToConstantCurrentDriverControlBlock
¼
SOUT
13 12 3 2
LSB
On/OffData
for
OUT3
On/OffData
for
OUT2
On/OffData
for
OUT13
On/OffData
for
OUT12
SIN
SCLK
¼
13 12 3 2
LSB
LAT
15 14
On/OffData
for
OUT15
On/OffData
for
OUT14
15 14
1 0
On/OffData
for
OUT1
On/OffData
for
OUT0
1 0
MSB
MSB
On/OffData
for
OUT13
On/OffData
for
OUT12
On/OffData
for
OUT15
On/OffData
for
OUT14
11
11
4
4
On/OffData
for
OUT3
On/OffData
for
OUT2
On/OffData
for
OUT1
On/OffData
for
OUT0
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
REGISTER CONFIGURATION
The TLC5928 has an on/off control data shift register and data latch. Both the on/off control shift register and
latch are 16 bits long and are used to turn on/off the constant-current drivers. Figure 17 shows the shift register
and latch configuration. The data at the SIN pin are shifted in to the LSB of the shift register at the rising edge of
the SCLK pin; SOUT data change at the rising edge of SCLK. The timing diagram for data writing is shown in
Figure 18. The driver on/off is controlled by the data in the on/off control data latch.
The on/off data are latched into the data latch by a rising edge of LAT after the data are written into the on/off
control shift register by SIN and SCLK. At the same time, the data in the on/off control shift register are replaced
with LED open detection (LOD) and pre-thermal warning (PTW) data. Therefore, LAT must be input only once
after the on/off data update to avoid the on/off control data latch being replaced with LOD and PTW data in the
shift register. When the IC is initially powered on, the data in the on/off control shift register and latch are not set
to the default values; on/off control data must be written to the on/off control data latch before turning the
constant-current output on. BLANK should be high when the IC is powered on because the constant-current may
be turned on at that time as a result of random values in the on/off data latch. All constant-current outputs are
forced off when BLANK is high.
Figure 17. On/Off Control Shift Register and Latch Configuration
14 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
PreviousOn/OffLatchData
SIN
OUTn(1)
ON ON
ON
ON
OFF
OFF
OFF OFF
OFF
OFF
OFF
LAT
On/OffControl
LatchData(Internal)
SOUT
OUTn(2)
Latest LatchDataOn/Off
SCLK
1 2 3 4 5 1 2 3 4 5 613 14 15 16
ShiftRegister
LSBData(Internal)
BLANK
ON
OFF
ON
OFF
OUTn(3)
ON
OFF
OUTn(4)
ShiftRegister
LSB+1Data(Internal)
ShiftRegister
MSBData(Internal)
ShiftRegister
MSB 1Data(Internal)-
¼
¼
¼
DATA
0A
DATA
0A
LOD
0
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
LOD0AorPTW_A
DATA
1A
LOD
1
LOD
0
DATA
15B
DATA
14B
DATA
13B
DATA
4B
DATA
3B
DATA
2B
LOD
0A
DATA
15C
DATA
14C
DATA
13C
DATA
12C
LOD1AorPTW_A
DATA
14A
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
1
LOD
0
DATA
15B
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD
9A
LOD14AorPTW_A
DATA
1A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD15AorPTW_A
DATA
15B
DATA
1A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD15AorPTW_A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1'to '0'at the second LAT signal.
(3) On/off latched data are changed from '0'to '1'at the second LAT signal.
(4) On/off latched data are '0'.
Figure 18. On/Off Control Operation
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TLC5928
PTWError
NoErrorInformation
PreviousLODandPTWData
NoErrorInformation
LODandPTWdataoffrombefore
BLANKgoeshighareheldinthe
SIDdatalatchattherisingedgeofBLANK.
T <T :
NormalTemperature
J (PTW)
T <T :
NormalTemperature
J (PTW)
LatestErrorInformationFromLODandPTWCircuit
LatestErrorInformationFromLODCircuit
OUTnON
OUTn
BLANK
GND
VOUTn
OUTnOFF
LODCircuitData
(Internal) NoErrorInformation
LODcircuitneeds1 stodetectLEDm
opencorrectlyasmaximum.
SIDDataLatch
(Internal)
LODandPTWdataarealwayscopiedinto
SIDdatalatchwhileBLANKislowlevel.
PTWCircuitData
(Internal) T T³:HighTemperature
J (PTW)
IfthevoltageofOUTn(V )islessthanV (0.3V,typ)whenOUTnison,
thentheLODcircuitreportserrorinformationtotheLODdatalatch
andtheerrorinformationissetas'1'tothebitthatcorrespondswith
theerrorOUTnintheLODdatalatch.
OUTn LOD
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
LED OPEN DETECTION (LOD) AND PRE-THERMAL WARNING (PTW)
The LED open detection (LOD) circuit checks the voltage of each active (that is, on) constant-current sink output
(OUT0 through OUT15) to detect open LEDs and LEDs shorted to GND while BLANK is low. The LOD bits in the
status information data register (SID) are set to '1' if the voltage of the corresponding OUTn pin is less than the
LED open detection threshold (VLOD = 0.3 V, typ). The status information data can be read from the SOUT pin.
To avoid false detection of open LEDs, the LED driver design must ensure that the constant-current sink output
voltage is greater than 0.3 V when the outputs are on. Also, the output on-time must be 1 ms or greater to
correctly read the valid LOD status.
The PTW function indicates that the IC junction temperature is too high. The PTW bit in the SID data is set to '1'
while the IC junction temperature exceeds the temperature threshold (T(PTW) = +138 °C, typ). If the IC junction
temperature decreases below the temperature of T(PTW), the SID data are set depending on the LOD function.
The constant-current outputs are not forced off during PTW conditions, so the controller should take appropriate
action (such as reducing the duty cycle of effected channels).
The LOD and PTW data are latched into the SID latch with the rising edge of BLANK and do not change until
BLANK goes low. The SID data latched in the latch are transferred into the on/off shift register with a rising edge
of LAT. SID can be shifted out from SOUT with rising edges of SCLK. The data in the on/off control shift register
are replaced with the LOD and PTW data at the rising edge of LAT. Therefore, LAT should be input only once
after the shift data are updated to avoid the on/off control data latch information from being replaced with LOD
and PTW data in the shift register. A timing diagram for LOD, PTW, and SID is shown in Figure 19.
Figure 19. LOD/PTW/SID timing
16 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
¼
SIDDataLatch(1Bit 16Channels)´
SIDControlShiftRegister(1Bit 16Channels)´
The16bitsintheSIDlatchareloadedintotheon/offshiftregisterattherisingedgeofLAT.
¼
SOUT
13 12 3 2
LSB
OUT15
LODData
(LOD3)
OUT15
LODData
(LOD2)
OUT15
LODData
(LOD13)
OUT15
LODData
(LOD12)
SIN
SCLK
¼
13 12 3 2
LSB
15 14
OUT15
LODData
(LOD15)
OUT15
LODData
(LOD14)
15 14
1 0
OUT15
LODData
(LOD1)
OUT15
LODData
(LOD0)
1 0
MSB
MSB
On/OffData
for
OUT13
On/OffData
for
OUT12
On/OffData
for
OUT15
On/OffData
for
OUT14
11
11
4
4
On/OffData
for
OUT3
On/OffData
for
OUT2
On/OffData
for
OUT1
On/OffData
for
OUT0
AllBitsBecome ‘1’ WhentheICisinaPTW(Pre-ThermalWarning)Condition
TLC5928
www.ti.com
SBVS120E –JULY 2008–REVISED JANUARY 2011
STATUS INFORMATION DATA (SID)
The latched LED open detection (LOD) error and pre-thermal warning (PTW) in the SID data latch are shifted out
onto the SOUT pin with each rising edge of SCLK. If a PTW is reported, all LOD error bits are set to '1'. The SID
data are written over the data in the on/off control shift register at the rising edge of LAT. Therefore, the previous
data in the on/off control shift register are lost when SID information is latched in. Figure 20 shows the SID bit
assignments. See Figure 7 for the read timing of SID.
When the IC is powered on, the initial LOD data are invalid. Therefore, LOD data must be read after the rising
edge of BLANK. Table 3 shows a truth table for LOD and PTW.
Table 3. LOD and PTW Truth Table
CONDITION SID DATA
LED is connected (VOUTn >VLOD) '0' (low level at SOUT)
LED open detection (LODn) LED is opened or shorted to GND '1' (high level at SOUT); set to the bit that has an
(VOUTn ≤VLOD and output on) LED error condition
IC temperature is low (IC temperature ≤T(PTW)) Depend LED open error
Pre-thermal warning (PTW) IC temperature is high (IC temperature >T(PTW)) All bits = '1' (high level at SOUT)
Figure 20. Status Information Data Configuration
LAYOUT CONSIDERATIONS
The output current transient time in the TLC5928 is very fast. In addition, all outputs turn on or off at the same
time to minimize the output on-time error. This high current demand can cause GND to shift in the entire system,
and lead to false triggering of signals. To overcome this issue, design all GND lines to be as wide and short as
possible in order to reduce parasitic inductance and resistance.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TLC5928
TLC5928
SBVS120E –JULY 2008–REVISED JANUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2010) to Revision E Page
•Added Layout Considerations section ................................................................................................................................ 17
Changes from Revision C (November 2008) to Revision D Page
•Changed SO-24 to SSOP-24/QSOP-24 in Package/Ordering Information table ................................................................. 2
•Changed SO-24 to SSOP-24/QSOP-24 in Dissipation Ratings table .................................................................................. 2
•Updated functional block diagram ........................................................................................................................................ 5
•Changed SO-24 to SSOP-24/QSOP-24 in DBQ and PW Packages pinout ......................................................................... 6
•Updated Figure 9 ................................................................................................................................................................ 10
•Updated Figure 18 .............................................................................................................................................................. 15
18 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5928
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC5928DBQ ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928DBQG4 ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928PW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5928PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5928PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928PWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5928PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5928RGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5928RGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC5928DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC5928PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TLC5928PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TLC5928RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLC5928RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLC5928RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLC5928RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5928DBQR SSOP DBQ 24 2500 367.0 367.0 38.0
TLC5928PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
TLC5928PWR TSSOP PW 24 2000 367.0 367.0 38.0
TLC5928RGER VQFN RGE 24 3000 367.0 367.0 35.0
TLC5928RGER VQFN RGE 24 3000 367.0 367.0 35.0
TLC5928RGET VQFN RGE 24 250 210.0 185.0 35.0
TLC5928RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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