Vishay Siliconix
DG2018, DG2019
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
1
Low Voltage, Dual DPDT and Quad SPDT Analog Switches
FEATURES
• Low voltage operation (1.8 V to 5.5 V)
• Low on resistance
- RDS(on): 6 Ω at 2.7 V
• Low voltage logic compatible
- DG2019: VINH = 1 V
• High bandwidth: 180 MHz
• QFN-16 package
BENEFITS
• Ideal for both analog and digital signal switching
• Reduced power consumption
• High accuracy
• Reduced PCB space
• Fast switching
• Low leakage
APPLICATIONS
• Cellular phones
• Audio and video signal routing
• PCMCIA cards
• Battery operated systems
• Portable instrumentation
DESCRIPTION
The DG2018 and DG2019 are low voltage, single supply
analog switches. The DG2018 is a dual double-pole/double-
throw (DPDT) with two control inputs that each controls a
pair of single-pole/double-throw (SPDT). The DG2019 uses
one control pin to operate four independent SPDT switches.
When operated on a + 3 V supply, the DG2018’s control pins
are compatible with 1.8 V digital logic. The DG2019 has an
available feature of a VL pin that allows a 1.0 V threshold for
the control pin when VL is powered with 1.5 V.
Built on Vishay Siliconix’s low voltage submicron CMOS
process, the DG2018 and DG2019 are ideal for high
performance switching of analog signals; providing low on-
resistance (6 Ω at + 2.7 V), fast speed (Ton, Toff at 42 ns and
16 ns), and a bandwidth that exceeds 180 MHz.
The DG2018 and DG2019 were designed to offer solutions
that extend beyond audio/video functions, to providing the
performance required for today’s demanding mixed-signal
switching in portable applications.
An epitaxial layer prevents latch-up. Brake-before-make is
guaranteed for all SPDT’s. All switches conduct equally well
in both directions when on, and blocks up to the power
supply level when off.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
IN1, IN2 NO4
COM2
NO2
NC3
IN3, IN4
NC1 COM4
1
2
3
12
11
10
49
56 8
16 15 14 13
NC2 GND NO3 COM3
COM1 NO1 V+ NC4
Top View
DG2018DN
QFN-16 (3 X 3)
7
TRUTH TABLE
IN1, IN2
Logic NC1 and NC2 NO1 and NO2
0ONOFF
1OFFON
IN3, IN4
Logic NC3 and NC4 NO3 and NO4
0ONOFF
1OFFON
ORDERING INFORMATION
Temp. Range Package Part Number
- 40 °C to 85 °C QFN-16 (3 x 3 mm) DG2018DN
www.vishay.com
2
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
Vishay Siliconix
DG2018, DG2019
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Notes:
a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 4.0 mW/°C above 70 °C.
IN NO4
COM2
NO2
NC3
VL
NC1 COM4
1
2
3
12
11
10
49
56 8
16 15 14 13
NC2 GND NO3 COM3
COM1 NO1 V+ NC4
Top View
DG2019DN
QFN-16 (3 X 3)
7
TRUTH TABLE
Logic NC1, 2, 3 and 4 NO1, 2, 3 and 4
0ONOFF
1OFFON
ORDERING INFORMATION
Temp. Range Package Part Number
- 40 °C to 85 °C QFN-16 (3 x 3 mm) DG2019DN
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Reference V+ to GND - 0.3 to + 6 V
IN, COM, NC, NO - 0.3 to (V+ + 0.3)
Continuous Current (Any terminal) ± 50 mA
Peak Current (Pulsed at 1 ms, 10 % Duty Cycle) ± 100
Storage Temperature (D Suffix) - 65 to 150 °C
Power Dissipation (Packages)bQFN-16 (3 x 3 mm)c850 mW
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
3
Vishay Siliconix
DG2018, DG2019
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
SPECIFICATIONS V+ = 3 V
Parameter Symbol
Test Conditions
Otherwise Unless Specified
V+ = 3 V, ± 10 %,
(DG2018 Only) VIN = 0.5 or 1.4 Ve
(DG2019 Only) VL = 1.5 V, VIN = 0.4 or 1.0 VeTemp.a
Limits
- 40 °C to 85 °C
Unit Min.bTyp.cMax.b
Analog Switch
Analog Signal RangedVNO, VNC,
VCOM
Full 0 V+ V
On-Resistance RON
V+ = 2.7 V, VCOM = 0.2 V/1.5 V
INO, INC = 10 mA
Room
Full
612
15
Ω
RON Flatness RON
Flatness V+ = 2.7 V
VCOM = 0 to V+, INO, INC = 10 mA
Room 0.5 2
RON Match Between
Channels
ΔRON Room 0.6 3
Switch Off Leakage Current
INO(off)
INC(off) V+ = 3.3 V, VNO, VNC = 0.3 V/3 V
VCOM = 3 V/0.3 V
Room
Full
- 1
- 10 0.3 1
10
nA
ICOM(off) Room
Full
- 1
- 10 0.3 1
10
Channel-On Leakage Current ICOM(on) V+ = 3.3 V, VNO, VNC = VCOM = 0.3 V/3 V Room
Full
- 1
10 0.3 1
10
Digital Control
Input High Voltage VINH
DG2018 Full 1.4
V
VL = 1.5 V DG2019 Full 1.0
Input Low Voltage VINL
DG2018 Full 0.5
VL = 1.5 V DG2019 Full 0.4
Input Capacitance Cin f = 1 MHz Full 9 pF
Input Current IINL or IINH VIN = 0 or V+ Full - 1 1 µA
Dynamic Characteristics
Tu r n - On T im e tON
VNO or VNC = 2.0 V, RL = 300 Ω, CL = 35 pF
Room
Full
42 55
65
ns
Turn-Off Time tOFF Room
Full
16 25
35
Break-Before-Make Time tdVNO or VNC = 2.0 V, RL = 50 Ω, CL = 35 pF Full 1
Charge InjectiondQINJ CL = 1 nF, VGEN = 0 V, RGEN = 0 ΩRoom - 1.46 pC
Off-IsolationdOIRR
RL = 50 Ω, CL = 5 pF, f = 1 MHz
Room - 67 dB
CrosstalkdXTA L K Room - 72
BandwidthdBW Room 180 MHz
NO, NC Off CapacitancedCNO(off)
VIN = 0 or V+, f = 1 MHz
Room 9
pF
CNC(off) Room 9
Channel-On CapacitancedCNO(on) Room 30
CNC(on Room 30
Power Supply
Power Supply Current I+ VIN = 0 or V+ Full 0.01 1.0 µA
www.vishay.com
4
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
Vishay Siliconix
DG2018, DG2019
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Not production tested.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS V+ = 5 V
Parameter Symbol
Test Conditions
Otherwise Unless Specified
V+ = 5 V, ± 10 %,
(DG2018 Only) VIN = 0.8 or 1.8 Ve
(DG2019 Only) VL = 1.5 V, VIN = 0.4 or 1.0 VeTemp.a
Limits
- 40 °C to 85 °C
Unit Min.bTyp.cMax.b
Analog Switch
Analog Signal RangedVNO, VNC,
VCOM
Full 0 V+ V
On-Resistance RON V+ = 4.5 V, VCOM = 3 V, INO, INC = 10 mA Room
Full
48
10
Ω
RON Flatness RON
Flatness V+ = 4.5 V
VCOM = 0 to V+, INO, INC = 10 mA
Room 0.6 1.2
RON Match Between Channels ΔRON Room 0.6 1.2
Switch Off Leakage Currentf
INO(off)
INC(off) V+ = 5.5 V
VNO, VNC = 1 V/4.5 V, VCOM = 4.5 V/1 V
Room
Full
- 1
- 10 0.03 1
10
nA
ICOM(off) Room
Full
- 1
- 10 0.03 1
10
Channel-On Leakage CurrentfICOM(on) V+ = 5.5 V, VNO, VNC = VCOM = 1 V/4.5 V Room
Full
- 1
- 10 0.03 1
10
Digital Control
Input High Voltage VINH
DG2018 Full 1.8
V
VL = 1.5 V DG2019 Full 1.0
Input Low Voltage VINL
DG2018 Full 0.8
VL = 1.5 V DG2019 Full 0.4
Input Capacitance Cin Full 9 pF
Input Current IINL or IINH VIN = 0 or V+ Full 1 1 µA
Dynamic Characteristics
Tur n -On Ti m e tON
VNO or VNC = 3 V, RL = 300 Ω, CL = 35 pF
Room
Full
44 48
52
ns
Turn-Off Time tOFF Room
Full
19 33
35
Break-Before-Make Time tdVNO or VNC = 3 V, RL = 50 Ω, CL = 35 pF Full 1
Charge InjectiondQINJ CL = 1 nF, VGEN = 0 V, RGEN = 0 ΩRoom - 2.46 pC
Off-IsolationdOIRR
RL = 50 Ω, CL = 5 pF, f = 1 MHz
Room - 67 dB
CrosstalkdXTA L K Room - 72
BandwidthdBW Room 180 MHz
Source-Off CapacitancedCNO(off)
VIN = 0 or V+, f = 1 MHz
Room 7.5
pF
CNC(off) Room 7.5
Channel-On CapacitancedCNO(on) Room 30
CNC(on Room 30
Power Supply
Power Supply Range V+ 1.8 5.5 V
Power Supply Current I+ VIN = 0 or V+ Full 0.01 1.0 µA
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
5
Vishay Siliconix
DG2018, DG2019
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
RON vs. VCOM and Supply Voltage
Supply Current vs. Temperature
Leakage Current vs. Temperature
0
2
4
6
8
10
0123456
VCOM - Analog Voltage (V)
- On-Resistance (Ω)
RON
T = 25 °C
ICOM = 10 mA
V+ = 5.5 V
V+ = 2.7 V
V+ = 3.3 V
- 60 - 40 - 20 0 20 40 60 80 100
1
1000
10 000
Temperature (°C)
V+ = 5.5 V
VIN = 0 V
10
100
I+ - Supply Current (pA)
- 60 - 40 - 20 0 20 40 60 80 100
1
1000
10 000
Temperature (°C)
V+ = 5 V
10
100
Leakage Current (pA)
INO(off), IINC(off)
ICOM(off)
ICOM(on)
RON vs. Analog Voltage and Temperature
Supply Current vs. Input Switching Frequency
Leakage vs. Analog Voltage
0
1
2
3
4
5
6
7
8
9
0123456
VCOM - Analog Voltage (V)
- On-Resistance (Ω)
RON
V+ = 2.7 V
25 °C
V+ = 5.5 V
- 40 °C
85 °C
85 °C
25 °C
- 40 °C
Input Switching Frequency (Hz)
I+ - Supply Current (A)
0 10 M2 M
10 mA
1 µA
100 nA
10 nA
0
1 mA
4 M 6 M 8 M
10 µA
100 µA
- 150
- 125
- 100
- 75
- 50
- 25
0
25
50
75
100
125
150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCOM, VNO, VNC - Analog Voltage (V)
Leakage Current (pA)
V+= 3.3 V
INO(off), INC(off)
ICOM(off) ICOM(on)
www.vishay.com
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Document Number: 72342
S-82626-Rev. C, 03-Nov-08
Vishay Siliconix
DG2018, DG2019
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Switching Time vs. Temperature
and Supply Voltage
VIN vs. VL (Typ)
0
10
20
30
40
50
- 60 - 40 - 20 0 20 40 60 80 100
R
L
= 300 Ω
t
ON
V+ = 5.5 V
t
OFF
V+ = 3.3 V
t
OFF
V+ = 5.5 V
Temperature (°C)
t
ON
V+ = 3.3 V
t
ON
/t
off
- Switching Time (ns)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VL (V)
V+ = 3.3 V
V+ = 5.5 V
Vth
- Threshold Voltage
DG2019
Switching Voltage vs. Supply Voltage (V+)
Charge Injection at Source vs. Analog Voltage
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0123456
ON/OFF
OFF/ON
Vth -Threshold Voltage
DG2018
V+ - Supply Voltage (V)
-6
-4
- 2
0
2
4
6
8
10
0123456
Q - Charge Injection (pC)
VCOM - Analog Voltage (V)
V+ = 3.3 V
V+ = 5.5 V
Insertion Loss, Off Isolation and Crosstalk
vs. Frequency
100K 1M 100M 1G
Frequency (Hz)
XTALK
Loss
10M
V+ = 3.0 V, 5.5 V
RL
OIRR
Loss, OIRR, XTALK (dB)
- 110
- 100
- 90
- 80
- 70
- 60
- 50
- 40
- 30
- 20
- 10
0
10
L = 5 pF = 50 Ω, C
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
7
Vishay Siliconix
DG2018, DG2019
TEST CIRCUITS
Figure 1. Switching Time
Switch
Input
CL (includes fixture and stray capacitance)
V+
IN
NO or NC
CL
35 pF
COM
Logic
Input
RL
300 Ω
VOUT
GND
V+
50 %
0 V
Logic
Input
Switch
Output
tON tOFF
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
0 V
Switch Output
0.9 x VOUT
tr < 5 ns
tf < 5 ns
VINH
VINL
VOUT =V
COM
RL
RL+R
ON
Figure 2. Charge Injection
Off OnOn
IN
ΔVOUT
VOUT
Q = ΔVOUT x CL
CL = 1 nF
Rgen
VOUT
COM
VIN = 0 - V+
IN
Vgen
GND
V+
V+
IN depends on switch configuration: input polarity
determined b
y
sense of switch.
+
NC or NO
Figure 3. Break-Before-Make Interval
CL (includes fixture and stray capacitance)
NC
VNO
NO
VNC
0 V
Logic
Input
Switch
Output
VO
VNC = VNO
tr < 5 ns
tf < 5 ns
90 %
tDtD
IN
COM
V+
GND
CL
35 pF
VO
RL
50 Ω
VINL
VINH
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8
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
Vishay Siliconix
DG2018, DG2019
TEST CIRCUITS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?72342.
Figure 4. Off-Isolation
IN
GND
NC or NO
0 V, 2.4 V
10 nF
COM
Off Isolation = 20 log
VCOM
VNO/ NC
RL
Analyzer
V+
V+
COM
Figure 5. Channel Off/On Capacitance
NC or NO
f = 1 MHz
IN
COM
GND
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
10 nF
V+
V+
-C-
C0.08
NOTES:
1. All dimensions are in millimeters.
2. N is the total number of terminals.
3. Dimension b applies to metallized terminal and is measured between 0.25 and 0.30 mm from terminal tip.
4. Coplanarity applies to the exposed heat sink slug as well as the terminal.
5. The pin #1 identifier may be either a mold or marked feature, it must be located within the zone iindicated.
4
C0.10//
-A-
-B-
E
SEATING
PLANE
A3
A1A
4NX
SIDE VIEW
3
3
Terminal T ip
Exposed Pad
D
D/2
E/2
BOTTOM VIEW
TOP VIEW
C0.25
C0.25
E2/2
E2
D2
D2/2
L
e
3 x e
3 x e
C0.10 MA B
4xb
Package Information
Vishay Siliconix
Document Number: 72208
29-Dec-03 www.vishay.com
1
QFN−16 LEAD (3 X 3)
VARIATION 1 VARIATION 2
Dim MILLIMETERS INCHES MILLIMETERS INCHES
Min Nom Max Min Nom Max Min Nom Max Min Nom Max
A0.80 0.90 1.00 0.031 0.035 0.039 0.80 0.90 1.00 0.031 0.035 0.039
b0.18 0.23 0.30 0.007 0.009 0.012 0.18 0.25 0.30 0.007 0.010 0.012
D3.00 BS C 0.118 BSC 3.00 BSC 0.118 BSC
D2 1.00 1.15 1.25 0.039 0.045 0.049 1.55 1.70 1.80 0.061 0.067 0.071
E3.00 BSC 0.118 BSC 3.00 BSC 0.1 18 BSC
E2 1.00 1.15 1.25 0.039 0.045 0.049 1.55 1.70 1.80 0.061 0.067 0.071
e0.50 BSC 0.020 BSC 0.50 BSC 0.020 BSC
L0.30 0.40 0.50 0.012 0.016 0.020 0.30 0.40 0.50 0.012 0.016 0.020
ECN: S-32625—Rev. B, 29-Dec-03
DWG: 5899
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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