[AK5552] AK5552 2-Channel Differential 32-bit ADC 1. General Description The AK555x series is a 32-bit, 768 kHz sampling, differential input A/D converter for digital audio systems. It achieves 115 dB dynamic range and 106 dB S/(N+D) while maintaining low power consumption performance. The AK5552 integrates a 2-channel A/D converter, suitable for mixers and multi-channel recorders. Four types of digital filters are integrated and selectable according to the sound quality preference. The AK5552 can be easily connected to a DSP by supporting TDM audio formats. Additionally, it supports DSD output up to 11.2MHz.The channel summation mode improves the dynamic range performance by summing-up multiple channel A/D data and averaging. The dynamic range is improved to 118 dB in 2-to-1 mode. 2. Features Sampling Rate: 8 kHz - 768 kHz Input: Full Differential Inputs S/(N+D): 106 dB DR: 115 dB (2-to-1 mode: 118 dB) S/N: 115 dB (2-to-1 mode: 118 dB) Internal Filter: Four types of LPF, Digital HPF Power Supply: 4.5-5.5 V (Analog), 1.7-1.98 V or 3.0-3.6 V (Digital) Output Format PCM mode: 24/32-bit MSB justified, I2S or TDM DSD mode: DSD Native 64, 128, 256 Maximized Slot Efficiency in TDM Mode by Optimal Data Placed Mode Cascade TDM I/F: TDM512: fs= 48 kHz TDM256: fs= 96 kHz or 48 kHz TDM126: fs= 192 kHz, 96 kHz or 48 kHz Operation Mode: Master Mode & Slave Mode Detection Function: Input Overflow Flag Serial Interface: 3-wire Serial and I2C P I/F (Pin setting is also available) Power Consumption: 83 mW (@AVDD= 5.0 V, TVDD= 3.3 V, fs= 48 kHz) Package: 48-pin QFN 015099871-E-01 2017/11 -1- [AK5552] 3. Table of Contents General Description ............................................................................................................................ 1 Features .............................................................................................................................................. 1 Table of Contents................................................................................................................................ 2 Block Diagram..................................................................................................................................... 3 Block Diagram.................................................................................................................................... 3 5. Pin Configurations and Functions ...................................................................................................... 4 Pin Configurations ............................................................................................................................. 4 Pin Functions ..................................................................................................................................... 5 Handling of Unused Pin ..................................................................................................................... 7 6. Absolute Maximum Ratings ................................................................................................................ 8 7. Recommended Operation Conditions ................................................................................................ 8 8. Analog Characteristics ........................................................................................................................ 9 9. Filter Characteristics ......................................................................................................................... 10 ADC Filter Characteristics (fs= 48 kHz) .......................................................................................... 10 ADC Filter Characteristics (fs= 96 kHz) .......................................................................................... 12 ADC Filter Characteristics (fs= 192 kHz) ........................................................................................ 14 ADC Filter Characteristics (fs= 384 kHz) ........................................................................................ 16 ADC Filter Characteristics (fs= 768 kHz) ........................................................................................ 17 10. DC Characteristics ........................................................................................................................ 18 11. Switching Characteristics .............................................................................................................. 19 Timing Diagram ............................................................................................................................... 26 12. Functional Descriptions ................................................................................................................. 31 Digital Core Power Supply ............................................................................................................... 31 Output Mode .................................................................................................................................... 31 Master Mode and Slave Mode ......................................................................................................... 31 System Clock ................................................................................................................................... 31 Audio Interface Format .................................................................................................................... 34 Channel Summation (PCM mode, DSD mode) .............................................................................. 46 Optimal Data Placement Mode (PCM Mode, DSD Mode) .............................................................. 46 CH Power Down & Channel Summation (PCM mode, DSD mode) ............................................... 46 Data Slot Configuration.................................................................................................................... 50 Digital Filter Setting (PCM mode) .................................................................................................... 51 Digital HPF (PCM mode) ................................................................................................................. 51 Overflow Detection (PCM mode, DSD mode) ................................................................................. 51 LDO .................................................................................................................................................. 52 Reset ................................................................................................................................................ 52 Power Down Function/ Sequence ................................................................................................... 53 Operation Mode Control .................................................................................................................. 56 Register Control Interface ................................................................................................................ 56 Register Map .................................................................................................................................... 60 Register Definitions .......................................................................................................................... 60 13. Recommended External Circuits .................................................................................................. 63 14. Package......................................................................................................................................... 66 Outline Dimensions .......................................................................................................................... 66 Material & Lead Finish ..................................................................................................................... 66 Marking ............................................................................................................................................ 66 15. Ordering Guide .............................................................................................................................. 67 16. Revision History ............................................................................................................................ 67 IMPORTANT NOTICE ........................................................................................................................... 68 1. 2. 3. 4. 015099871-E-01 2017/11 -2- [AK5552] 4. Block Diagram VREFL1 VREFH1 Block Diagram TVDD AIN1P Delta-Sigma Modulator VDD18 DVSS LDO Voltage Reference AIN1N LDOE Decimation Filter HPF DIF0/DSDSEL0 DIF1/DSDSEL1 AIN2P AIN2N Delta-Sigma Modulator Decimation Filter HPF BICK/DCLK Serial Output Interface LRCK/DSDOL1 TDMIN/DSDOR1 SDTO1 DP TDM0 TDM1 ODP AVDD AVSS PSN/CAD0_SPI CKS0/SDA/CDTI CKS1/CAD0_I2C/CSN CKS2/SCL/CCLK CKS3/CAD1 I2C DCKS/HPFE OVF MSN PW0 PW1 PW2 SD/PMOD SLOW/DCKB TEST MCLK PDN Controller Figure 1. Block Diagram 015099871-E-01 2017/11 -3- [AK5552] 5. Pin Configurations and Functions 36 35 34 33 32 31 30 29 28 27 26 25 SD/PMOD SLOW/DCKB CKS3/CAD1 CKS2/SCL/CCLK CKS1/CAD0_I2C/CSN CKS0/SDA/CDTI OVF TESTO1 SDTO1 TDMIN/DSDOR1 LRCK/DSDOL1 BICK/DCLK Pin Configurations 37 38 39 40 41 42 43 44 45 46 47 48 48QFN TOP VIEW Exposed Pad (Back Face) * 24 23 22 21 20 19 18 17 16 15 14 13 MSN PW2 PW1 PW0 PDN VDD18 DVSS TVDD MCLK TEST TESTIN6 TESTIN5 NC VREFL1 VREFH1 AIN2N AIN2P AVDD AVSS TESTIN1 TESTIN2 TESTIN3 TESTIN4 NC 1 2 3 4 5 6 7 8 9 10 11 12 DIF0/DSDSEL0 DIF1/DSDSEL1 TDM0 TDM1 PSN/CAD0_SPI I2C DP HPFE/DCKS LDOE ODP AIN1P AIN1N * The exposed pad at back face of the package must be open or connected to the ground. Figure 2. Pin Configurations 015099871-E-01 2017/11 -4- [AK5552] Pin Functions No. Pin Name I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC VREFL1 VREFH1 AIN2N AIN2P AVDD AVSS TESTIN1 TESTIN2 TESTIN3 TESTIN4 NC I I I I - Function TESTIN5 TESTIN6 - TEST MCLK I I 17 TVDD - 18 DVSS I No internal bonding. Connect to AVSS. ADC Low Level Voltage Reference Input Pin ADC High Level Voltage Reference Input Pin Channel 2 Negative Input Pin Channel 2 Positive Input Pin Analog Power Supply Pin (AIN1-2), 4.5-5.5 V Analog Ground Pin (AIN1-2) Test Input Pin1 Test Input Pin2 Test Input Pin3 Test Input Pin4 No internal bonding. Connect to AVSS. Test Input Pin5 Test Input Pin6 TEST Enable Pin Master Clock Input Pin Digital I/O Buffers and LDO Power Supply Pin, 1.7-1.98 V (LDOE pin= "L") or 3.0-3.6 V (LDOE pin= "H"). Digital Ground Pin Digital Core Power Supply Pin, 1.7-1.98 V (LDOE pin= "L") 19 VDD18 O LDO Stabilization Capacitor Connect Pin. (LDOE pin= "H") 20 PDN I 21 22 23 24 PW0 PW1 PW2 MSN I I I I - I BICK 25 O DCLK O I LRCK 26 O DSDOL1 O TDMIN I DSDOR1 O SDTO1 O O O 27 28 29 30 TESTO1 OVF Reset & Power Down Pin "L": Reset & Power Down, "H" : Normal Operation Power Management Pin, Channel Summation Select Pin1 Power Management Pin, Channel Summation Select Pin2 Power Management Pin, Channel Summation Select Pin3, Master/Slave Select Pin Audio Serial Data Clock Input Pin in PCM & Slave Mode (This pin is pull down by 100 k internally.) Audio Serial Data Clock Output Pin in PCM & Master Mode (This pin is pull down by 100 k internally.) DSD Clock Output Pin in DSD Mode (This pin is pull down by 100 k internally.) Channel Clock Input Pin in PCM & Slave Mode (This pin is pull down by 100 k internally.) Channel Clock Output Pin in PCM & Master Mode (This pin is pull down by 100 k internally.) Audio Serial Data Output Pin for AIN1 in DSD Mode (This pin is pull down by 100 k internally.) TDM Data Input Pin in PCM Mode (This pin is pull down by 100 k internally.) Audio Serial Data Output Pin for AIN2 in DSD Mode (This pin is pull down by 100 k internally.) Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode Test Output Pin1 Analog Input Over Flow Flag Output Pin 015099871-E-01 Power Down Status Hi-z & Pull Down with 500 Hi-z Hi-z Hi-z Hi-z Hi-z L Hi-z L 2017/11 -5- [AK5552] No. 31 32 33 34 35 36 Pin Name I/O Function CKS0 SDA CDTI CKS1 CAD0_I2C CSN CKS2 SCL CCLK CKS3 CAD1 SLOW DCKB SD PMOD I I/O I I I I I I I I I I I I I Clock Mode Select Pin 2 Control Data I/O Pin in I C Bus Serial Control Mode Control Data Input Pin in 3-wire Serial Control Mode Clock Mode Select Pin 2 Chip Address 0 Pin in I C Bus Serial Control Mode Chip Select Pin in 3-wire Serial Control Mode Clock Mode Select Pin 2 Control Data Clock Pin in I C Bus Serial Control Mode Control Data Clock Pin in 3-wire Serial Control Mode Clock Mode Select Pin 2 Chip Address 1 Pin in I C Bus or 3-wire Serial Control Mode Slow Roll-OFF Digital Filter Select Pin in PCM Mode Polarity of DCLK Pin in DSD Mode Short Delay Digital Filer Select Pin in PCM Mode DSD Phase Modulation Mode Select Pin in DSD Mode Audio Data Format Select Pin in PCM Mode 2 "L": MSB Justified, "H": I S DSD Sampling Rate Control Pin in DSD Mode Audio Data Format Select Pin in PCM Mode "L": 24-bit Mode, "H": 32-bit Mode DSD Sampling Rate Control Pin in DSD Mode TDM I/F Format Select Pin * This pin must be fixed to "L" when using DSD mode. TDM I/F Format Select Pin * This pin must be fixed to "L" when using DSD mode. Control Mode Select Pin (I2C pin = "H") 2 "L":I C Bus Serial Control Mode, "H" :Parallel Control Mode Chip Address 0 Pin in 3-wire serial control Mode (I2C pin = "L") Control Mode Select Pin "L": 3-wire Serial Control Mode 2 "H": I C Bus Serial Control Mode or Parallel Control Mode DSD Mode Enable Pin "L": PCM Mode, "H": DSD Mode High Pass Filter Enable Pin "L": HPF Disable, "H": HPF Enable Master Clock Frequency Select at DSD Mode (DSD Only) LDO Enable Pin "L": LDO Disable, "H": LDO Enable DIF0 I DSDSEL0 I DIF1 I DSDSEL1 I 39 TDM0 I 40 TDM1 I PSN I CAD0_SPI I 42 I2C I 43 DP I 37 38 41 44 45 HPFE I DCKS I LDOE I Power Down Status Hi-z - - This pin is pulled down by 100 k internally. 46 47 48 ODP AIN1P AIN1N I I I Optimal Data Placement Mode Enable Pin Channel 1 Positive Input Pin Channel 1 Negative Input Pin - Note 1. All digital input pins must not be allowed to float. 015099871-E-01 2017/11 -6- [AK5552] Handling of Unused Pin The unused I/O pins should be connected appropriately. 1. PCM Mode Classification Analog Digital 2. DSD Mode Classification Analog Digital Pin Name AIN1-2P, AIN1-2N NC, TESTIN1-6 TDMIN, TEST OVF, TESTO1 Setting Open Connect to AVSS Connect to DVSS Open Pin Name AIN1-2P, AIN1-2N NC, TESTIN1-6 TDM0, TDM1, TEST SDTO1, OVF, TESTO1 Setting Open Connect to AVSS Connect to DVSS Open Note 2. Unused channels must be powered down. 015099871-E-01 2017/11 -7- [AK5552] 6. Absolute Maximum Ratings (VSS= 0 V; Note 3) Parameter Symbol Min. Max. Unit Power Analog (AVDD pin) AVDDam -0.3 6.0 V Supplies: Digital Interface (TVDD pin) TVDDam -0.3 4.0 V Digital Core (VDD18 pin)(Note 4) VDD18am -0.3 2.5 V Input Current (Any Pin Except Supplies) IIN mA 10 Analog Input Voltage (AIN1-4P, AIN1-4N pins) VINA -0.3 AVDD+0.3 V Digital Input Voltage VIND -0.3 TVDD+0.3 V Ambient Temperature (Power applied) When the back tab is connected to VSS Ta -40 105 C When the back tab is open Ta -40 70 C Storage Temperature Tstg -65 150 C Note 3. All voltages with respect to ground. Note 4. The 1.8 V LDO is off (LDOE pin = "L") and an external power is supplied to the VDD18 pin. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operation Conditions (VSS= 0 V; Note 3) Parameter Analog (AVDD pin) Power Supplies (LDOE pin= "L") (Note 5) Digital Interface (TVDD pin) (Note 6) Digital Core (VDD18 pin) (LDOE pin= "H") (Note 7) Digital Interface (TVDD pin) Symbol AVDD Min. 4.5 Typ. 5.0 Max. 5.5 Unit V TVDD VDD18 1.7 1.7 1.8 1.8 1.98 1.98 V V TVDD 3.0 3.3 3.6 V Voltage "H" voltage Reference (Note 8) VREFH1 4.5 5.0 5.5 V Reference "L" voltage reference VREFL1 AVSS V (Note 11) Note 3. All voltages with respect to ground. Note 5. VDD18 must be powered up either at the same time or after TVDD is powered up.The power up sequence between AVDD pin and TVDD pin or between AVDD pin and VDD18 pin is not critical. Note 6. TVDD must not exceed VDD180.1 V when LDOE pin= "L". Note 7. When LDOE pin = "H", the internal LDO supplies 1.8 V (typ). The power up sequences between AVDD pin and TVDD pin is not critical. Note 8. VREFH1 must not exceed AVDD+0.1 V. Note 9. VREFL1 must be connected to AVSS. Analog Input Voltage is proportional to {(VREFH) - (VREFL)}. Vin (typ, @ 0dB) = 2.8 {(VREFH) - (VREFL)} / 5 [V]. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015099871-E-01 2017/11 -8- [AK5552] 8. Analog Characteristics (Ta= 25 C; AVDD= 5.0 V; TVDD= 3.3 V, fs= 48 kHz, BICK= 64fs; Signal Frequency= 1 kHz; 24-bit Data; Measurement frequency= 20 Hz-20 kHz at fs= 48 kHz, 40 Hz-40 kHz at fs= 96 kHz, 40 Hz-40 kHz at fs= 192 kHz, unless otherwise specified.) Parameter Min. Typ. Max. Unit Analog Input Characteristics: Resolution 32 Bit Input Voltage (Note 10) Vpp 2.7 2.8 2.9 106 1dBFS 100 dB S/(N+D) fs=48kHz 20dBFS dB 92 BW=20kHz 60dBFS dB 52 106 1dBFS dB fs=96kHz 20dBFS dB 89 BW=40kHz 60dBFS dB 49 106 1dBFS dB fs=192kHz 20dBFS dB 89 BW=40kHz 60dBFS dB 49 Dynamic Range Not Sum. mode 110 115 dB (60dBFS with A-weighted) 2-to-1 mode 118 dB S/N Not Sum. mode 110 115 dB (A-weighted) 2-to-1 mode 118 dB Input Resistance These values will be doubled in DSD 64fs mode. k 8.8 10.4 12.0 (Values in DSD128 or DSD256 modes are as shown here) Interchannel Isolation 110 120 dB (AIN1AIN2) Interchannel Gain Mismatch 0 0.5 dB Power Supply Rejection (Note 11) 60 dB Power Supplies Power Supply Current Normal Operation (PDN pin = "H", LDOE pin = "H") AVDD+VREFH1 12 16 mA TVDD (fs= 48 kHz) 7 10 mA TVDD (fs= 96 kHz) 11 14 mA TVDD (fs= 192 kHz) 11 14 mA Power down mode (PDN pin = "L") (Note 12) AVDD+TVDD 10 100 A Note 10. This value is (AINnP)(AINnN) that the ADC output becomes full-scale (n=1-2). Vin = 0.56 (VREFHmVREFLm) [Vpp]. (m=1) Note 11. PSRR is applied to AVDD, TVDD with 1kHz, 20mVpp sine wave. The VREFH1 is held to the fixed voltage. Note 12. All digital inputs are fixed to TVDD or TVSS. 015099871-E-01 2017/11 -9- [AK5552] 9. Filter Characteristics ADC Filter Characteristics (fs= 48 kHz) (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD=1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin= "L")) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 3) (SD pin="L", SLOW pin="L") Passband (Note 13) PB 0 kHz 22.0 +0.001/0.06 dB kHz 24.4 6.0 dB Stopband (Note 13) SB 27.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 19 Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 4) (SD pin="L", SLOW pin="H") Passband (Note 13) PB +0.001/0.076 dB 0 12.5 kHz 21.9 kHz 6.0 dB Stopband (Note 13) SB 36.5 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 0 1/fs GD Group Delay (Note 14) GD 7 1/fs Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 5) (SD pin="H", SLOW pin="L") Passband (Note 13) PB 0 22.0 kHz +0.001/0.06 dB 24.4 kHz 6.0 dB Stopband (Note 13) SB 27.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 2.8 1/fs GD Group Delay (Note 14) GD 1/fs 5 Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 6) (SD pin="H", SLOW pin="H") Passband (Note 13) +0.001/0.076 dB PB 0 12.5 kHz 21.9 kHz 6.0 dB Stopband (Note 13) SB 36.5 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 1.2 1/fs GD Group Delay (Note 14) GD 5 1/fs Digital Filter (HPF): 3.0 dB Frequency Response 1.0 Hz FR 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The passband and stopband frequencies scale with fs. For example, PB (+0.001 dB/0.06 dB) =0.46 fs (SHARP ROLL-OFF). For example, PB (+0.001 dB/0.076 dB) =0.26 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099871-E-01 2017/11 - 10 - [AK5552] Figure 3. SHARP ROLL-OFF (fs= 48 kHz) Figure 4. SLOW ROLL-OFF (fs= 48 kHz) Figure 5. SHORT DELAY SHARP ROLL-OFF (fs= 48 kHz) Figure 6. SHORT DELAY SLOW ROLL-OFF (fs= 48 kHz) 015099871-E-01 2017/11 - 11 - [AK5552] ADC Filter Characteristics (fs= 96 kHz) (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD=1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin= "L")) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 7) (SD pin="L", SLOW pin= "L") 44.1 Passband (Note 13) +0.001/0.06 dB 0 kHz PB 48.8 kHz 6.0 dB Stopband (Note 13) SB 55.7 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 ~ 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 19 Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 8) (SD pin="L", SLOW pin= "H") 25 Passband (Note 13) +0.001/0.076 dB 0 kHz PB 43.8 kHz 6.0 dB Stopband (Note 13) SB 73 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 ~ 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 7 Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF (Figure 9) (SD pin="H", SLOW pin= "L") Passband (Note 13) +0.001/0.06 dB 0 44.1 kHz PB 48.8 kHz 6.0 dB Stopband (Note 13) SB 55.7 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 ~ 40.0 kHz 2.8 1/fs GD Group Delay (Note 14) GD 1/fs 5 Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 10) (SD pin="H", SLOW pin= "H") Passband (Note 13) +0.001/0.076 dB 0 25 kHz PB 43.8 kHz 6.0 dB Stopband (Note 13) SB 73 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 ~ 40.0 kHz 1.2 1/fs GD Group Delay (Note 14) GD 1/fs 5 Digital Filter (HPF): 3.0 dB Frequency Response 1.0 Hz FR 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The passband and stopband frequencies scale with fs. For example, PB (+0.001 dB/0.06 dB) = 0.46 fs (SHARP ROLL-OFF). For example, PB (+0.001 dB/0.076 dB) = 0.26 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099871-E-01 2017/11 - 12 - [AK5552] Figure 7. SHARP ROLL-OFF (fs= 96 kHz) Figure 8. SLOW ROLL-OFF (fs= 96 kHz) Figure 9. SHORT DELAY SHARP ROLL-OFF (fs= 96 kHz) Figure 10. SHORT DELAY SLOW ROLL-OFF (fs= 96 kHz) 015099871-E-01 2017/11 - 13 - [AK5552] ADC Filter Characteristics (fs= 192 kHz) (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD=1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin= "L")) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 11) (SD pin="L", SLOW pin="L") 83.7 Passband (Note 13) +0.001/0.037 dB 0 kHz PB 100.2 kHz 6.0 dB Stopband (Note 13) SB 122.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 15 Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 12) (SD pin="L", SLOW pin="H") Passband (Note 13) +0.001/0.1 dB 0 31.5 kHz PB 75.2 kHz 6.0 dB Stopband (Note 13) SB 146 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 8 1/fs Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 13) (SD pin="H", SLOW pin="L") Passband (Note 13) +0.001/0.037 dB 0 83.7 kHz PB 100.2 kHz 6.0 dB Stopband (Note 13) SB 122.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0.3 1/fs GD Group Delay (Note 14) GD 1/fs 6 Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER (Figure 14) (SD pin="H", SLOW pin="H") Passband (Note 13) +0.001/0.1 dB 0 31.5 kHz PB 75.2 kHz 6.0 dB Stopband (Note 13) SB 146 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0.4 1/fs GD Group Delay (Note 14) GD 6 1/fs Digital Filter (HPF): 3.0 dB Frequency Response 1.0 Hz FR 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The passband and stopband frequencies scale with fs. For example, PB (+0.001 dB/0.037 dB) = 0.436 fs (SHARP ROLL-OFF). For example, PB (+0.001 dB/0.1 dB) = 0.164 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099871-E-01 2017/11 - 14 - [AK5552] Figure 11. SHARP ROLL-OFF (fs= 192 kHz) Figure 12. SLOW ROLL-OFF (fs= 192 kHz) Figure 13. SHORT DELAY SHARP ROLL-OFF (fs= 192 kHz) Figure 14. SHORT DELAY SLOW ROLL-OFF (fs= 192 kHz) 015099871-E-01 2017/11 - 15 - [AK5552] ADC Filter Characteristics (fs= 384 kHz) (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD=1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin= "L")) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF) (Figure 15) (SD pin="X", SLOW pin="X") * It does not depend on the SD pin and SLOW pin. 0.1 dB Frequency 81.75 kHz Response 1.0 dB 114 kHz FR (Note 13) 137.63 kHz 3.0 dB 157.2 kHz 6.0 dB Stopband (Note 13) SB 277.4 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 7 Note 13. The passband and stopband frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. Figure 15. Frequency Response (fs = 384 kHz) 015099871-E-01 2017/11 - 16 - [AK5552] ADC Filter Characteristics (fs= 768 kHz) (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD=1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin= "L")) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF) (Figure 16) (SD pin="X", SLOW pin="X") * It does not depend on the SD pin and SLOW pin. 0.1 dB Frequency Response 26.25 kHz (Note 13) 1.0 dB 83.75 kHz FR 144.5 kHz 3.0 dB 203.1 kHz 6.0 dB Stopband (Note 13) SB 640.3 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 1/fs 5 Note 13. The passband and stopband frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. Figure 16. Frequency Response (fs = 768 kHz) 015099871-E-01 2017/11 - 17 - [AK5552] 10. DC Characteristics (Ta= 40-105 C; AVDD= 4.5-5.5 V, VDD18= 1.7-1.98 V (LDOE pin="L")) Parameter Symbol Min. TVDD= 3.0-3.6 V (LDOE pin="H") High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout= 100 A) Low-Level Output Voltage (except SDA pin: Iout= 100 A) (SDA pin: Iout= 3 mA) TVDD=1.7-1.98 V (LDOE pin="L") (Note 15) (Note 15) (Note 16) Typ. Max. Unit VIH VIL 70%TVDD - - 30%TVDD V V VOH TVDD0.5 - - V VOL VOL - - 0.5 0.4 V V (Note 17) High-Level Input Voltage (Note 15) VIH 80%TVDD V Low-Level Input Voltage (Note 15) VIL 20%TVDD V High-Level Output Voltage (Note 16) VOH TVDD0.3 V (Iout= 100 A) Low-Level Output Voltage (Note 17) (except SDA pin: Iout= 100 A) VOL 0.3 V (SDA pin: Iout= 3 mA) VOL 20%TVDD V Input Leakage Current Iin 10 A Note 15. MCLK, PDN, PW0-2, MSN, BICK (Slave Mode), LRCK (Slave Mode), TDMIN, SLOW/DCKB, SD/PMOD, CKS0/SDA (Write)/CDTI, CKS1/CAD0_I2C/CSN, CKS2/SCL/CCLK, CKS3/CAD1, DIF0/DSDSEL0, DIF1/DSDSEL1, TDM0, TDM1, PSN/CAD0_SPI, I2C, DP, HPFE/DCKS, LDOE, ODP and TEST pins. Note 16. BICK (Master Mode)/DCLK, LRCK (Master Mode)/DSDOL1, DSDOR1, SDTO1 and OVF pins. Note 17. Pins shown in Note.16 and SDA (Read) pin. The external pull-up resistors should be connected to TVDD+0.3 V or less. 015099871-E-01 2017/11 - 18 - [AK5552] 11. Switching Characteristics (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Master Clock Timing (Figure 18) fCLK 2.048 49.152 MHz Frequency dCLK 45 55 % Duty Cycle LRCK Frequency (Slave mode) (Figure 17) Normal mode (TDM1-0 bits = "00") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode fsq 108 216 kHz Quad Speed mode fso 384 kHz Oct Speed mode fsh 768 kHz Hex Speed mode Duty 45 55 % Duty Cycle TDM128 mode (TDM1-0 bits = "01") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode fsq 108 216 kHz Quad Speed mode tLRH 1/128fs ns High Time tLRL 1/128fs ns Low Time TDM256 mode (TDM1-0 bits = "10") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode tLRH 1/256fs ns High time tLRL 1/256fs ns Low time TDM512 mode (TDM1-0 bits = "11") fsn 8 54 kHz Normal Speed mode tLRH 1/512fs ns High Time tLRL 1/512fs ns Low Time LRCK Frequency (Master mode) (Figure 18) Normal mode (TDM1-0 bits = "00") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode fsq 108 216 kHz Quad Speed mode fso 384 kHz Oct Speed mode fsh 768 kHz Hex Speed mode Duty 50 % Duty Cycle TDM128 mode (TDM1-0 bits = "01") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode fsq 108 216 kHz Quad Speed mode tLRH 1/4fs ns High Time TDM256 mode (TDM1-0 bits = "10") fsn 8 54 kHz Normal Speed mode fsd 54 108 kHz Double Speed mode tLRH 1/8fs ns High Time TDM512 mode (TDM1-0 bits = "11") fsn 8 54 kHz Normal Speed mode tLRH 1/16fs ns High Time Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. 015099871-E-01 2017/11 - 19 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) Normal mode (TDM1-0 bits = "00") (8 kHz fs 216 kHz) (Figure 19) (LDOE pin = "H") BICK Period Normal Speed mode Double Speed mode Quad Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK "" (Note 19) BICK "" to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I2S Mode) BICK ""toSDTO1 tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fsn 1/128fsd 1/64fsq 32 32 25 25 - - 25 25 ns ns ns ns ns ns ns ns ns Normal mode (TDM1-0 bits = "00") (8 kHz fs 216 kHz) (Figure 19) (LDOE pin = "L") BICK Period Normal Speed mode(8 kHz fs 48 kHz) Double Speed mode(48 kHz fs 96 kHz) Quad Speed mode(96 kHz fs 192 kHz) BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK "" (Note 19) BICK "" to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I2S Mode) BICK "" to SDTO1 tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fsn 1/128fsd 1/64fsq 36 36 30 30 - - 30 30 ns ns ns ns ns ns ns ns ns Normal mode (TDM1-0 bits = "00") (fs = 384 kHz, 768 kHz) (Figure 20) BICK Period Oct Speed mode Hex Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK "" (Note 19) BICK "" to LRCK Edge (Note 19) BICK "" to SDTO1 tBCK tBCK tBCKL tBCKH tLRB tBLR tBSDD 1/64fso 1/48fsh 12 12 12 12 5 - 22 ns ns ns ns ns ns ns Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. 015099871-E-01 2017/11 - 20 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) (Figure 21) TDM128 mode (TDM1-0 bits = "01") BICK Period tBCK 1/128fsn ns Normal Speed mode tBCK 1/128fsd ns Double Speed mode tBCK 1/128fsq ns Quad Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK "" (Note 19) tBLR 14 ns BICK "" to LRCK Edge (Note 19) tBSDD 5 30 ns BICK "" to SDTO1 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time TDM256 mode (TDM1-0 bits = "10") BICK Period tBCK 1/256fsn ns Normal Speed mode tBCK 1/256fsd ns Double Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK "" (Note 19) tBLR 14 ns BICK "" to LRCK Edge (Note 19) tBSDD 5 30 ns BICK "" to SDTO1 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time TDM512 mode (TDM1-0 bits = "11") BICK Period tBCK 1/512fsn ns Normal Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK "" (Note 19) tBLR 14 ns BICK "" to LRCK Edge (Note 19) tBSDD 5 30 ns BICK "" to SDTO1 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. 015099871-E-01 2017/11 - 21 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Master mode) (Figure 22) Normal mode (TDM1-0 bits = "00") (8 kHz fs 216 kHz) BICK Period tBCK 1/64fsn ns Normal Speed mode tBCK 1/64fsd ns Double Speed mode tBCK 1/64fsq ns Quad Speed mode dBCK 50 % BICK Duty tMBLR 20 20 ns BICK "" to LRCK Edge tBSD 20 ns BICK ""to SDTO1 20 Normal mode (TDM1-0 bits = "00") (fs = 384 kHz,768 kHz) (LDOE pin = "H") BICK Period tBCK 1/64fso ns Oct speed mode tBCK 1/64fsh ns Hex speed mode dBCK 50 % BICK Duty tMBLR 4 4 ns BICK "" to LRCK Edge tBSD 4 ns BICK "" to SDTO1 4 Normal mode (TDM1-0 bits = "00") (fs = 384 kHz,768 kHz) (LDOE pin = "L") BICK Period tBCK 1/64fso ns Oct speed mode tBCK 1/48fsh ns Hex speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK "" to LRCK Edge tBSD 5 ns BICK "" to SDTO1 5 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. 015099871-E-01 2017/11 - 22 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Master mode) (Figure 22) TDM128 mode (TDM1-0 bits = "01") BICK Period tBCK 1/128fsn ns Normal Speed mode tBCK 1/128fsd ns Double Speed mode tBCK 1/128fsq ns Quad Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK "" to LRCK Edge tBSD 5 ns BICK "" to SDTO1 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 TDM256 mode (TDM1-0 bits = "10") BICK Period tBCK 1/256fsn ns Normal Speed mode tBCK 1/256fsd ns Double Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK "" to LRCK Edge tBSD 5 ns BICK "" to SDTO1 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 TDM512 mode (TDM1-0 bits = "11") BICK Period tBCK 1/512fsn ns Normal Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK "" to LRCK Edge tBSD 5 ns BICK "" to SDTO1 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. 015099871-E-01 2017/11 - 23 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Master mode) (Figure 23) DSD Audio Interface Timing (64fs mode, DSDSEL 1-0 bits = "00") tDCK 1/64fs ns DCLK Period 144 tDCKL ns DCLK Pulse Width Low 144 tDCKH ns DCLK Pulse Width High tDDD 20 ns DCLK Edge to DSDOL/R (Note 20) 20 DSD Audio Interface Timing (128fs mode, DSDSEL 1-0 bits = "01") tDCK 1/128fs ns DCLK Period 72 tDCKL ns DCLK Pulse Width Low 72 tDCKH ns DCLK Pulse Width High tDDD 10 ns DCLK Edge to DSDOL/R (Note 20) 10 DSD Audio Interface Timing (256fs mode, DSDSEL 1-0 bits = "10") tDCK 1/256fs ns DCLK Period 36 tDCKL ns DCLK Pulse Width Low 36 tDCKH ns DCLK Pulse Width High tDDD 10 ns DCLK Edge to DSDOL/R (Note 20) 10 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5552 should be reset by the PDN pin or RSTN bit. Note 20. tDDD is defined from a falling edge of DCLK "" to a DSDOL/R edge when DCKB bit = "0" and it is defined from a rising edge of DCLK "" to a DSDOL/R edge when DCKB bit = "1". 015099871-E-01 2017/11 - 24 - [AK5552] (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin="L") or 3.0-3.6 V (LDOE pin="H"), VDD18= 1.7-1.98 V (LDOE pin="L"), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-Wire Serial mode): (Figure 25) (Figure 26) tCCK 200 ns CCLK Period tCCKL 80 ns CCLK Pulse Width Low tCCKH 80 ns Pulse Width High tCDS 40 ns CDTI Setup Timing tCDH 40 ns CDTI Hold Timing tCSW 150 ns CSN "H" Time tCSS 50 ns CSN "" to CCLK "" tCSH 50 ns CCLK "" to CSN "" Control Interface Timing (I2C Bus mode): (Figure 27) fSCL 400 kHz SCL CLOCK Frequency tBUF 1.3 s Bus Free Time Between Transmissions tHD STA 0.6 s Start Condition Hold Tune (Prior to First Clock Pulse) tLow 1.3 s Clock Low Time tHIGH 0.6 s Clock High Time tSU STA 0.6 s Setup Time for Repeated Start Condition tHD DAT 0 s SDA Hold Time from SCL Falling (Note 21) tSU DAT 0.1 s SDA Setup Time from SCL Rising tR 1.0 s Rise Time of Both SDA and SCL Lines tF 0.3 s Fall Time of Both SDA and SCL Lines tSU STO 0.6 s Setup Time for Stop Condition tSP 0 50 ns Pulse Width of Spike Noise Suppressed by Input Filter Cb 400 pF Capacitive Load on Bus Power Down & Reset Timing (Figure 28) tPD 150 ns PDN Pulse Width (Note 22) tRPD 30 ns PDN Reject Pulse Width (Note 22) tPDV 583 1/fs PDN "" to SDTO1 valid (Note 23) Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 22. The AK5552 can be reset by setting the PDN pin to "L" upon power-up. The PDN pin must held "L" for more than 150 ns for a certain reset. The AK5552 is not reset by the "L" pulse less than 30 ns. Note 23. This cycle is the number of LRCK rising edges from the PDN pin = "H". 015099871-E-01 2017/11 - 25 - [AK5552] Timing Diagram [1] PCM mode 1/fCLK 50%TVDD MCLK tdCLKH tdCLKL dCLK=tdCLKHfs100 or tdCLKLfs100 1/fs 50%TVDD LRCK tLRH tLRL tBCK Duty=tLRHfs100 or tLRLfs100 VIH BICK VIL tBCKH tBCKL Figure 17. Clock Timing (Slave mode) 1/fCLK 50%TVDD MCLK tCLKH tCLKL dCLK=tCLKHfCLK100 or tCLKLfCLK100 1/fs VOH 50%TVDD LRCK Duty=tLRHfs100 tLRH 1/fBCK 50%TVDD BICK tBCKH tBCKL dBCK=tBCKHfBCK100 or tBCKLfBCK100 Figure 18. Clock Timing (Master mode) 015099871-E-01 2017/11 - 26 - [AK5552] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO1 50%TVDD Figure 19. Audio Interface Timing (Normal mode & Slave mode: 8kHzfs216kHz) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSDD SDTO1 50%TVDD Figure 20. Audio Interface Timing (Normal & Slave mode: fs=384kHz, 768kHz) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSDD SDTO1 50%TVDD tSDS tSDH VIH TDMIN VIL Figure 21. Audio Interface Timing (TDM & Slave mode) 015099871-E-01 2017/11 - 27 - [AK5552] LRCK 50%TVDD tMBLR 50%TVDD BICK tBSD 50%TVDD SDTO1 tSDS tSDH VIH TDMIN VIL Figure 22. Audio Interface Timing (Master mode) [2] DSD mode tDCK tDCKL tDCKH VOH DCLK VOL tDDD VOH DSDOL1 DSDOR1 VOL Figure 23. Audio Serial Interface Timing (Normal mode, DCKB bit= "0" or DCKB pin= "L") tDCK tDCKL tDCKH VOH DCLK VOL tDDD tDDD VOH DSDOL1 DSDOR1 VOL Figure 24. Audio Serial Interface Timing (Phase Modulation mode, DCKB bit= "0" or DCKB pin= "L") 015099871-E-01 2017/11 - 28 - [AK5552] [3] 3-Wire Serial Interface VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL Figure 25. WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL Figure 26. WRITE Data Input Timing (3-wire Serial mode) 015099871-E-01 2017/11 - 29 - [AK5552] [4] I2C Interface VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start tSU:DAT tSU:STA tSU:STO Start Stop Figure 27. I2C Bus mode Timing [5] Power-down Timing tPD VIH PDN VIL tPDV SDTO1 tRP D 50%TVDD Figure 28. Power-down & Reset Timing 015099871-E-01 2017/11 - 30 - [AK5552] 12. Functional Descriptions Digital Core Power Supply The digital core of the AK5552 is operates off of a 1.8 V power supply. Normally, this voltage is generated by the internal LDO from TVDD (3.3 V) for digital interface. The internal LDO will be powered up by setting the LDOE pin = "H". Set the LDOE pin to "L" and supply a 1.8 V power to the VDD18 pin externally when a 1.8 V is used as TVDD. Output Mode The AK5552 is able to output either PCM or DSD data. The DP pin or DP bit select the output mode. Set the PW2 pin = PW1 pin = PW0 pin = "L" or RSTN bit = "0" or PW2-1 bits = "00" to reset all channels when changing the PCM/DSD mode. The AK5552 outputs data from the SDTO1 pin by BICK and LRCK in PCM mode. DSD data are output from the DSDOL1 and DSDOR1 pin by DCLK in DSD mode. DP pin DP bit Interface L 0 PCM H 1 DSD Table 1. PCM/DSD Mode Control Master Mode and Slave Mode The AK5552 requires a master clock (MCLK), an audio serial data clock (BICK) and an output channel clock (LRCK) in PCM mode. In this case, the LRCK frequency will be the sampling frequency. Both master and slave modes are available in PCM mode. In master mode, the AK5552 internally generates BICK and LRCK clocks from MCLK inputs and outputs them from the BICK pin and the LRCK pin. MCLK must be synchronized with BICK and LRCK but the phase is not important. The MSN pin controls master/slave mode. The AK5552 is in master mode when the MSN pin = "H" and in slave mode when the MSN pin = "L". The AK5552 requires a master clock (MCLK) in DSD mode. Slave mode is not available in DSD mode, only master mode is supported. System Clock [1] PCM Mode The external system clocks, which are required to operate the AK5552, are MCLK, BICK and LRCK in PCM mode. MCLK frequency is determined based on LRCK frequency, according to the operation mode. Table 2, Table 3 and Table 4 show MCLK frequencies correspond to the normal audio rate. Set the frequency ratio between Sampling frequency and MCLK by the CKS3-0 pins (Table 5). All channels must be reset when changing the clock mode or audio interface format by the CKS2-0 pins (bits), TDM1-0 pins (bits), DIF1-0 pins (bits) and the MSN pin. In parallel control mode, all channels will be reset by the PDN pin = "L" or PW2-0 pins = "LLL". In serial control mode, all channels will be reset by RSTN bit = "0" or PW4-1 bits = "0H". A stable clock must be supplied after releasing the reset. The AK5552 integrates a phase detection circuit for LRCK. If the internal timing becomes out of synchronization in slave mode, the AK5552 is reset automatically and the phase is resynchronized. The following sequence must be executed when synchronizing multiple AK5552's. Stop all AK5552's in reset status by setting the PDN pin = "L" "H" after stopping the system clock. Make pin or register settings while all channels are in reset status. After that, input the same system clock to all AK5552's. 015099871-E-01 2017/11 - 31 - [AK5552] 32fs 48fs 64fs 96fs 128fs MCLK 192fs 32 kHz N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 192 kHz N/A N/A N/A N/A 24.576 MHz 384 kHz N/A N/A 24.576 MHz 36.864 MHz 768 kHz 24.576 MHz 36.864 MHz N/A N/A fs 256fs 8.192 MHz 12.288 MHz 24.576 MHz 384fs 12.288 MHz 18.432 MHz 36.864 MHz 512fs 16.384 MHz 24.576 MHz 768fs 24.576 MHz 36.864 MHz 1024fs 32.768 MHz N/A N/A N/A 36.864 MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not Available) Table 2 System Clock Example (Slave mode) 32fs 48fs 64fs 96fs 128fs MCLK 192fs 32 kHz N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 192 kHz N/A N/a N/A N/A 24.576 MHz 384 kHz N/A N/A 36.864 MHz 768 kHz 24.576 MHz 36.864 MHz 24.576 MHz 49.152 MHz N/A fs 256fs 8.192 MHz 12.288 MHz 24.576 MHz 384fs 12.288 MHz 18.432 MHz 36.864 MHz 512fs 16.384 MHz 24.576 MHz 768fs 24.576 MHz 36.864 MHz 1024fs 32.768 MHz N/A N/A N/A 36.864 MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not available) Table 3. System Clock Example (Master mode) 32fs 48fs 64fs 96fs 128fs MCLK 192fs 256fs 384fs 32 kHz N/A N/A N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 24.576 MHz 192 kHz N/A N/a N/A N/A 24.576 MHz 36.864 MHz 384 kHz N/A N/A 24.576 MHz 36.864 MHz N/A 768 kHz 24.576 MHz 36.864 MHz N/A N/A N/A fs 512fs 16.384 MHz 24.576 MHz 768fs 24.576 MHz 36.864 MHz 1024fs 32.768 MHz 36.864 MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not available) Table 4. System Clock Example (Auto mode) 015099871-E-01 2017/11 - 32 - [AK5552] CKS3 pin(bit) CKS2 pin(bit) CKS1 pin(bit) CKS0 pin(bit) L(0) L(0) L(0) L(0) L(0) L(0) L(0) H(1) L(0) L(0) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) L(0) L(0) L(0) H(1) L(0) H(1) L(0) H(1) H(1) L(0) L(0) H(1) H(1) H(1) H(1) L(0) L(0) L(0) H(1) L(0) L(0) H(1) H(1) L(0) H(1) L(0) H(1) L(0) H(1) H(1) H(1) H(1) L(0) L(0) H(1) H(1) L(0) H(1) H(1) H(1) H(1) L(0) H(1) H(1) H(1) H(1) MSN pin L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H MCLK Frequency 128fs 24M 192fs 36M 256fs 12M 256fs 24M 384fs 36M 384fs 18M 512fs 24M 768fs 36M 64fs 24M 32fs 24M 96fs 36M 48fs 36M NA 64fs 49.1M 1024fs 32M Speed Mode fs Range Quad Speed 108 kHz fs 216 kHz Quad Speed 108 kHz fs 216 kHz Normal Speed 8 kHz fs 54 kHz Double Speed 54 kHz fs 108 kHz Double Speed 54 kHz fs 108 kHz Normal Speed 8 kHz fs 54 kHz Normal Speed 8 kHz fs 54 kHz Normal Speed 8 kHz fs 54 kHz Oct Speed fs = 384 kHz Hex Speed fs = 768 kHz Oct Speed fs = 384 kHz Hex Speed fs = 768 kHz NA Hex Speed fs = 768 kHz Normal Speed 8 kHz fs 32 kHz NA NA L Auto H NA 8 kHz fs 216kHz fs = 384kHz, 768 kHz NA Table 5. Clock Mode (fs & MCLK Frequency) 015099871-E-01 2017/11 - 33 - [AK5552] [2] DSD Mode The AK5552 only supports master mode in DSD mode. The external clock, which is required to operate the AK5552, is MCLK in DSD mode. The AK5552 generates DCLK from MCLK inputs and DSD data outputs (DSDOL1 and DSDOR1) are synchronized with DCLK. The necessary MCLK frequencies are 512fs and 768fs (fs=32 kHz, 44.1 kHz, 48 kHz). MCLK frequency can be changed by the DCKS pin (bit). After exiting reset (PDN pin = "L" "H") upon power-up, the AK5552 is in power-down state until MCLK is input. DCKS pin (bit) MCLK Frequency L(0) 512fs H(1) 768fs Table 6. System Clock (DSD mode) (default) The AK5552 supports 64fs, 128fs and 256fs DSD sampling frequencies (fs= 32 kHz 44.1 kHz, 48 kHz). DSDSEL1-0 pins (bits) control this setting (Table 7). DSDSEL1 pin (bit) L(0) L(0) H(1) H(1) DSDSEL0 pin (bit) L(0) H(1) L(0) H(1) Frequency DSD Sampling Frequency Mode fs= 32 kHz fs= 44.1 kHz fs= 48 kHz 64fs 2.048 MHz 2.8224 MHz 3.072 MHz 128fs 4.096 MHz 5.6448 MHz 6.144 MHz 256fs 8.192 MHz 11.2896 MHz 12.288 MHz Reserved Reserved Reserved Table 7. DSD Sampling Frequency Select (default) Audio Interface Format TDM1-0 pins(bits), DIF1-0 pins(bits), SLOW pin(bit) and SD pin(bit) settings should be changed when all channel are reset condition. [1] PCM Mode 48 types of audio interface format can be selected by the TDM1-0 pins (bits), MSN pin and DIF1-0 pins (bits) (Table 8, Table 9). In all formats the serial data is MSB-first, 2's complement format. In master mode, the SDTO1 is clocked out on the falling edge of BICK. Normal output in slave mode, the SDTO1 is clocked out on the falling edge of BICK if 8 kHz fs 216 kHz. In other conditions, the data is clocked out on the prior rising edge of BICK to compensate for some delay that renders the edge of data transition near BICK falling edge. Audio interface format is distinguished in four types: Normal mode, TDM128 mode, TDM256 mode and TDM512 mode are available. The TDM1-0 pins (bits) select these modes. In Normal mode (non TDM), AIN1 and AIN2 A/D converted data is output from the SDTO1 pin. The BICK frequency must be in the rage from 48fs to 128fs (fs= 48 kHz) in slave mode if the audio interface format is in normal output (non TDM) and the interface speed is in Normal, Double or Quad mode. Bit length of A/D data is 24-bit or 32-bit and it is selected by the DIF1 pin (bit). The BICK frequency must be set to 32fs, 48fs or 64fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in OCT mode. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit) if the BICK frequency is 32fs or 48fs. It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. When the BICK frequency is 64fs, A/D data can be selected between 24-bit and 32-bit by the DIF1 pin (bit). 015099871-E-01 2017/11 - 34 - [AK5552] The BICK frequency must be set to 32fs or 48fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in HEX mode. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit). It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. The BICK frequency will be 64fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is Normal, Double or Quad mode. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The MCLK frequency must be 64fs or 96fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is OCT mode. The BICK frequency will be 64fs. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The BICK frequency will be synchronized with the MCLK frequency in master mode if the audio interface format is normal output (non TDM) and the interface speed is HEX mode. The MCLK frequency must be 32fs, 48fs or 64fs. The bit length of A/D data is 16-bit when the MCLK frequency is 32fs, 24-bit when the MCLK frequency is 48fs and 24-bit or 32-bit can be selected by the DIF1 pin (bit) when the MCLK frequency is 64fs. The DIF0 pin selects the A/D data format between MSB justified and I2S Compatible. No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Multiplex Speed TDM1 TDM0 Mode Mode pin(bit) pin(bit) MSN Pin L Normal Double Quad L(0) L(0) H L Normal OCT HEX L(0) L(0) H DIF1 DIF0 SDTO pin(bit) pin(bit) L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S * L(0) 16-bit, MSB 2 * H(1) 16-bit, I S * L(0) 24-bit, MSB 2 * H(1) 24-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S * L(0) 16-bit, MSB 2 * H(1) 16-bit, I S * L(0) 24-bit, MSB 2 * H(1) 24-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S LRCK Pol. I/O H/L I L/H I H/L I L/H I H/L O L/H O H/L O L/H O I I I I I I I I O O O O O O O O BICK Freq. 48-128fs 48-128fs 64-128fs 64-128fs 64fs 64fs 64fs 64fs 32fs 32fs 48fs 48fs 64fs 64fs 64fs 64fs 32fs 32fs 48fs 48fs 64fs 64fs 64fs 64fs I/O I I I I O O O O I I I I I I I I O O O O O O O O MCLK Freq. I/O 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32fs I 32fs I 48fs I 48fs I 64-96fs I 64-96fs I 64-96fs I 64-96fs I Table 8. Audio Interface Format (Normal mode) 015099871-E-01 2017/11 - 35 - [AK5552] No. Multiplex Speed TDM1 TDM0 Mode Mode pin(bit) pin(bit) 24 25 26 Normal 27 TDM128 Double 28 Quad 29 30 31 32 33 34 35 Normal TDM256 Double 36 37 38 39 40 41 42 43 TDM512 Normal 44 45 46 47 MSN pin L L(0) H(1) H L H(1) L(0) H L H(1) H(1) H DIF1 DIF0 pin(bit) pin(bit) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) SDTO 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S LRCK Edg. I/O I I I I O O O O I I I I O O O O I I I I O O O O BICK Freq. I/O 128fs I 128fs I 128fs I 128fs I 128fs O 128fs O 128fs O 128fs O 256fs I 256fs I 256fs I 256fs I 256fs O 256fs O 256fs O 256fs O 512fs I 512fs I 512fs I 512fs I 512fs O 512fs O 512fs O 512fs O MCLK Freq. I/O 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 512-1024fs I 512-1024fs I 512-1024fs I 512-1024fs I Table 9. Audio Interface Format (TDM mode) 015099871-E-01 2017/11 - 36 - [AK5552] Cascade Connection in TDM mode The AK5552 supports cascade connection in TDM mode. All A/D converted data of connected AK5552 are output from the SDTO1 pin of the last AK5552 by cascade connection. When the ODP pin = "L", a cascade connection of one devices in TDM128 mode, two devices in TDM256 mode and four devices in TDM512 mode are supported. Figure 29 shows a connection example. When the ODP pin = "H", a cascade connection of two up to sixteen devices is available. When using multiple devices in slave mode on cascade connection, internal operation timing of each device may differ for one MCLK cycle depending on MCLK and BICK input timings. To prevent this timing difference, BICK "" should be more than 10ns from MCLK "" as shown in Table 10. To realize this timing, BICK divided by two should be input on a falling edge of MCLK as shown in Figure 54 when MCLK=2xBICK (normal speed 1024fs mode). When MCLK=BICK (normal speed 512fs mode), MCLK and BICK should be input in-phase as shown in Figure 55 to satisfy the timing shown in Table 10. 256fs, 512fs or 1024fs AK5552 #1 MCLKI 48kHz LRCK 256fs BICK 256fs, 512fs or 1024fs TDMIN 48kHz GND 512fs SDTO1 BICK SDTO1 GND AK5552 #2 AK5552 #2 MCLKI TDMIN TDMIN LRCK LRCK BICK TDMIN LRCK Master mode Slave mode MCLKI AK5552 #1 MCLKI BICK SDTO1 SDTO1 Slave mode Slave mode AK5552 #3 MCLKI TDMIN LRCK BICK SDTO1 Slave mode AK5552 #8 AK5552 #4 MCLKI LRCK BICK MCLKI TDMIN 8ch TDM SDTO1 TDMIN LRCK BICK 16ch TDM SDTO1 Slave mode Slave mode TDM256 TDM512 Figure 29. Cascade Connection 015099871-E-01 2017/11 - 37 - [AK5552] LRCK 0 1 2 11 12 13 23 24 31 0 1 2 11 12 13 23 24 31 0 1 BICK(64fs) SDTO1 1 13 12 11 23 22 0 23 22 13 1 12 11 0 31 23: MSB, 0: LSB AIN1 Data AIN2 Data Figure 30. Mode 0/4 Timing (Normal mode, Normal/Double/Quad Speed mode, MSB Justified, 24-bit) LRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK(64fs) SDTO1 23 22 2 1 0 23 22 2 1 0 23: MSB, 0: LSB AIN1 Data AIN2 Data Figure 31. Mode 1/5 Timing (Normal mode, Normal/Double/Quad Speed mode, I2S Compatible, 24-bit) LRCK 0 1 2 11 12 13 20 21 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO1 12 11 22 20 19 31 30 1 0 31 30 22 12 11 20 19 1 0 31 31: MSB, 0: LSB AIN1 Data AIN2 Data Figure 32. Mode 2/6 Timing (Normal mode, Normal/Double/Quad Speed mode, MSB Justified, 32-bit) LRCK 0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1 BICK(64fs) SDTO1 31 30 16 15 14 3 2 1 0 31 30 16 15 14 3 2 1 0 31: MSB, 0: LSB AIN1 Data AIN2 Data Figure 33. Mode 3/7 Timing (Normal mode, Normal/Double/Quad Speed mode, I2S Compatible, 32-bit) 015099871-E-01 2017/11 - 38 - [AK5552] 32 BICK LRCK (Master) LRCK (Slave) BICK (32fs) SDTO1 (O) 0 15 14 9 8 7 6 1 0 15 14 9 8 7 6 1 AIN1 Data AIN2 Data 16 BICK 16 BICK 0 15 14 Figure 34. Mode 8/16 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 16-bit) 32 BICK LRCK (Master) LRCK (Slave) BICK (32fs) SDTO1 (O) 0 15 14 9 8 7 6 1 0 15 14 9 8 7 6 1 AIN1 Data AIN2 Data 16 BICK 16 BICK 0 15 14 Figure 35. Mode 9/17 Timing (Normal mode, OCT/HEX Speed mode, I2S Compatible, 16-bit) 48 BICK LRCK (Master) LRCK (Slave) BICK (48fs) SDTO1 (O) 0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 AIN1 Data AIN2 Data 24 BICK 24 BICK 1 0 23 22 Figure 36. Mode 10/18 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 24-bit) 48 BICK LRCK (Master) LRCK (Slave) BICK (48fs) SDTO1 (O) 0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 AIN1 Data AIN2 Data 24 BICK 24 BICK 1 0 23 22 Figure 37. Mode 11/19 Timing (Normal mode, OCT/HEX Speed mode, I2S Compatible, 24-bit) 015099871-E-01 2017/11 - 39 - [AK5552] 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1 (O) 23 22 15 8 7 0 23 22 15 8 7 0 AIN1 Data AIN2 Data 32 BICK 32 BICK 23 22 Figure 38. Mode 12/20 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 24-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1 (O) 23 22 15 8 7 0 23 22 15 8 7 0 AIN1 Data AIN2 Data 32 BICK 32 BICK 23 22 Figure 39. Mode 13/21 Timing (Normal mode, OCT/HEX Speed mode, I2S Compatible, 24-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1 (O) 0 31 30 17 16 15 14 1 0 31 30 17 16 15 14 AIN1 Data AIN2 Data 32 BICK 32 BICK 1 0 31 30 Figure 40. Mode 14/22 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 32-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1 (O) 0 31 30 17 16 15 14 1 0 31 30 17 16 15 14 AIN1 Data AIN2 Data 32 BICK 32 BICK 1 0 31 30 Figure 41. Mode 15/23 Timing (Normal mode, OCT/HEX Speed mode, I2S Compatible, 32-bit) 015099871-E-01 2017/11 - 40 - [AK5552] 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 Data 1 Data 2 32 BICK 32 BICK 23 22 Figure 42. Mode 24/28 Timing (TDM128 mode, MSB Justified, 24-bit) 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 Data 1 Data 2 32 BICK 32 BICK 23 22 Figure 43. Mode 25/29 Timing (TDM128 mode, I2S Compatible) 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 1 0 31 30 1 Data 1 Data 2 32 BICK 32 BICK 0 31 30 Figure 44. Mode 26/30 Timing (TDM128 mode, MSB Justified) 015099871-E-01 2017/11 - 41 - [AK5552] 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 1 0 31 30 1 Data 1 Data 2 32 BICK 32 BICK 0 31 30 Figure 45. Mode 27/31 Timing (TDM128 mode, I2S Compatible) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 23 22 (#3 SDTO1) #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 32 BICK 0 23 22 32 BICK Figure 46. Mode 32/36 Timing (TDM256 mode, MSB Justified, 24-bit) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 23 22 (#3 SDTO1) #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 0 32 BICK 23 22 0 32 BICK 23 22 0 23 22 32 BICK 0 32 BICK 23 22 0 32 BICK 23 22 32 BICK 32 BICK 0 23 32 BICK Figure 47. Mode 33/37 Timing (TDM256 mode, I2S Compatible, 24-bit) 015099871-E-01 2017/11 - 42 - [AK5552] 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 31 30 (#3 SDTO1) #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 32 BICK 0 31 30 32 BICK Figure 48. Mode 34/38 Timing (TDM256 mode, MSB Justified, 32-bit) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 31 30 (#3 SDTO1) #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 1 0 31 30 32 BICK 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 32 BICK 0 31 32 BICK Figure 49. Mode 35/39 Timing (TDM256 mode, I2S Compatible, 32-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 23 22 0 23 33 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 #8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 23 22 (#7 SDTO1) #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 32 BICK 31 30 32 BICK Figure 50. Mode 40/44 Timing (TDM512 mode, MSB Justified, 24-bit) 015099871-E-01 2017/11 - 43 - [AK5552] 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 #8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 23 22 (#7 SDTO1) #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 32 BICK 0 23 32 BICK Figure 51. Mode 41/45 Timing (TDM512 mode, I2S Compatible, 24-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 #8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 31 30 (#7 SDTO1) #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 0 1 31 30 32 BICK 1 0 31 30 32 BICK 0 1 31 30 32 BICK 32 BICK 1 0 31 30 32 BICK Figure 52. Mode 42/46 Timing (TDM512 mode, MSB Justified, 32-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 #8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMIN (I) 31 30 (#7 SDTO1) #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 0 1 31 30 32 BICK 1 0 31 30 32 BICK 0 1 31 30 32 BICK 32 BICK 1 0 32 BICK 31 32 BICK Figure 53. Mode 43/47 Timing (TDM512 mode, I2S Compatible, 32-bit) Parameter MCLK "" to BICK "" BICK "" to MCLK"" Symbol Min. tMCB tBIM 10 10 Typ. Max Unit ns ns Table 10. TDM Mode Clock Timing 015099871-E-01 2017/11 - 44 - [AK5552] VIH MCLK VIL tMCB tBIM VIH BICK VIL Figure 54. Audio Interface Timing (Slave mode, TDM mode MCLK=2xBICK) VIH VIL MCLK tMCB tBIM VIH VIL BICK Figure 55. Audio Interface Timing (Slave mode, TDM mode MCLK=BICK) [2] DSD mode DSD output is available only when the AK5552 is in Master mode. The DCLK frequency can be selected from 64fs, 128fs and 256fs by setting the DSDSEL1-0 pins (bits). The AK5552 enters Phase Modulation mode by setting PMOD pin = "H" or PMOD bit = "1". It does not support Phase Modulation mode when the DCLK frequency is 256fs. DCKB bit controls DCLK polarity. DCLK (64fs, 128fs, 256fs) DCKB bit="1" DCLK (64fs, 128fs, 256fs) DCKB bit="0" DSDOL, DSDOR Normal D0 DSDOL,DSDOR Phase Modulation D0 D1 D1 D2 D1 D2 D3 D2 D3 Figure 56. DSD Mode Timing 015099871-E-01 2017/11 - 45 - [AK5552] Channel Summation (PCM mode, DSD mode) Channel Summation function improves the dynamic range and S/N performance by averaging all A/D data of multiple-channel that the same signal is input. The AK5552 supports 2-to-1 mode. 2-to-1 mode (Mono mode) Improve the dynamic range and S/N for 3 dB (2 dB in DSD mode) by averaging two channels. Not-Summation mode (Stereo mode) Normal mode that does not execute Summation is called as Not-Summation mode or Stereo mode. Refer to the section "CH Power Down & Channel Summation mode" for details. Optimal Data Placement Mode (PCM Mode, DSD Mode) Assigned data to the SDTO1 slot is controlled by the ODP pin setting in parallel control mode. When the ODP pin = "L", the data is output by Fixed Data Placement mode. Channel assignment of data slot is fixed regardless of enable/disenable of channel summation. For example, averaging data of two channels are output to both channel slots. When the ODP pin = "H", the data is output by Optimal Data Placement mode that is uses data slot more efficiently. In Optimal Data Placement mode, there are no data redundant of channel summation, and the data is output in MSB justified. Therefore, the maximum number of connecting device in cascade connection will be increased. If the AK5552 is set to 2-to-1 mode (Mono Mode), four devices can be connected in TDM128 mode, eight devices can be connected in TDM256 mode and sixteen devices can be connected in TDM512 mode. In serial control mode, the data output is Optimal Data Placement mode regardless of the ODP pin setting. Refer to "CH Power Down & Channel Summation mode" for details. CH Power Down & Channel Summation (PCM mode, DSD mode) [1] Parallel mode The setting of the PW2-0 pins and the ODP pin controls the channel power-down and channel summation mode setting in parallel mode (Table 11 - Table 16). The PDN pin must be set to "L" when changing the ODP pin and the PW2-0 pins. The power consumption of the device can be improved by setting unused channels to power-down state. In this case, the channel circuit that is powered down will be reset. When the ODP pin = "L", the PW2-0 pins control channel power-down and 2-to-1 mode. In 2-to-1 mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1 and DSDOR1) by dividing into half amplitude. 015099871-E-01 2017/11 - 46 - [AK5552] PW2 PW1 PW0 Power ON/OFF pin pin pin Ch2 Ch1 L L L OFF OFF L L H ON OFF L H L OFF ON L H H ON ON H L L OFF OFF H L H ON OFF H H L OFF ON H H H ON ON Table 11. Channel Power ON/OFF (Parallel Control Mode, ODP pin= "L") Data on Slot PW2 PW1 PW0 pin pin pin Slot 2 Slot 1 L L L All "0" All "0" L L H Not Available L H L Not Available L H H (CH1+2)/2 (CH1+2)/2 H L L All "0" All "0" H L H CH2 All "0" H H L All "0" CH1 H H H CH2 CH1 Table 12. Slot Data Assign (Parallel Control Mode, ODP pin= "L") When the ODP pin = "H", the AK5552 becomes optimal data placement mode and data slots can be used efficiently. The PW2-0 pins control power down, 2-to-1 mode. In 2-to-1 mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1) by dividing into half amplitude. PW2 PW1 PW0 Power ON/OFF pin pin pin Ch2 Ch1 L L L OFF OFF L L H ON ON L H L ON ON L H H ON ON H L L ON ON H L H ON ON H H L ON ON H H H ON ON Table 13. Channel Power ON/OFF (Parallel Control mode, ODP pin= "H") 015099871-E-01 2017/11 - 47 - [AK5552] Data on Slot PW2 PW1 PW0 pin pin pin Slot 2 Slot 1 L L L All "0" All "0" L L H (CH1+2)/2 (CH1+2)/2 L H L CH2 CH1 L H H All "0" (CH1+2)/2 H L L CH2 CH1 H L H (CH1+2)/2 (CH1+2)/2 H H L CH2 CH1 H H H All "0" (CH1+2)/2 Table 14. Slot Data Assign (Parallel Control mode, ODP pin= "H", Normal Output) Data on Slot PW2 PW1 PW0 pin pin pin Slot 2 Slot 1 L L L All "0" All "0" L L H (CH1+2)/2 (CH1+2)/2 L H L CH2 CH1 L H H TDMIN (CH1+2)/2 H L L CH2 CH1 H L H (CH1+2)/2 (CH1+2)/2 H H L CH2 CH1 H H H TDMIN (CH1+2)/2 Table 15. Slot Data Assign (Parallel Control mode, ODP pin= "H", TDM128) Data on Slot PW2 PW1 PW0 pin pin pin Slot 2 Slot 1 L L L All "0" All "0" L L H (CH1+2)/2 (CH1+2)/2 L H L CH2 CH1 L H H TDMIN (CH1+2)/2 H L L CH2 CH1 H L H (CH1+2)/2 (CH1+2)/2 H H L CH2 CH1 H H H TDMIN (CH1+2)/2 Table 16. Slot Data Assign (Parallel Control mode, ODP pin= "H", TDM256 & TDM512) 015099871-E-01 2017/11 - 48 - [AK5552] [2] Serial Mode In 3-wire serial mode or I2C mode, PW1-2 bits control the power of AIN1-2 channels independently. AINn channel is powered down when PWn bit = "0" (n=1-2) and AINn channel is in normal operation when PWn bit = "1". The power-down channel is reset status and outputs all "0". The 2-to-1 mode is controlled by MONO2-1 bits. RSTN bit must be "0" when changing the setting of MONO1-2 bits and PW1-2 bits. Data on Slot (Normal Output) MONO2 MONO1 bit bit Slot 2 Slot 1 0 0 CH2 CH1 0 1 (CH1+2)/2 (CH1+2)/2 1 0 CH2 CH1 1 1 All "0" (CH1+2)/2 Table 17. Slot Data Assign (Serial Control mode, Normal Output or DSD mode) Data on Slot (TDM Output) MONO2 MONO1 bit bit Slot 2 Slot 1 0 0 CH2 CH1 0 1 (CH1+2)/2 (CH1+2)/2 1 0 CH2 CH1 1 1 TDMIN (CH1+2)/2 Table 18. Slot Data Assign (Serial Control mode, TDM128) Data on Slot (TDM Output) MONO2 MONO1 bit bit Slot 2 Slot 1 0 0 CH2 CH1 0 1 (CH1+2)/2 (CH1+2)/2 1 0 CH2 CH1 1 1 TDMIN (CH1+2)/2 Table 19. Slot Data Assign (Serial Control mode, TDM256 & TDM512) 015099871-E-01 2017/11 - 49 - [AK5552] Data Slot Configuration [1] PCM mode LRCK Period = 1/fs Normal Output SDTO1 pin Slot 1 Slot 2 LRCK Period = 1/fs TDM128 SDTO1 pin Slot 1 Slot 2 TDMI LRCK Period = 1/fs TDM256 SDTO1 pin Slot 1 Slot 2 TDMI LRCK Period = 1/fs TDM512 SDTO1 pin 1 2 TDMI Figure 57. Slot Assign in PCM mode [2] DSD mode LRCK Period = 1/fs DSDOL1 pin Slot 1 DSDOR1 pin Slot 2 Figure 58. Slot Assign in DSD mode 015099871-E-01 2017/11 - 50 - [AK5552] Digital Filter Setting (PCM mode) The AK5552 has four types of digital filters and they can be selected by SD pin (bit) and SLOW pin (bit). The filter setting is not available in OCT speed mode, HEX speed mode and DSD mode. So the setting of the digital filter is ignored. SD pin (bit) L (0) L (0) H (1) H (1) SLOW Filter pin (bit) L (0) Sharp Roll-off Filter H (1) Slow Roll-off Filter L (0) Short Delay Sharp Roll-off Filter H (1) Short Delay Slow Roll-off Filter Table 20. Digital Filter Setting Digital HPF (PCM mode) The AK5552 has a digital high-pass filter for DC offset (include internal offset) cancelation. The digital high-pass filter is enabled by setting the HPFE pin (bit) = "H (1)". The cut-off frequency of the high-pass filter is fixed 1.0 Hz when fs= 48 kHz (Normal Speed mode), 96 kHz (Double Speed mode) or 192 kHz (Quad Speed mode). The high-pass filter is not available in OCT speed mode, HEX speed mode and DSD mode. So that the setting of the HPFE pin is ignored. The high pass-filter setting should be changed when all channels are reset condition. Overflow Detection (PCM mode, DSD mode) [1] PCM mode The AK5552 has an overflow detect function for the analog input. The OVF pin outputs "H" if one of AIN1 - 2 channels overflows (more than 0.3 dBFS). The OVF pin returns to "L" when analog input overflows are resolved. The OVF output for overflowed analog input has the same group delay as the ADC. [2] DSD mode Overflow Detection (Error Detection Function) The OVF pin outputs "H" if any channel's DSD modulators overflows. The OVF pin returns to "L" when overflows are resolved. 015099871-E-01 2017/11 - 51 - [AK5552] LDO The voltage range of TVDD is from 1.7 V to 1.98 V or from 3.0 V to 3.6 V. Set ON/OFF of the LDO by the LDOE pin according to TVDD voltage (Table 21). The internal LDO is switched ON/OFF depending on TVDD voltage range. LDOE PDN LDO L L H H L H L H OFF OFF OFF ON VDD18 pin External Power Input 1.7-1.98 V External Power Input 1.7-1.98 V Pulled Down by 500 internally LDO Voltage Output Table 21. LDO Control Additional Voltage Range to TVDD pin 1.7-1.98 V 1.7-1.98 V 3.0-3.6 V 3.0-3.6 V [1] TVDD=1.7-1.98 V, LDO is OFF (LDOE pin = "L") The internal LDO does not work properly when the TVDD voltage range is from 1.7 V to 1.98 V. Set the LDOE pin to "L" to switch OFF the LDO. A 1.7 V ~ 1.98 V is supplied from the VDD18 pin for internal logic circuits. The voltage difference between TVDD and VDD18 must be 0.1 V or less. [2] TVDD=3.0-3.6 V, LDO is ON (LDOE pin = "H") The internal LDO should be ON when the TVDD voltage range is from 3.0 V to 3.6 V. It will be the power supply for the internal logic circuit. The VDD18 pin will be a connection terminal for a stabilization capacitor. It is not possible to supply the power to external circuits from the VDD18 pin. Reset The AK5552 must be reset upon power up or when changing the clock setting or clock frequency. It can be reset by the PDN pin and PW2-0 pins or RSTN bit and PW4-1 bits. 015099871-E-01 2017/11 - 52 - [AK5552] Power Down Function/ Sequence The AK5552 enters power-down mode by setting the PDN pin to "L". Digital filters are reset at the same time. [1] PCM Mode In slave mode, internal power down signal (Internal PDN) is released by inputting MCLK, BICK and LRCK after setting the PDN pin to "H". In master mode, The Internal PDN is released by inputting MCLK after setting the PDN pin to "H". Initialization cycle starts when the Internal PDN is released. The output data of SDTO will be valid in 583 1/fs after exiting power-down mode in slave mode, it will be valid in 578 1/fs after exiting power-down mode in master mode. During initialization, the ADC digital outputs of both channels are in 2's complement format and forced to "0". The ADC outputs settle to data correspondent to the input signals after the end of initialization. This settling takes approximately the group delay time. Power PDN pin (1) VDD18 pin (2) Internal PDN (3) Internal State Power -down Initialize Normal Operation Power -down ADC In (Analog) GD (5) (5) GD (4) (4) ADC Out (Digital) "0"data Idle Noise "0"data Idle Noise (6) Clock In Don't care Don't care MCLK,LRCK,BICK Figure 59. Power-Up/Down Sequence Example Notes: (1) The PDN pin should be held to "L" for more than 150 ns after AVDD and TVDD are powered up. (2) a. LDOE pin = "H", I2C pin = "H" and PSN pin = "H" (Parallel Mode): The internal LDO is powered up by releasing PDN pin to "H". The Internal PDN is released by toggling MCLK for 16384times. b. LDOE pin = "H" and PSN pin = "L" (Register Mode): The internal LDO is powered up by releasing PDN pin to "H". The internal PDN is released by toggling internal oscillator clock for 16384 times (max. 10 ms). c. LDOE pin = "L": The internal PDN is released in 1 ms (max.) after releasing PDN pin to "H". During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I2C bus as the AK5552 should be avoided in this period to prevent system errors. 015099871-E-01 2017/11 - 53 - [AK5552] (3) Initialization cycle is 583/fs in slave mode and 578/fs in master mode. (4) The ADC output data is "0" during initialization cycle and power-down mode. (5) The digital output corresponding to analog input has group delay (GD). Internal PDN Release Sequence Figure 60. Internal PDN Release Sequence 015099871-E-01 2017/11 - 54 - [AK5552] [2] DSD mode The Internal PDN is released by inputting MCLK after setting the PDN pin to "H". PDN pin Internal PDN (1) MCLK In Don't care Internal State Power-Down Don't care Initialize Normal Operation Power-Down (2) ADC In (Analog) (6) (4) OVF-pin (5) (3) DSD Out (Digital) "L" (-full scale data) normal data abnormal data normal data "L" (-full scale data) Figure 61. DSD Operation Timing Notes: (1) The internal LDO is powered up by releasing PDN pin to "H". The internal PDN is released by toggling internal oscillator clock for 16384 times (max. 10ms). The internal PDN is released in max. 1 ms after releasing PDN pin to "H". Register writings become available when the internal PDN changes to "1". During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I2C bus as the AK5552 should be avoided in this period to prevent system errors. (2) Initialization operation will be completed in 583/fs. (3) DSD output pins output "L" (-full scale data) during power down and initializing operation. DSD output pins output full scale data during phase modulation mode, a reset sequence and a CH power down status. (4) The OVF pin outputs "H" when an excessive signal is input and overflow is detected at internal modulator. The OVF pin status will change after group delay period from the excessive input. (5) In the case above (4), the DSD output data will not be correct. (6) The OVF pin returns to "L" when the input signal settled to a normal state and overflow status of the internal modulator is resolved. The OVF pin status will change after group delay period from the normal input. 015099871-E-01 2017/11 - 55 - [AK5552] Operation Mode Control Operation modes of the AK5552 are set by pins or registers. In parallel mode, the operation mode is set by pin and register settings are invalid. Therefor the functions that needs register settings are not available in parallel mode. For register accessing, 3-wire serial and I2C bus communications are available. This control mode of the AK5552 is selected by the I2C pin and the PSN pin. In serial control mode, register settings are prioritized so that all pin settings except the MSN pin setting are ignored. I2C pin L L H H PSN pin Control Mode L 3-wire Serial H 3-wire Serial L I2C Bus H Parallel Table 22. Control Mode Register Control Interface (1) 3-wire Serial Control mode (I2C pin = "L") The internal registers may be written through the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to "1", Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max). The internal registers are initialized by setting the PDN pin = "L". In serial mode, an internal timing circuit is reset by setting RSTN bit = "0" but register values are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1=CAD1, C0=CAD0) READ/WRITE (Fixed to "1", Write only) Register Address Control Data Figure 62. Control I/F Timing * The AK5552 does not support read commands in 3-wire serial control mode. * When the AK5552 is in power down mode (PDN pin = "L"), a writing into the control registers is prohibited. * The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more during CSN is "L". 015099871-E-01 2017/11 - 56 - [AK5552] (2) I2C-bus Control mode (I2C pin = "H" and PSN pin = "L") The AK5552 supports the fast-mode I2C-bus (max: 400 kHz, Ver1.0). (2)-1. WRITE Operations Figure 63 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 69). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as "00100". The next bits are CAD1-0 (device address bits). This bits identifies the specific device on the bus. The hard-wired input pins (CAD1-0 pins) set these device address bit (Figure 64). If the slave address matches that of the AK5552, the AK5552 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 70). R/W bit = "1" indicates that the read operation is to be executed. "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK5552. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 65). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 66). The AK5552 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 69). The AK5552 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5552 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds "07H" prior to generating a stop condition, the address counter will "roll over" to "00H" and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 71) except for the START and STOP conditions. S T A R T SDA S S T O P R/W= "0" Slave Address 1st byte Sub Address(n) A C K 2nd byte Data(n) A C K Data(n+1) A C K 3rd byte Data(n+x) A C K A C K P A C K Figure 63. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 R/W A1 A0 D1 D0 (CAD0 and CAD1 are set by pins) Figure 64. The First Byte 0 0 0 A4 A3 A2 Figure 65. The Second Byte D7 D6 D5 D4 D3 D2 Figure 66. Byte Structure After The Second Byte 015099871-E-01 2017/11 - 57 - [AK5552] (2)-2. READ Operations Set the R/W bit = "1" for the READ operation of the AK5552. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds "07H" prior to generating stop condition, the address counter will "roll over" to "00H" and the data of "00H" will be read out. The AK5552 supports two basic read operations: Current Address Read and Random Address Read. (2)-2-1. Current Address Read The AK5552 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address "n", the next CURRENT READ operation would access data from the address "n+1". After receipt of the slave address with R/W bit "1", the AK5552 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK5552 ceases transmission. S T A R T SDA S S T O P R/W= "1" Slave Address Data(n) A C K Data(n+1) A C K Data(n+2) A C K Data(n+x) A C K A C K P A C K Figure 67. Current Address Read (2)-2-2. Random Address Read The random read operation allows the master to access any memory location at random. Prior to issuing a slave address with the R/W bit ="1", the master must execute a "dummy" write operation first. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit ="1". The AK5552 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK5552 ceases transmission. S T A R T SDA S S T A R T R/W= "0" Slave Address Sub Address(n) A C K S A C K S T O P R/W= "1" Slave Address Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 68. Random Address Read 015099871-E-01 2017/11 - 58 - [AK5552] SDA SCL S P start condition stop condition Figure 69. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 70. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 71. Bit Transfer on the I2C-Bus 015099871-E-01 2017/11 - 59 - [AK5552] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H Register Name Power Management1 Power Management2 Control 1 Control 2 Control 3 DSD TEST1 TEST2 D7 1 0 0 0 DP 0 TST7 0 D6 1 0 CKS3 TDM1 0 0 TST6 0 D5 1 0 CKS2 TDM0 0 DCKS TST5 0 D4 1 0 CKS1 0 0 0 TST4 0 D3 1 0 CKS0 0 0 PMOD TST3 0 D2 1 MONO2 DIF1 0 0 DCKB TST2 0 D1 PW2 MONO1 DIF0 0 SD DSDSEL1 TST1 0 D0 PW1 RSTN HPFE 0 SLOW DSDSEL0 TST0 TRST Note 24. Data must not be written into addresses from "06H" to "1FH". Note 25. The bits indicated as "0" must contain a "0" value. When RSTN bit is set to "0", the internal digital filter and the control block are reset but the register values are not initialized. Note 26. When the PDN pin is set to "L", all registers are initialized to their default values. Register Definitions Addr 00H Register Name D7 D6 Power Management1 1 1 R/W R/W R/W Default 1 1 PW4-1: Power Down control for channel 4-1 0: power OFF 1: power ON (default) D5 1 R/W 1 D4 1 R/W 1 D3 1 R/W 1 Addr 01H Register Name D7 D6 D5 D4 D3 Power Management2 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) Internal clock timings are reset but registers are not reset. D2 1 R/W 1 D2 MONO2 R/W 0 D1 PW2 R/W 1 D0 PW1 R/W 1 D1 MONO1 R/W 0 D0 RSTN R/W 1 D1 DIF0 R/W 0 D0 HPFE R/W 1 MONO2-1: Channel Summation Mode Select (Table 17-Table 19) 00: Not- Summation mode (default) 01: 2-to-1 mode (Fixed Data Placement) 10: Not- Summation mode 11: 2-to-1 mode (Optimal Data Placement) Addr 02H Register Name D7 D6 D5 D4 Control 1 0 CKS3 CKS2 CKS1 R/W R/W R/W R/W R/W Default 0 0 0 0 HPFE: High Pass Filter Enable 0: High Pass Filter OFF 1: High Pass Filter ON (default) When this bit is "1", digital HPFs for all channels are ON. D3 CKS0 R/W 0 D2 DIF1 R/W 0 DIF1-0: Audio Data Interface Modes Select (Table 8, Table 9) Select A/D data bit length (24-bit/32-bit) and the format (MSB justified/ I2S Compatible) CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 5) Select Sampling Speed and MCLK frequency. 015099871-E-01 2017/11 - 60 - [AK5552] Addr 03H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 2 0 TDM1 TDM0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 TDM1-0: TDM Modes Select (Table 9) Select the A/D data output mode from Normal, TDM128, TDM256 and TDM512 modes. Addr 04H Register Name D7 D6 D5 Control 3 DP 0 0 R/W R/W R/W R/W Default 0 0 0 SLOW: Slow Roll-off Filter Select (Table 20) 0: Sharp Roll-off (default) 1: Slow Roll-off Select Roll-off characteristic of the digital filter. SD: Short Delay Select (Table 20) 0: Normal Delay (default) 1: Short Delay Select group delay of the digital filter. DP: DSD Mode Select 0: PCM Mode (default) 1: DSD Mode Select Output Mode. Addr Register Name D7 D6 05H DSD 0 0 R/W R/W R/W Default 0 0 DSDSEL1-0: Select the Frequency of DCLK 00: 64fs (default) 01: 128fs 10: 256fs 11: Reserved D5 DCKS R/W 0 D4 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D3 PMOD R/W 0 D2 0 R/W 0 D1 SD R/W 0 D0 SLOW R/W 0 D2 D1 D0 DCKB DSDSEL1 DSDSEL0 R/W R/W R/W 0 0 0 DCKB: Polarity of DCLK 0: DSD data is output from DCLK Falling Edge (default) 1: DSD data is output from DCLK Rising Edge PMOD: DSD Phase Modulation Mode 0: Not Phase Modulation Mode (default) 1: Phase Modulation Mode DSD Output Phase Modulation Mode Enable DCKS: Master Clock Frequency Select at DSD Mode (DSD Only) 0: 512fs (default) 1: 768fs 015099871-E-01 2017/11 - 61 - [AK5552] Addr 06H Register Name D7 D6 D5 D4 D3 D2 D1 D0 TEST 1 TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 TST7-0: Test register. This register must be used as the default setting. Normal operation is not guaranteed if all bits are not "0". Addr 07H Register Name D7 D6 D5 D4 D3 D2 D1 D0 TEST 2 0 0 0 0 0 0 0 TRST R/W R/W R/W R/W R/W R/W R/W R/W W Default 0 0 0 0 0 0 0 0 TRST: Test register. This register must be "0". This register must be used as the default setting. Normal operation is not guaranteed if all bits are not "0". 015099871-E-01 2017/11 - 62 - [AK5552] 34 33 32 31 30 29 28 27 26 25 SLOW/DCKB 35 CKS3/CAD1 CKS2/SCL/CCLK CKS1/CAD0_I2C/CSN CKS0/SDA/CDTI OVF TESTO1 SDTO1 TDMIN/DSDOR1 LRCK/DSDOL1 BICK/DCLK DIF1/DSDSEL1 TDM0 TDM1 PSN/CAD0_SPI I2C DP HPFE/DCKS LDOE ODP AIN1P AIN1N AK5552 Top View MSN PW2 PW1 PW0 PDN VDD18 DVSS TVDD MCLK TEST TESTIN6 TESTIN5 24 23 22 21 20 19 18 17 16 15 14 13 Mode Setting Controller 0.1 4.7 + + 0.1 10 Digital 3.3V Mater Clock 0.1 + 10 AIN2 AIN2+ Analog 5V Analog 5V 20 100 + 0.1 1 2 3 4 5 6 7 8 9 10 11 12 AIN1+ AIN1 DIF0/ DSDSEL0 Controller NC VREFL1 VREFH1 AIN2N AIN2P AVDD AVSS TESTIN1 TESTIN2 TESTIN3 TESTIN4 NC Mode Setting 37 38 39 40 41 42 43 44 45 46 47 48 SD/PMOD 36 Mode Setting fs 64fs 13. Recommended External Circuits Figure 72 shows recommended external connection. Figure 72. Typical Connection Diagram Note 27. All digital input pins must not be allowed to float. 015099871-E-01 2017/11 - 63 - [AK5552] 1. Grounding and Power Supply Decoupling The AK5552 requires careful attention to power supply and grounding arrangements. Normally AVDD and TVDD are supplied from analog supply of the system. The power-up sequence between AVDD1 and TVDD are not critical when AVDD and TVDD are supplied separately. DVSS and AVSS must be connected to the same analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. Reference Voltage The differential voltage between the VREFH1 pin and the VREFL1 pin is the common voltage of A/D conversion. The VREFL1 pins are normally connected to AVSS. In order to remove a high frequency noise, connect a 20 resistor between the VREFH1 pins and analog 5 V supply, and connect a 0.1 F ceramic capacitor in parallel with an 100 F electrolytic capacitor between the VREFH1 pin and the VREFL1 pin. Especially the ceramic capacitor should be connected as close as possible to the pin. All digital signals, especially clocks, should be kept away from the VREFH1 and VREFL1 pins in order to avoid unwanted noise coupling into the AK5552. 3. Analog Inputs The Analog input signal is differentially supplied into the modulator via the AINn+ and the AINn- pins (n= 1-2). The input voltage is the difference between the ALINn+ and ALINn- pins (n= 1-2). The full scale signal on each pin is nominally 2.8 V (typ). A voltage from AVSS to AVDD can be input to the AK5552. The output code format is two's complement. The internal HPF removes DC offset (including DC offset by the ADC itself). The AK5552 requires a +5 V analog supply voltage. Any voltage which exceeds the upper limit of AVDD+0.3 V and lower limit of AVSS0.3 V and any current beyond 10 mA for the analog input pins should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution especially when using 15 V for other analog circuits in the system. 015099871-E-01 2017/11 - 64 - [AK5552] 4. External Analog Circuit Examples Figure 73 shows an input buffer circuit example 1. (1st order HPF; fc= 0.70 Hz, 2nd order LPF; fc= 351 kHz, gain= 14.5 dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 14.9 Vpp (AK5552: 2.8 Vpp Typ.). When using this circuit, analog characteristics at fs= 48 kHz is DR= 115 dB, S/(N+D)= 106 dB. The S/(N+D) characteristics of the AK5552 varies depending on DC bias current of the input signal. Set the DC bias voltage in a range from 0.49 x AVDD to 0.51 x AVDD for a better characteristic. * Film capacitors are recommended for the components shown as 15nF and 1 nF in the figure below. 4.7k 4.7k Analog In 620 JP1 VP+ Vin- 68 + 14.9Vpp Bias VP- 1n * 3.3k 10 + 2.8Vpp AK5552 AINn+ 100p NJM5534 NJM5534 XLR 15n * VA+ 620 10k Bias 10k JP2 68 - + 10 1n * 3.3k Vin+ 0.1 10 + NJM5534 Bias VA=+5V VP=15V AK5552 AINn100p 2.8Vpp Figure 73. Input Buffer Example1 fin 1Hz 10Hz Frequency Response 1.77dB 0.02dB Table 23. Frequency Response of HPF fin 20kHz 40kHz 80kHz Frequency Response 0.00dB 0.00dB 0.00dB Table 24. Frequency Response of LPF 015099871-E-01 6.144MHz 49.68dB 2017/11 - 65 - [AK5552] 14. Package Outline Dimensions 48-pin QFN (Unit mm) 7.000.10 0.400.10 B A C0 .60 0.23 +0.07 -0.05 0.10 M AX 5.1 6.750.10 7.000.10 6.750.10 0.50 M AB 5.1 0.85 +0.15 -0.05 +0.03 C 0.08 0.02 -0.02 0.20 C Material & Lead Finish Package molding compound: Epoxy resin Lead frame material: Cu Terminal surface treatment: Solder (Pb free) plate Marking AKM AK5552VN XXXXXXX 1 1) 2) 3) 4) Pin #1 indication Date Code: XXXXXXX (7 digits) Marketing Code: AK5552VN AKM Logo 015099871-E-01 2017/11 - 66 - [AK5552] 15. Ordering Guide 40 - 105 C 48-pin QFN Evaluation Board for AK5552 AK5552VN AKD5552 16. Revision History Date (Y/M/D) 16/03/10 17/11/16 Revision 00 01 Reason First Edition Specification change Page Contents 47 Table 12. PW2-0 pins setting. Change "LLH" and "LHL" setting to Not Available. 015099871-E-01 2017/11 - 67 - [AK5552] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. 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