DS05-20907-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
32 M (4M ×
××
× 8/2M ×
××
× 16) BIT
MirrorFlashTM*
MBM29PL32TM/BM 90/10
■DESCRIPTION
The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M b ytes b y 8 bits or 2M w ords b y
16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be
programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or
erase operations. The devices can also be reprogrammed in standard EPROM programmers.
(Continued)
■PRODUCT LINE UP
■PACKAGES
* : MirrorFlashTM is a trademark of Fujitsu Limited.
Notes : • Programming in byte mode ( × 8) is prohibited.
• Programming to the address that already contains data is prohibited.
(It is mandatory to erase data prior to overprogram on the same address.)
Part No. MBM29PL32TM/BM
90 10
VCC 3.0 V to 3.6 V 3.0 V to 3.6 V
Max Address Access Time 90 ns 100 ns
Max CE Access Time 90 ns 100 ns
Max Page Read Access Time 25 ns 30 ns
48-pin plastic TSOP (1) 48-ball plastic FBGA
(FPT-48P-M19) (BGA-48P-M20)
MBM29PL32TM/BM90/10
2
(Continued)
The standard MBM29PL32TM/BM off ers access times of 90 ns , allowing oper ation of high-speed microproces-
sors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable
(WE), and output enable (OE) controls.
The MBM29PL32TM/BM supports command set compatible with JEDEC single-pow er-supply EEPROMS stan-
dard. Commands are written into the command register. The register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Wr ite cycles also inter nally latch addresses and
data needed for the programming and erase operations. Reading data out of the devices is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL32TM/BM is programmed by executing the program command sequence. This will invoke the
Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths
and ver ifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will
inv oke the Embedded Er ase AlgorithmTM which is an internal algorithm that automatically preprograms the arra y
if it is not already programmed before executing the erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.
The de vice features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices
internally return to the read mode.
Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiv eness. The devices electrically erase all bits within a sector sim ulta-
neously via hot-hole assisted erase. The words are programmed one word at a time using the EPR OM program-
ming mechanism of hot electron injection.
MBM29PL32TM/BM90/10
3
■FEATURES
•0.23 µ
µµ
µm Process Tec h nology
•Single 3.0 V read, program and erase
Minimizes system level power requirements
•Industry-standard pinouts
48-pin TSOP (1) (Package suffix: TN - Normal Bend Type)
48-ball FBGA(Package suffix: PBT)
• Minimum 100,000 program/erase cycles
•High performance Page mode
Fast 8 bytes / 4 words access capability
•Sector erase architecture
Eight 8K byte and sixty-three 64K byte sectors
Eight 4K word and sixty-three 32K word sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase
•Boot Code Sector Architecture
T = Top sector
B = Bottom sector
•HiddenROM
256 bytes / 128 words of HiddenROM, accessible through a “HiddenROM Entry” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP/ACC input pin
At VIL, allows protection of outermost two 8K bytes / 4K w ords sectors , regardless of sector protection/unpro-
tection status
At VACC, increases program performance
•Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
•Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
•Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
•Program Suspend/Resume
Suspends the program operation to allow a read in another address
•Low VCC write inhibit ≤
≤≤
≤ 2.5 V
•Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
•Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin
This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29PL32TM/BM90/10
4
■PIN ASSIGNMENTS
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
N.C.
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin Plastic TSOP(1)
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
(Marking Side)
(FPT-48P-M19)
(Top View)
A6 B6 C6 D6 E6 F6
BYTE G6 H6
A5 B5 C5 D5 E5 F5 G5 H5
A9A8A10 A11 DQ7DQ14 DQ13 DQ6
A4 B4 C4 D4 E4 F4 G4 H4
WE RESET N.C. A19 DQ5DQ12 VCC DQ4
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY WP/
ACC A18 A20 DQ2DQ10 DQ11 DQ3
A2 B2 C2 D2 E2 F2 G2 H2
A7A17 A6A5DQ0DQ8DQ9DQ1
A1 B1 C1 D1 E1 F1 G1 H1
A3A4A2A1A0CE OE VSS
A13 A12 A14 A15 A16 DQ15/
A-1 VSS
48-ball plastic FBGA
(Top Vie w)
Marking Side
(BGA-48P-M20)
MBM29PL32TM/BM90/10
5
■PIN DESCRIPTIONS
MBM29PL32TM/BM Pin Configuration
Pin Function
A20 to A0, A-1 Address Inputs
DQ15 to DQ0Data Inputs/Outputs
CE Chip Enable
OE Output Enable
WE Write Enable
WP/ACC Hardware Write Protection/Program Acceleration
RESET Hardware Reset Pin/Temporary Sector Group Unprotection
BYTE Select Byte or Word mode
RY/BY Ready/Busy Output
VCC Device Power Supply
VSS Device Ground
N.C. No Internal Connection
MBM29PL32TM/BM90/10
6
■BLOCK DIAGRAM
■LOGIC SYMBOL
VSS
VCC
WE
CE
A1, A0
OE
Erase Voltage
Generator
DQ15 to DQ0
State
Control
Command
Register Program Voltage
Generator
Address
Latch X-Decoder
Y-Decoder
Cell Matrix
Y-Gating
Chip Enable
Output Enable
Logic Data Latch
STB
STB
RESET
WP/ACC
Timer for
Program/Erase
Input/Output
Buffers
A20 to A2
BYTE
(A-1)
21 A20 to A0
WE
OE
CE
DQ 15 to DQ 0
WP/ACC
RESET
16 or 8
BYTE RY/BY
A-1
MBM29PL32TM/BM90/10
7
■DEVICE BUS OPERATION
MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for
voltage levels.
Hi-Z = High-Z, VID = 11.5 V to 12.5 V
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See “Sector Group Protection Verify Autoselect Codes”.
*2 : Refer to “Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION.
*3 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*4 : If WP/ACC = VIL, the outermost two sectors remain protected.
If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the method
specified in “Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION.
Operation CE OE WE A0A1A2A3A6A9DQ0 to
DQ15 RESET WP/
ACC
Standby H X X X X X X X X Hi-Z H X
Autoselect Manufacture Code*1LLHLLLLLV
ID Code H X
Autoselect Device Code*1LLHHLLLLV
ID Code H X
Read L L H A0A1A2A3A6A9DOUT HX
Output Disable L H H X X X X X X Hi-Z H X
Write (Program/Erase) L H L A0A1A2A3A6A9*3 H *4
Enable Sector Group Protection*2LHLLHLLLX *3 V
ID H
Temporary Sector Group
Unprotection XXXXXXXXX *3 V
ID H
Reset (Hardware) X X X X X X X X X Hi-Z L X
Sector Write Protection X X X X X X X X X X H L
MBM29PL32TM/BM90/10
8
MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for
voltage levels.
Hi-Z = High-Z, VID = 11.5 V to 12.5 V
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See “MBM29PL32TM/BM Standard Command Definitions”.
*2 : Refer to “Sector Group Protection”.
*3 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*4 : If WP/ACC = VIL, the outermost two sectors remain protected.
If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the method
specified in “Sector Group Protection” in page 23.
Operation CE OE WE DQ15/
A-1 A0A1A2A3A6A9DQ0 to
DQ7RESET WP/
ACC
Standby H X X X X X X X X X Hi-Z H X
Autoselect Manufacture Code*1LLH L LLLLLV
ID Code H X
Autoselect Device Code*1LLH L HLLLLV
ID Code H X
Read L L H A-1 A0A1A2A3A6A9DOUT HX
Output Disable L H H X X X X X X X Hi-Z H X
Write (Erase) L H L A-1 A0A1A2A3A6A9*3 H *4
Enable Sector Group Protection*2LHL L LHLLLX *3 V
ID H
Temporary Sector Group
Unprotection XXXXXXXXXX*3 V
ID H
Reset (Hardware) X X X X X X X X X X Hi-Z L X
Sector Write Protection X X X X X X X X X X X H L
MBM29PL32TM/BM90/10
9
MBM29PL32TM/BM Standard Command Definitions*1
(Continued)
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle Second Bus
Write Cycle Third Bus
Write Cycle Fourth Bus
Read/Write
Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset*2Word/
Byte 1XXXhF0h— — ——— — ————
Reset*2Word 3555h AAh 2AAh 55h 555h F0h RA*13 RD*13 ————
Byte AAAh 555h AAAh
Autoselect Word 3555h AAh 2AAh 55h 555h 90h 00h*13 04h*13 ————
Byte AAAh 555h AAAh
Program Word 4555h AAh 2AAh 55h 555h A0h PA PD — — — —
Chip Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
Byte AAAh 555h AAAh AAAh 555h AAAh
Sector Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Byte AAAh 555h AAAh AAAh 555h
Program/Erase Suspend*31XXXhB0h— — ——— — ————
Program/Erase Resume*31XXXh30h— — ——— — ————
Set to Fast Mode*4Word 3555h AAh 2AAh 55h 555h 20h— — ————
Byte AAAh 555h AAAh
Fast Program*4Word 2XXXh A0h PA PD — — — — — — — —
Reset from Fast
Mode*5Word/
Byte 2XXXh 90h XXXh 00h*12 ——— — ————
Write to Buffer Word 20 555h AAh 2AAh 55h SA 25h SA 0Fh PA PD WBL PD
Byte AAAh 555h
Program Buffer to Flash
(Confirm) 1SA29h— — ——— — ————
Write to Buffer Abort
Reset*6
Word 3555h AAh 2AAh 55h 555h F0h— — ————
Byte AAAh 555h AAAh
Extended Sector
Group Protection*7,*8
Word 4XXXh 60h SGA 60h SGA 40h SGA
*13 SD*13 ————
Byte
Query*9Word 155h 98h— — ——— — ————
Byte AAh
HiddenROM
Entry*10
Word 3555h AAh 2AAh 55h 555h 88h— — ————
Byte AAAh 555h AAAh
HiddenROM
Program *10,*11
Word 4555h AAh 2AAh 55h 555h A0hPAPD————
Byte AAAh 555h AAAh
HiddenROM Exit*11 Word 4555h AAh 2AAh 55h 555h 90h XXXh 00h — — — —
Byte AAAh 555h AAAh
MBM29PL32TM/BM90/10
10
(Continued)
Legend : Address bits A20 to A11 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA) and Sector Group Address (SGA).
Bus operations are defined in “MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)”
and “MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)”.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the write pulse.
SA = Address of the sector to be programmed / erased. The combination of A20, A19, A18, A17, A16, A15,
A14, A13 and A12 will uniquely select any sector. See “Sector Address Table (MBM29PL32TM)”
and “Sector Address Table (MBM29PL32BM)”.
SGA = Sector Group Address to be protected. See “Sector Group Address Table (MBM29PL32TM)”
and “Sector Group Address Table (MBM29PL32BM)”.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write plus.
WBL = Write Buffer Location
HRA = Address of the HiddenROM area ;
MBM29PL32TM (Top Boot Type)Word Mode : 1FFF7Fh to 1FFFFFh
Byte Mode : 3FFEFFh to 3FFFFFh
MBM29PL32BM (Bottom Boot Type)Word Mode : 000000h to 00007Fh
Byte Mode : 000000h to 0000FFh
*1 : The command combinations not described in “MBM29PL32TM/BM Standard Command Definitions” are
illegal.
*2 : Both of these reset commands are equivalent except for "Write to Buffer Abort" reset.
*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.
*4 : The Set to Fast Mode command is required prior to the Fast Program command.
*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast mode.
*6 : Reset to the read mode. The Write to Buffer Abort Reset command is required after the Write to Buffer
operation was aborted.
*7 : This command is valid while RESET = VID.
*8 : Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0
*9 : The valid address are A6 to A0.
*10 : The HiddenROM Entry command is required prior to the HiddenROM programming.
*11 : This command is valid during HiddenROM mode.
*12 : The data “F0h” is also acceptable.
*13 : Indicates read cycle.
MBM29PL32TM/BM90/10
11
Sector Group Protection Verify Autoselect Codes
*1 : A-1 is for Byte mode.
*2 : At Word mode, a read cycle at address 01h ( at Byte mode, 02h ) outputs device code. When 227Eh
( at Byte mode, 7Eh ) is output, it indicates that reading two additional codes, called Extended Device
Codes, will be required. Therefore the system may continue reading out these Extended Device
Codes at the address of 0Eh ( at Byte mode, 1Ch ), as well as at 0Fh ( at Byte mode, 1Eh ).
*3 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*4 : Toggle CE, provided SGA = fix and WE = fix.
The data in the first cycle is invalid. The data in the second one is valid.
Type A20 to A12 A6A3A2A1A0A-1*1Code (HEX)
Manufacturer’s Code X VIL VIL VIL VIL VIL VIL 04h
Device Code Word XV
IL VIL VIL VIL VIH X 227Eh
Byte VIL 7Eh
Extended
Device
Code*2
MBM29PL32TM
Word XV
IL VIH VIH VIH VIL X 221Ah
Byte VIL 1Ah
Word XV
IL VIH VIH VIH VIH X 2201h
Byte VIL 01h
MBM29PL32BM
Word XV
IL VIH VIH VIH VIL X 221Ah
Byte VIL 1Ah
Word XV
IL VIH VIH VIH VIH X 2200h
Byte VIL 00h
Sector Group Protection*4Sector Group
Addresses VIL VIL VIL VIH VIL VIL *3
MBM29PL32TM/BM90/10
12
Sector Address Table (MBM29PL32TM)
(Continued)
Sector Sector Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA0 000000XXX 64/32 000000h to 00FFFFh 000000h to 007FFFh
SA1 000001XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh
SA2 000010XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh
SA3 000011XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh
SA4 000100XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh
SA5 000101XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh
SA6 000110XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh
SA7 000111XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh
SA8 001000XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh
SA9 001001XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh
SA10001010XXX 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh
SA11001011XXX 64/32 0B0000h to 0BFFFFh058000h to 05FFFFh
SA12001100XXX 64/32 0C0000h to 0CFFFFh060000h to 067FFFh
SA13001101XXX 64/32 0D0000h to 0DFFFFh068000h to 06FFFFh
SA14001110XXX 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh
SA15001111XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh
SA16010000XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh
SA17010001XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh
SA18010010XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh
SA19010011XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh
SA20010100XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh
SA21010101XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh
SA22010110XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh
SA23010111XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh
SA24011000XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25011001XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26011010XXX 64/32 1A0000h to 1AFFFFh0D0000h to 0D7FFFh
SA27011011XXX 64/32 1B0000h to 1BFFFFh0D8000h to 0DFFFFh
SA28011100XXX 64/32 1C0000h to 1CFFFFh0E0000h to 0E7FFFh
SA29011101XXX 64/32 1D0000h to 1DFFFFh0E8000h to 0EFFFFh
SA30011110XXX 64/32 1E0000h to 1EFFFFh0F0000h to 0F7FFFh
SA31011111XXX 64/32 1F0000h to 1FFFFFh0F8000h to 0FFFFFh
MBM29PL32TM/BM90/10
13
(Continued)
Sector Sector Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA32 1 0 0 0 0 0 X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh
SA33 1 0 0 0 0 1 X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh
SA34 1 0 0 0 1 0 X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh
SA35 1 0 0 0 1 1 X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh
SA36 1 0 0 1 0 0 X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh
SA37 1 0 0 1 0 1 X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh
SA38 1 0 0 1 1 0 X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh
SA39 1 0 0 1 1 1 X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh
SA40 1 0 1 0 0 0 X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh
SA41 1 0 1 0 0 1 X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh
SA42 1 0 1 0 1 0 X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh
SA43 1 0 1 0 1 1 X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh
SA44 1 0 1 1 0 0 X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh
SA45 1 0 1 1 0 1 X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh
SA46 1 0 1 1 1 0 X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh
SA47 1 0 1 1 1 1 X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh
SA48 1 1 0 0 0 0 X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh
SA49 1 1 0 0 0 1 X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh
SA50 1 1 0 0 1 0 X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh
SA51 1 1 0 0 1 1 X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh
SA52 1 1 0 1 0 0 X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh
SA53 1 1 0 1 0 1 X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh
SA54 1 1 0 1 1 0 X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh
SA55 1 1 0 1 1 1 X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh
SA56 1 1 1 0 0 0 X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh
SA57 1 1 1 0 0 1 X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh
SA58 1 1 1 0 1 0 X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA59 1 1 1 0 1 1 X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA60 1 1 1 1 0 0 X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA61 1 1 1 1 0 1 X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA62 1 1 1 1 1 0 X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA63 1 1 1 1 1 1 0 0 0 8/4 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
SA64 1 1 1 1 1 1 0 0 1 8/4 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
MBM29PL32TM/BM90/10
14
(Continued)
Note : The address range is A20 to A-1 if in Byte mode (BYTE = VIL) .
The address range is A20 to A0 if in Word mode (BYTE = VIH) .
Sector Sector Address Sector
Size
(Kb ytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA65111111010 8/4 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
SA66111111011 8/4 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
SA67111111100 8/4 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
SA68111111101 8/4 3FA000h to 3FBFFFh1FD000h to 1FDFFFh
SA69111111110 8/4 3FC000h to 3FDFFFh1FE000h to 1FEFFFh
SA70111111111 8/4 3FE000h to 3FFFFFh1FF000h to 1FFFFFh
MBM29PL32TM/BM90/10
15
Sector Address Table (MBM29PL32BM)
(Continued)
Sector Sector Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA70 1 1 1 1 1 1 X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
SA69 1 1 1 1 1 0 X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA68 1 1 1 1 0 1 X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA67 1 1 1 1 0 0 X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA66 1 1 1 0 1 1 X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA65 1 1 1 0 1 0 X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA64 1 1 1 0 0 1 X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh
SA63 1 1 1 0 0 0 X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh
SA62 1 1 0 1 1 1 X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh
SA61 1 1 0 1 1 0 X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh
SA60 1 1 0 1 0 1 X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh
SA59 1 1 0 1 0 0 X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh
SA58 1 1 0 0 1 1 X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh
SA57 1 1 0 0 1 0 X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh
SA56 1 1 0 0 0 1 X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh
SA55 1 1 0 0 0 0 X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh
SA54 1 0 1 1 1 1 X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh
SA53 1 0 1 1 1 0 X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh
SA52 1 0 1 1 0 1 X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh
SA51 1 0 1 1 0 0 X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh
SA50 1 0 1 0 1 1 X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh
SA49 1 0 1 0 1 0 X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh
SA48 1 0 1 0 0 1 X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh
SA47 1 0 1 0 0 0 X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh
SA46 1 0 0 1 1 1 X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh
SA45 1 0 0 1 1 0 X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh
SA44 1 0 0 1 0 1 X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh
SA43 1 0 0 1 0 0 X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh
SA42 1 0 0 0 1 1 X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh
SA41 1 0 0 0 1 0 X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh
SA40 1 0 0 0 0 1 X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh
SA39 1 0 0 0 0 0 X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh
SA38 0 1 1 1 1 1 X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MBM29PL32TM/BM90/10
16
(Continued)
Sector Sector Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA37011110XXX 64/32 1E0000h to 1EFFFFh0F0000h to 0F7FFFh
SA36011101XXX 64/32 1D0000h to 1DFFFFh0E8000h to 0EFFFFh
SA35011100XXX 64/32 1C0000h to 1CFFFFh0E0000h to 0E7FFFh
SA34011011XXX 64/32 1B0000h to 1BFFFFh0D8000h to 0DFFFFh
SA33011010XXX 64/32 1A0000h to 1AFFFFh0D0000h to 0D7FFFh
SA32011001XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh
SA31011000XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh
SA30010111XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh
SA29010110XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh
SA28010101XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh
SA27010100XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh
SA26010011XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh
SA25010010XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh
SA24010001XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh
SA23010000XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh
SA22001111XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh
SA21001110XXX 64/32 0E0000h to 0EFFFFh070000h to 077FFFh
SA20001101XXX 64/32 0D0000h to 0DFFFFh068000h to 06FFFFh
SA19001100XXX 64/32 0C0000h to 0CFFFFh060000h to 067FFFh
SA18001011XXX 64/32 0B0000h to 0BFFFFh058000h to 05FFFFh
SA17001010XXX 64/32 0A0000h to 0AFFFFh050000h to 057FFFh
SA16001001XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh
SA15001000XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh
SA14000111XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh
SA13000110XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh
SA12000101XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh
SA11000100XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh
SA10000011XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh
SA9 000010XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh
SA8 000001XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh
SA7 000000111 8/4 00E000h to 00FFFFh 007000h to 007FFFh
SA6 000000110 8/4 00C000h to 00DFFFh 006000h to 006FFFh
SA5 000000101 8/4 00A000h to 00BFFFh 005000h to 005FFFh
MBM29PL32TM/BM90/10
17
(Continued)
Note : The address range is A20 to A-1 if in Byte mode (BYTE = VIL) .
The address range is A20 to A0 if in Word mode (BYTE = VIH) .
Sector Sector Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA4 000000100 8/4 008000h to 009FFFh 004000h to 004FFFh
SA3 000000011 8/4 006000h to 007FFFh 003000h to 003FFFh
SA2 000000010 8/4 004000h to 005FFFh 002000h to 002FFFh
SA1 000000001 8/4 002000h to 003FFFh 001000h to 001FFFh
SA0 000000000 8/4 000000h to 001FFFh 000000h to 000FFFh
MBM29PL32TM/BM90/10
18
Sector Group Address Table (MBM29PL32TM)
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 0 0 0 0 X X X X X SA0 to SA3
SGA1 0 0 0 1 X X X X X SA4 to SA7
SGA2 0010XXXXX SA8 to SA11
SGA3 0 0 1 1 X X X X X SA12 to SA15
SGA4 0 1 0 0 X X X X X SA16 to SA19
SGA5 0 1 0 1 X X X X X SA20 to SA23
SGA6 0 1 1 0 X X X X X SA24 to SA27
SGA7 0 1 1 1 X X X X X SA28 to SA31
SGA8 1 0 0 0 X X X X X SA32 to SA35
SGA9 1 0 0 1 X X X X X SA36 to SA39
SGA10 1 0 1 0 X X X X X SA40 to SA43
SGA11 1 0 1 1 X X X X X SA44 to SA47
SGA12 1 1 0 0 X X X X X SA48 to SA51
SGA13 1 1 0 1 X X X X X SA52 to SA55
SGA14 1 1 1 0 X X X X X SA56 to SA59
SGA15 1 1 1 1
00
X X X SA60 to SA6201
10
SGA16 1 1 1 1 1 1 0 0 0 SA63
SGA17 1 1 1 1 1 1 0 0 1 SA64
SGA18 1 1 1 1 1 1 0 1 0 SA65
SGA19 1 1 1 1 1 1 0 1 1 SA66
SGA20 1 1 1 1 1 1 1 0 0 SA67
SGA21 1 1 1 1 1 1 1 0 1 SA68
SGA22 1 1 1 1 1 1 1 1 0 SA69
SGA23 1 1 1 1 1 1 1 1 1 SA70
MBM29PL32TM/BM90/10
19
Sector Group Address Table (MBM29PL32BM)
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 000000000 SA0
SGA1 000000001 SA1
SGA2 000000010 SA2
SGA3 000000011 SA3
SGA4 000000100 SA4
SGA5 000000101 SA5
SGA6 000000110 SA6
SGA7 000000111 SA7
SGA8 0000
01
X X X SA8 to SA1010
11
SGA9 0 0 0 1 X X X X X SA11 to SA14
SGA10 0 0 1 0 X X X X X SA15 to SA18
SGA11 0 0 1 1 X X X X X SA19 to SA22
SGA12 0 1 0 0 X X X X X SA23 to SA26
SGA13 0 1 0 1 X X X X X SA27 to SA30
SGA14 0 1 1 0 X X X X X SA31 to SA34
SGA15 0 1 1 1 X X X X X SA35 to SA38
SGA16 1 0 0 0 X X X X X SA39 to SA42
SGA17 1 0 0 1 X X X X X SA43 to SA46
SGA18 1 0 1 0 X X X X X SA47 to SA50
SGA19 1 0 1 1 X X X X X SA51 to SA54
SGA20 1 1 0 0 X X X X X SA55 to SA58
SGA21 1 1 0 1 X X X X X SA59 to SA62
SGA22 1 1 1 0 X X X X X SA63 to SA66
SGA23 1 1 1 1 X X X X X SA67 to SA70
MBM29PL32TM/BM90/10
20
Common Flash Memory Interface Code
(Continued)
A6 to A0DQ15 to DQ0Description
10h
11h
12h
0051h
0052h
0059h Query-unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
(02h = Fujitsu standard)
15h
16h 0040h
0000h Address for Primary Extended Table
17h
18h 0000h
0000h Alternate OEM Command Set
(00h = not applicable)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table
(00h = not applicable)
1Bh 0027h VCC Min (write/erase)
DQ7 to DQ4: 1 V/bit,
DQ3 to DQ0: 100 mV/bit
1Ch 0036h VCC Max (write/erase)
DQ7 to DQ4: 1 V/bit,
DQ3 to DQ0: 100 mV/bit
1Dh 0000h VPP Min voltage (00h = no Vpp pin)
1Eh 0000h VPP Max voltage (00h =no Vpp pin)
1Fh 0007h Typical timeout per single write 2N µs
20h 0007h Typical timeout for Min size buffer write 2N µs
21h 000Ah Typical timeout per individual sector erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms
23h 0001h Max timeout for write 2N times typical
24h 0005h Max timeout for buffer write 2N times typical
25h 0004h Max timeout per individual sector erase 2N times typical
26h 0000h Max timeout for full chip erase 2N times typical
27h 0016h Device Size = 2N byte
28h
29h 0002h
0000h Flash Device Interface description
02h : × 8/ × 16
2Ah
2Bh 0005h
0000h Max number of byte in
multi-byte write = 2N
2Ch 0002h Number of Erase Block Regions within device (02h = Boot)
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
MBM29PL32TM/BM90/10
21
(Continued)
A6 to A0DQ15 to DQ0Description
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
40h
41h
42h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII
45h 0008h Address Sensitive Unlock
Required
46h 0002h Erase Suspend
(02h = To Read & Write)
47h 0004h Number of sectors in per group
48h 0001h Sector Temporary Unprotection
(01h = Supported)
49h 0004h Sector Protection Algorithm
4Ah 0000h Dual Operation
(00h = Not Supported)
4Bh 0000h Burst Mode Type
(00h = Not Supported)
4Ch 0001h Page Mode Type
(01h = 4-Word Page Supported)
4Dh 00B5h VACC (Acceleration) Supply Minimum
DQ7 to DQ4: 1 V/bit,
DQ3 to DQ0: 100 mV/bit
4Eh 00C5h VACC (Acceleration) Supply Maximum
DQ7 to DQ4: 1 V/bit,
DQ3 to DQ0: 100 mV/bit
4Fh 00XXh CFI Write Protect
(02h = Bottom Boot Device with WP Protect
03h = Top Boot Device with WP Protect)
50h 01h Program Suspend
(01h = Supported)
MBM29PL32TM/BM90/10
22
■FUNCTIONAL DESCRIPTION
Standby Mode
There are two w ays to implement the standb y mode on the de vice, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ±0.3 V. Under
this condition the current consumed is less than 5 µA Max. During Embedded Algor ithm operation, VCC active
current (ICC2) is required e ven when CE = “H”. The de vice can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE =
“H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,
the device requires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state, regardless of OE input.
Automatic Sleep Mode
Automatic sleep mode work s to restrain power consumption during read-out of device data. It can be useful in
applications such as handy terminal, which requires low power consumption.
To activate this mode, the device automatically switch themselves to low power mode when the device addresses
remain stable after tACC + 30 ns from data v alid. It is not necessary to control CE, WE, and OE in this mode. The
current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device read-out the data for changed addresses.
Autoselect
The A utoselect mode allo ws reading out of a binary code and identifies its manuf acturer and type.It is intended
f or use by progr amming equipment for the purpose of automatically matching the device to be prog rammed with
its corresponding progra mming algorithm.
To activate this mode, the programming equipment must force VID on address pin A9. Two identifier bytes may
then be sequenced from the de vices outputs b y toggling A0. All addresses can be either High or Low except A6,
A3,A2,A1 and A0. See “MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)” and
“MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE BUS OPERATION.
The manuf acturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in “MBM29PL32TM/BM Standard Command Definitions” in ■DEVICE BUS OPERATION.Refer to
Autoselect Command section.
In W ord mode, a read cycle from address 00h returns the manuf acturer’s code (Fujitsu = 04h) . A read cycle at
address 01h outputs de vice code. When 227Eh is output, it indicates that two additional codes, called Extended
Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes
at addresses of 0Eh and 0Fh. Notice that the abov e applies to Word mode . The addresses and codes differ from
those of Byte mode. Refer to “Sector Group Protection V erify Autoselect Codes” in ■DEVICE BUS OPERATION.
Read Mode
The device has two control functions required to obtain data at the outputs. CE is the power control and used
for a device selection. OE is the output control and used to gate data to the output pins.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses hav e been stable f or at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, input hardware reset or to change CE pin from “H” or “L”.
MBM29PL32TM/BM90/10
23
Page Mode Read
The de vice is capab le of fast read access f or r andom locations within limited address location called Page. The
Page size of the device is 8 bytes / 4 words, within the appropriate Page being selected by the higher address
bits A20 to A2 and the address bits A1 to A0 in W ord mode ( A1 to A-1 in Byte mode) determining the specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.
The initial page access is equal to the random access (tACC) and subsequent P age read access (as long as the
locations specified by the microprocessor fall within that Page) is equivalent to the page address access time
(tPACC). Here again, CE selects the device and OE is the output control and should be used to gate data to the
output pins if the de vice is selected. Fast P age mode , accesses are obtained b y k eeping A20 to A2 constant and
changing A1 and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within that Page.
Output Disable
With the OE input at logic high le v el (VIH), output from the devices are disabled. This may cause the output pins
to be in a high impedance state.
Write
Device erasure and programming are accomplished via the command register . The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the device function.
The command register itself does not occup y an y addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
f alling edge of WE or CE, whichev er starts later; while data is latched on the rising edge of WE or CE, whichev er
starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardw are sector group protection. This feature will disable both program and erase oper a-
tions in any combination of thirty two sector groups of memory.See “Sector Group Address Table
(MBM29PL32TM)” and “Sector Group Address Table (MBM29PL32BM)” in ■DEVICE BUS OPERATION. The
user‘s side can use the sector group protection using programming equipment. The device is shipped with all
sector groups that are unprotected.
To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and
A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector g roup addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should
be set to the sector to be protected. “Sector Address Table (MBM29PL32TM)” and “Sector Address Table
(MBM29PL32BM)” in ■DEVICE BUS OPERATION defines the sector address f or each of the se v enty-one (71)
individual sectors, and “Sector Group Address Table (MBM29PL32TM)” and “Sector Group Address Table
(MBM29PL32BM)” in ■DEVICE BUS OPERATION defines the sector group address f or each of the twenty-f our
(24) individual group sectors . Programming of the protection circuitry begins on the f alling edge of the WE pulse
and is ter minated with the rising edge of the same. Sector group addresses must be held constant during the
WE pulse. See “Sector Group Protection Timing Diag r am” in ■SWITCHING WAVEFORMS and “Sector Group
Protection Algorithm” in ■FLOW CHART for sector group protection timing diagram and algorithm.
To verify progr amming of the protection circuitry, the programming equipment m ust force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,
and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a
protected sector. Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order
addresses, except for A0, A1, A2, A3, and A6 can be either High or Low . Address locations with A1 = VIL are reserved
for Autoselect manufacturer and device codes. A-1 requires applying to VIL on Byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
P erf orming a read operation at the address location XX02h, where the higher order addresses(A20, A19, A18, A17,
A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected
sector group. See “Sector Group Protection Ver ify Autoselect Codes” in ■DEVICE BUS OPERATION for Au-
toselect codes.
MBM29PL32TM/BM90/10
24
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the devices in order to change
data. The Sector Group Unprotection mode is activa ted by setting the RESET pin to high voltage (VID). During
this mode, for merly protected sector groups can be programmed or erased by selecting the sector group ad-
dresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be
protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in ■SWITCHING WAVE-
FORMS and “Temporary Sector Group Unprotection Algorithm” in ■FLOW CHART.
Hardware Reset
The devices may be reset by dr iving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement
and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. An y oper ation
in the process of being e xecuted will be terminated and the internal state machine will be reset to the read mode
“tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an
additional “tRH” before it will allow read access. When the RESET pin is low, the devices will be in the standby
mode f or the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during
a program or erase operation, the data at that particular location will be corrupted.
Write Protect (WP)
The Write Protection function provides a hardware method of protecting certain outermost 8K bytes / 4K w ords
sectors without using VID. This function is one of two provided by the WP/ACC pin.
If the system asserts VIL on the WP/ACC pin, the de vice disab les prog ram and erase functions in the outermost
8K bytes / 4K words sectors independently of whether this sector was protected or unprotected using the method
described in “Sector Group Protection" above.
If the system asserts VIH on the WP/ACC pin, the device rev erts of whether the outermost 8K bytes / 4K words
sectors were last set to be protected to the unprotected status . Sector protection or unprotection for this sector
depends on whether this was last protected or unprotected using the method described in “Sector protection/
unprotection”.
Accelerated Program Operation
The device offers accelerated program operation which enables programming in high speed. If the system asserts
VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program
operation will reduce to about 85%. This function is primarily intended to allow high speed programing, so caution
is needed as the sector group becomes temporarily unprotected.
The system would use a fast program command sequence when programming during acceleration mode. Set
command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode , the device is automatically set to f ast mode . Therefore , the present sequence could be used
for programming and detection of completion during acceleration mode.
Removing VACC from the WP/A CC pin returns the device to normal operation. Do not remove VACC from the WP/
ACC pin while programming. See “Accelerated Program Timing Diagram” in ■SWITCHING WAVEFORM.
MBM29PL32TM/BM90/10
25
■COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
“MBM29PL32TM/BM Standard Command Definitions” in ■DEVICE BUS OPERATION shows the v alid register
command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only
while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Progra m Resume (30h)
commands are valid only while the Program operation is in progress.Moreover Reset commands are functionally
equiv alent, resetting the device to the read mode . Please note that commands must be asserted to DQ7 to DQ0
and DQ15 to DQ8 bits are ignored.
Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation
is initiated by writing the Reset command sequence into the command register. The devices remain enab led f or
reads until the command register contents are altered.
The devices will automatically be in the reset state after power-up. In this case, a command sequence is not
required in order to read data.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-
grammers typically access the signature codes by raising A9 to a high voltage. However applying high voltage
onto the address lines is not generally desired system design practice.
The de vice contains an A utoselect command oper ation to supplement traditional PR OM prog ramming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The A utoselect command sequence is initiated first by writing two unloc k cycles. This is f ollo wed b y a third write
cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be
read from the address, and an actual data of memory cell can be read from the another address.
Following the command write, a read cycle from address 00h retur n s the manufa ctures’s code (Fujitsu = 04h).
A read cycle at address 01h outputs de vice code . When 227Eh is output, it indicates that tw o additional codes ,
called Extended De vice Codes will be required. Therefore the system ma y continue reading out these Extended
De vice Codes at address of 0Eh as well as at 0Fh. Notice that abov e applies to W ord mode. The addresses and
codes diff er from those of Byte mode . Refer to “Sector Group Protection Verify Autoselect Codes” in ■DEVICE
BUS OPERATION.
To terminate the operation, it is necessary to write the Reset command into the register. T o execute the Autoselect
command during the operation, Reset command must be written before the Autoselect command.
Programming
The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are
two “unloc k” write cycles. These are f ollowed b y the program set-up command and data write cycles. Addresses
are latched on the f alling edge of CE or WE, whiche v er happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming.
Upon executing the Embedded Program Algor ithm command sequence, the system is not required to provide
further controls or timings. The de vice will automatically pro vide adequate internally generated program pulses
and verify the programmed cell margin.
The system can determine the status of the program oper ation b y using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.
The programming oper ation is completed when the data on DQ7 is equiv alent to data written to this bit at which
the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require
that a valid address to the devices be supplied by the system at this par ticular instance. Hence Data Polling
requires the same address which is being programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
MBM29PL32TM/BM90/10
26
Programming is allo wed in an y address sequence and across sector boundaries. Be ware that a data “0” cannot
be programmed bac k to a “1”. Attempting to do so may result in either failure condition or an apparent success
according to the data polling algorithm. But a read from Reset mode will show that the data is still “0”. Only erase
operations can convert “0”s to “1”s.
Note that attempting to program a “1” over a “0” will result in programming failure. This precaution is the same
with Fujitsu standard NOR devices. “Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Em-
bedded ProgramTM Algorithm using typical command strings and bus operations.
Pr ogram Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during Embedded Program operation imme-
diately suspends the programming.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1us and updates the status bits.After the program operation has been suspended, the system
can read data from any address . The data at prog r am-suspended address is not valid. Normal read timing and
command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program
operation. See "Write Operation Status" for more information.
When issuing program suspend command in 4 µs after issuing program command, determine the status of
program operation by reading status bit at more 4 µs after issuing program resume command.
The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows
reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the
memory. When the de vice exits the Autoselect mode , the device reverts to the Program Suspend mode, and is
ready for another valid operation. See "Autoselect Command Sequence" for more information.
The system must write the Program Resume command to exit from the Program Suspend mode and continue
the programming operation. Fur ther wr ites of the Resume command are ignored. Another Program Suspend
command can be written after the device resumes programming.
Do not read CFI code after HiddenROM Entry and Exit in program suspend mode.
Write Buffer Programming Operations
Write Buffer Programming allows the system write to series of 16 words in one programming operation. This
results in faster effective word progr amming time than the standard prog ramming algorithms. The Write Buff er
Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle selecting the Sector Address in which programming will occur. In f orth cycle contains both Sector Address
and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming
will occur.
The system then writes the starting address/data combination. This “starting address” must be the same Sector
Address used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent address
must be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever happens later
and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE
(whichever happens first) starts programming. Upon executing the Write Buff er Prog r amming Operations com-
mand sequence, the system is not required to provide further controls or timings. The device will automatically
provide adequate internally generated program pulses and verify the programmed cell margin.
DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be moni-
tored to deter mine the device status during Write Buffer Programming. In addition to these functions, it is also
possible to indicate to the host system that Write Buff er Progr amming Operations are either in progress or ha v e
been completed by RY/BY. See “Hardware Sequence Flags”.
The Data polling techniques described in “Data Polling Algorithm” in ■FLOW CHART should be used while
monitoring the last address location loaded into the wr ite buffer. In addition, it is not neccessar y to specify an
MBM29PL32TM/BM90/10
27
address in Toggle Bit techniques described in “Toggle Bit Algorithm” in ■FLOW CHART. The automatic pro-
graming operation is completed when the data on DQ7 is equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are no longer latched ( See "Hardware Sequence Flags").
The write-buffer programming operation can be suspended using the standard prog r am suspend/resume com-
mands.
Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command
at the Sector Address. Any other address/data combination will abort the Wr ite Buffer Programming operation
and the device will continue busy state.
The Write Buffer Programming Sequence can be ABORTED by doing the following :
• Different Sector Address is asserted.
• Write data other than the “Program Buff er to Flash" command after the specified number of “data load” cycles.
A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See
“MBM29PL32TM/BM Standard Command Definitions” in ■DEVICE BUS OPERATION for details on this com-
mand sequence.)
Chip Erase
Chip erase is a six bus cycle operation. It begins two “unlock” write cycles followed by writing the “set-up”
command, and two “unlock” write cycles followed by the chip erase command which invokes the Embedded
Erase algorithm.
The device does not require the user to program the de vice prior to erase. Upon e xecuting the Embedded Erase
Algorithm the devices automatically programs and verifies the entire memory for an all zero data patter n prior
to electrical erase (Preprogram function). The system is not required to provide any controls or timings during
these operations.
The system can deter mine the erase operation status by using DQ7 (Data Po lling), DQ6 (Toggle Bit I) and DQ2
(Toggle Bit II) or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever
happens first from last command sequence and completes when the data on DQ7 is “1” (See Write Operation
Status section.) at which time the device returns to read mode.
Sector Erase
Sector erase is a six b us cycle oper ation. There are two “unloc k” write cycles. These are f ollo wed b y writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command.
Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is
followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased.
The time between writes must be less than Erase Time-out time(tTOW). Otherwise that command will not be
accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to
guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out
of “tTOW” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector
Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-
out window the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete (ref er to the Write Operation Status).
Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm.
When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to
provide any controls or timings during these operations.
The system can deter mine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY.
The sector erase begins after the “tTOW” time-out from the r ising edge of CE or WE whichever happens first for
the last sector erase command pulse and completes when the data on DQ7 is “1” (see Write Operation Status
section), at which the devices retur n to the read mode. Data polling and Toggle Bit must be perfor med at an
address within any of the sectors being erased.
MBM29PL32TM/BM90/10
28
Erase Suspend/Resume
The Erase Suspend command allows the user to interr upt Sector Erase operation and then perfor m read or
programming to a sector not being erased. This command is applicable ONLY during the Sector Erase operation
within the time-out period for sector er ase. Writting the Erase Suspend command (B0h) during the Sector Erase
time-out results in immediate termination of the time-out period and suspension of the erase operation.
Writing the "Erase Resume" command (30h) resumes the erase operation.
When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum
of “tSPD” to suspend the erase operation. When the de vices enter the er ase-suspended mode, the RY/BY output
pin will be at High-Z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use the address
of the erasing sector f or reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Do not issue program command after entering erase-suspend-read mode.
Fast Mode Set/Reset
The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard
program command sequence by writing Fast Mode command into the command register. In this mode, the
required bus cycle for programming consists of two cycles instead of four bus cycles in standard program
command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any
command other than the F ast program/F ast mode reset command. To exit from this mode, write Fast Mode Reset
command into the command register. (Refer to the “Embedded Progr amTM Algorithm f or Fast Mode” in ■FLOW
CHART.) The VCC active current is required even CE = VIH during Fast Mode.
F ast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). See “Embedded
ProgramTM Algorithm for Fast Mode” in ■FLOW CHART.
Extended Sector Group Protection
In addition to nor mal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command
sequence. Unlike conventional procedures, it is not necessar y to force VID and control timing for control pins.
The only RESET pin requires VID f or sector group protection in this mode. The e xtended sector g roup protection
requires VID on RESET pin. With this condition, the operation is initiated by wr iting the set-up command (60h)
into the command register. Then the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12)
and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other
addresses pins is recommended), and write extended sector g roup protection command (60h). A sector group
is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses
pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write
a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected
sector in the read operation. If the output data is logical “0”, write the extended sector group protection command
(60h) again. To terminate the operation, set RESET pin to VIH. (Ref er to the “Extended Sector Group Protection
Timing Diagram” in ■SWITCHING WAVEFORMS and “Extended Sector Group Protection Algorithm” in ■FLOW
CHART.)
MBM29PL32TM/BM90/10
29
Query Command (CFI : Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation
handshake which allows specific vendor-specified softw are algorithms to be used f or entire families of devices .
This allows device-independent, JEDEC ID-independent, and f orward-and backw ard-compatible software sup-
port for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. Following the command
write, a read cycle from specific address retriev es de vice information. Please note that output data of upper byte
(DQ15 to DQ8) is “0”. Refer to the CFI code table. To terminate operation, it is necessary to write the Reset
command sequence into the register. (See “Common Flash Memory Interf ace Code” in ■DEVICE BUS OPER-
ATION.)
HiddenROM Mode
(1) HiddenROM Region
The HiddenROM (HiddenROM) fe ature provides a Flash memory region that the system may access through
a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number
(ESN) in the de vice with the ESN protected against modification. Once the HiddenROM region is protected, an y
further modification of that region is impossible. This ensures the security of the ESN once the product is shipped
to the field.
The HiddenROM region is 256 bytes / 128 words in length. After the system writes the HiddenROM Entry
command sequence, it may read the HiddenROM region by using device addresses A6 to A0 (A20 to A7 are all
“0”). That is, the device sends only program command that would normally be sent to the address to the
HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command
sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device
reverts to sending commands to the address.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more infor-
mation.
(2) HiddenROM Entry Command
The de vice has a HiddenROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Programming is allowed in this area until it is protected. However,
once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.
The HiddenROM area is 256 bytes / 128 words. This area is in SA0 . Therefore, write the HiddenROM entry
command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area
appears.
Sectors other than the bloc k area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM
area is possible during HiddenR OM mode. Write the HiddenROM reset command sequence to e xit the Hidden-
ROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/reset
commands during the HiddenROM mode . When y ou issue the other commands including the suspend resume
capability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each com-
mand.
MBM29PL32TM/BM90/10
30
(3) HiddenROM Program Command
To program the data to the HiddenROM area, wr ite the HiddenROM program command sequence dur ing Hid-
denROM mode. This command is the same as the usual program command, except that it needs to write the
command during HiddenROM mode . Therefore the detection of completion method is the same as in the past,
using the DQ7 data pooling, DQ6 Toggle bit or R Y/BY. You should pay attention to the address to be programmed.
If an address not in the HiddenROM area is selected, the previous data will be deleted.
During the write into the HiddenROM region, the program suspend command issuance is prohibited.
(4) HiddenROM Protect Command
There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command
(60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the
sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used
because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM
mode and does not apply high voltage to the RESET pin. Please refer to above mentioned “Extended Sector
Group Protection” for details of sector group protect setting.
The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area
and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the wr ite pulse dur ing the HiddenROM mode. To verify the
protect circuit, apply high vo ltage (VID) to A9, specify (A6, A 3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address
in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear
on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the abo ve
method because other than the HiddenROM mode, it is the same as the sector group protect previously men-
tioned.
Take note that other sector groups will be affected if an address other than those for the HiddenROM area is
selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection
CANNOT BE CANCELLED.
MBM29PL32TM/BM90/10
31
Write Operation Status
Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the device for
current mode operation. When checking Hardware Sequence Flags during program operations, it should be
checked 4 µs after issuing program command. During sector erase, the part provides the status flags automat-
ically to the I/O ports. The information on DQ2 is address sensitive. If an address from an erasing sector is
consecutively read, then the DQ2 bit will toggle. However DQ2 will not toggle if an address from a non-erasing
sector is consecutively read. This allows the user to determine which sectors are erasing.
Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one
av ailab le f or read) is pro vided, then stored data can be read from the de vice . If the address of an erasing sector
(one unavailabl e for read) is applied, the device will output its status bits.
Hardware Sequence Flags
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
*3 : DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations.
*4 : The Data Polling algorithm detailed in “Data Polling Algorithm” in ■FLOW CHART should be used for Write-
Buffer-Programming operations. Note that DQ7 during Write-Buffer-Programming indicates the data-bar for
DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Status DQ7DQ6DQ5DQ3DQ2DQ1*3
In
Progress
Embedded Program Algorithm DQ7Toggle 0 0 1 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle*1N/A
Program
Suspend
Mode
Program-Suspend-Read
(Program Suspended Sector) Data Data Data Data Data Data
Program-Suspend-Read
(Non-Program Suspended Sector) Data Data Data Data Data Data
Erase
Suspend
Mode
Erase-Suspend-Read
(Erase Suspended Sector) 1 1 0 0 Toggle*1N/A
Erase-Suspend-Read
(Non-Erase Suspended Sector) Data Data Data Data Data Data
Erase-Suspend-Program
(Non-Erase Suspended Sector) DQ7Toggle 0 0 1*2N/A
Exceeded
Time
Limits
Embedded Program Algorithm DQ7Toggle 1 0 1 N/A
Embedded Erase Algorithm 0 Toggle 1 1 N/A N/A
Erase
Suspend
Mode
Erase-Suspend-Program
(Non-Erase Suspended Sector) DQ7Toggle 1 0 N/A N/A
Write to
Buffer*4
BUSY State DQ7Toggle 0 N/A N/A 0
Exceeded Timing Limits DQ7Toggle 1 N/A N/A 0
ABORT State N/A Toggle 0 N/A N/A 1
MBM29PL32TM/BM90/10
32
DQ7
Data Polling
The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce
re verse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the
de vice will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the
device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to
read device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “Data Polling
Algorithm” in ■FLOW CHART.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector addresses of sectors being erased, not protected
sectors. Otherwise, the status may become invalid.
If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 µs, then
the de vice returns to read mode. After an erase command sequence is written, if all sectors selected f or erasing
are protected, Data Polling on DQ7 is active for approximately 100 µs, then the device returns to read mode. If
not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ7 at one instant of time, and then that byte’s valid data the next. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device completes the Embedded
Algorithm operation and DQ7 has a v alid data, the data outputs on DQ6 to DQ0 ma y still be inv alid. The valid data
on DQ7 to DQ0 will be read on the successive read attempts.
The Data Polling feature is active only dur ing the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erace Suspendmode or sector erase time-out.
See “Data Polling dur ing Embedded Algorithm Operation Timing Diagram” in ■SWITCHING WAVEFORM for
the Data Polling timing specifications and diagram.
DQ6
Toggle Bit I
The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the ne xt successiv e attempts.
During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. F or chip er ase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programm operation, if the sector being wr itten to is protected, the Toggle bit will toggle for about 1 µs and
then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for
the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100 µs and
then drop back into read mode, having data kept remained.
Either CE or OE toggling will cause the DQ6 to toggle. See “ Toggle Bit l Timing Diagramduring Embedded
Algorithm Operations” in ■SWITCHING WAVEFORM for the Toggle Bit I timing specifications and diagram.
MBM29PL32TM/BM90/10
33
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (inter nal pulse count). Under
these conditions DQ5 will produce a “1”. This is a f ailure condition indicating that the program or er ase cycle was
not successfully completed. Data Polling is the only operating function of the device under this condition. The
CE circuit will partially power down the de vice under these conditions (to appro ximately 2 mA). The OE and WE
pins will control the output disable functions as described in “MBM29PL32TM/BM User Bus Operations (Word
Mode : BYTE = VIH)” and “MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE
BUS OPERATION.
The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a v alid data on DQ7 bit and DQ6 nev er stop toggling. Once the de vice has e xceeded timing limits , the DQ5
bit will indicate a “1”. Note that this is not a de vice failure condition since the de vice w as incorrectly used. If this
occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to
determine whether the sector erase timer window is still open. If DQ3 is “1” the internally controlled erase cycle
has begun. If DQ3 is “0”, the device will accept additional sector erase commands. To insure the command has
been accepted, the system software should check the status of DQ3 prior to and following each subsequent
Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted.
See “Hardware Sequence Flags”.
DQ2
Toggle Bit II
This Toggle bit II, along with DQ6, can be used to deter mine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successiv e reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
de vices are in the er ase-suspended-read mode , successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the de vice is in the erase-suspended-program mode, successive reads from the non-erase
suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “DQ2 vs. DQ6” in ■SWITCHING
WAVEFORM.
Furthermore, DQ2 can also be used to determine which sector is being erased. At the erase mode , DQ2 toggles
if this bit is read from an erasing sector.
MBM29PL32TM/BM90/10
34
Reading Toggle Bits DQ6 / DQ2
Whenever the system initially begins reading Toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to deter mine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle
bit after the first read. After the second read, the system would compare the ne w v alue of the Toggle bit with the
first. If the Toggle bit is not toggling, the de vice has completed the progr am or er ase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
How ev er, if, after the initial tw o read cycles, the system determines that the Toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ5
went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the de vice did not complete the operation successfully, and the system m ust write
the reset command to return to reading array data.
The remaining scenario is that the system initially deter mines that the Toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, deter-
mining the status as described in the previous par agraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “Toggle Bit Algorithm” in ■FLOW CHART.)
Toggle Bit Status
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
DQ1
Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was abor ted. Under these conditions DQ1 produces a "1".
The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array
data. See "Write Buffer Programming Operations" section for more details.
RY/BY
Ready/Busy
The device provides a R Y/BY open-drain output pin to indicate to the host system that the Embedded Algorithms
are either in progress or has been completed. If the output is low, the device is busy with either a program or
erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the
de vice is placed in an Erase Suspend mode , the RY/BY output will be high, by means of connecting with a pull-
up resister to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the f ourth WE pulse. During an erase
operation, the RY/BY pin is driv en lo w after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See “RY/BY Timing Diagra m during Program/Erase Oper ation Timing
Diagram” and “RESET Timing Diagram ( During Embedded Algorithms )” in ■SWITCHING WAVEFORM for a
detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Mode DQ7DQ6DQ2
Program DQ7Toggle 1
Erase 0 Toggle Toggle *1
Erase-Suspend-Read
(Erase-Suspended Sector) 1 1 Toggle *1
Erase-Suspend-Program DQ7Toggle 1 *2
MBM29PL32TM/BM90/10
35
Word/Byte Configuration
BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the
de vice operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven
low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address bit, and
DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence com-
mands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
le vel signals that ma y e xist during power tr ansitions. During power up the de vice automatically reset the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incor porates several features to prevent inadver tent wr ite cycles resulting for m VCC power-up
and power-down transitions or system noise.
(1) Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO. If VCC < VLKO, the command register is disabled and all inter nal program/erase circuits are disabled.
Under this condition, the de vice will reset to the read mode. Subsequent writes will be ignored until the VCC lev el
is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above VLKO.
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
(2) Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
(3) Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE mus t
be a logical zero while OE is a logical one.
(4) Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
(5) Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored .
MBM29PL32TM/BM90/10
36
■ABSOLUTE MAXIMUM RATINGS
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions , input or I/O pins may undershoot
VSS to –0.2 V f or periods of up to 20 ns. Maximum DC v oltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns
*3 : Minimum DC input voltage is –0.5V. During voltage transitions, these pins may undershoot VSS to –0.2 V for
periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN–VCC) dose not exceed to
+9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
* : Voltage is defined on the basis of VSS = GND = 0V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min Max
Storage Temperature Tstg –55 +125 °C
Ambient Temperature with Power Applied TA–20 +85 °C
Voltage with Respect to Ground All Pins Except
A9, OE, and RESET *1,*2VIN, VOUT –0.5 VCC +0.5 V
Power Supply Voltage *1VCC –0.5 +4.0 V
Input Voltage A9, OE, and RESET *1,*3VIN –0.5 +12.5 V
Input Voltage WP/ACC *1,*3VACC –0.5 +12.5 V
Parameter Symbol Value Unit
Min Max
Ambient Temperature 90 TA–20 +70 °C
10 –20 +85
VCC Supply Voltage * VCC +3.0 +3.6 V
MBM29PL32TM/BM90/10
37
■MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
Maximum Undershoot Waveform
+0.6 V
–0.5 V
20 ns
–2.0 V 20 ns
20 ns
Maximum Overshoot Waveform 1
0.7 × VCC
VCC +0.5 V
20 ns
VCC +2.0 V 20 ns
20 ns
Maximum Overshoot Waveform 2
VCC +0.5 V
+12.5 V
20 ns
+14.0 V 20 ns
20 ns
Note: This waveform is applied for A9, OE, RESET, and ACC.
MBM29PL32TM/BM90/10
38
■ELECTRICAL CHARACTERISTICS
1. DC Characteristics
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component.
*2 : Maximum ICC values are tested with VCC = VCC Max
*3 : ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
*4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns.
Parameter Symbol Conditions Value Unit
Min Typ Max
Input Leakage Current ILI VIN = VSS to VCC,
VCC = VCC Max WP/ACC pin –2.0 — +2.0 µA
Others –1.0 — +1.0
Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max –1.0 — +1.0 µA
A9, OE, RESET Inputs Leakage
Current ILIT VCC = VCC Max,
A9, OE, RESET = 12.5 V ——35µA
VCC Active Current
(Read ) *1,*2ICC1
CE = VIL, OE = VIH,
f = 5 MHz Word — 18 20
mA
Byte — 16 20
CE = VIL, OE = VIH,
f = 10 MHz Word — 35 50
Byte — 35 50
VCC Active Current
(Intra-Page Read ) *2 ICC2 CE = VIL, OE = VIH, tPRC = 25ns,
4-Word —1020mA
VCC Active Current
(Program / Erase) *2,*3ICC3 CE = VIL, OE = VIH —5060mA
VCC Standby Current *2ICC4 CE = VCC ±0.3 V,
RESET = VCC ±0.3 V,
OE = VIH, WP/ACC = VCC ±0.3 V —15µA
VCC Reset Current *2ICC5 RESET = VCC ±0.3 V,
WP/ACC = VCC ±0.3 V —15µA
VCC Automatic Sleep Current *4ICC6
CE = VSS ±0.3 V,
RESET = VCC ±0.3 V,
VIN = VCC ±0.3V or Vss ±0.3V,
WP/ACC = VCC ±0.3 V
—15µA
VCC Active Current
(Erase-Suspend-Program) *2ICC7 CE = VIL, OE = VIH —5060mA
ACC Accelerated Program
Current IACC
CE = VIL, OE = VIH,
Vcc = Vcc Max,
WP/ACC =VACC
Max
WP/ACC pin — — 20
mA
Vcc Pin — — 60
Input Low Level VIL — –0.5 — 0.6 V
Input High Level VIH —0.7×VCC —V
CC + 0.3 V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration VACC VCC = 3.0 V to 3.6 V 11.5 12.0 12.5 V
Voltage for Autoselect, and
Temporary Sector Unprotected VID VCC = 3.0 V to 3.6 V 11.5 12.0 12.5 V
Output Low Voltage Level VOL IOL = 4.0 mA, VCC = VCC Min — — 0.45 V
Output High Voltage Level VOH IOH = –2.0 mA, VCC = VCC Min 0.85×VCC ——V
Low VCC Lock-Out Voltage VLKO —2.3—2.5V
MBM29PL32TM/BM90/10
39
2. AC Characteristics
• Read Only Operations Characteristics
* : Test Conditions :
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCC
Timing measurement reference level
Input : VCC / 2
Output : VCC / 2
Parameter Symbols Condition
Value*
Unit90 10
JEDEC Standard Min Max Min Max
Read Cycle Time tAVAV tRC —90100 ns
Address to Output Delay tAVQV tACC CE = VIL,
OE = VIL 90 100 ns
Chip Enable to Output Delay tELQV tCE OE = VIL 90 100 ns
Page Read Cycle Time — tPRC —2530 ns
Page Address to Output Delay — tPACC CE = VIL,
OE = VIL 25 30 ns
Output Enable to Output Delay tGLQV tOE —25 30 ns
Chip Enable to Output High-Z tEHQZ tDF —25 30 ns
Output Enable
Hold Time Read —t
OEH —00ns
Toggle and Data Polling — 10 10 ns
Output Enable to Output High-Z tGHQZ tDF —25 30 ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First tAXQX tOH —00ns
RESET Pin Low to Read Mode — tREADY —20 20 µs
Test Conditions
CL
3.3 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
Diode = 1N3064
or Equivalent
6.2 kΩ
MBM29PL32TM/BM90/10
40
• Write (Erase/Program) Operations
(Continued)
Parameter Symbol Value
Unit90 10
JEDEC Standard Min Typ Max Min Typ Max
Write Cycle Time tAVAV tWC 90 100 ns
Address Setup Time tAVWL tAS 0 0ns
Address Setup Time to OE Low During
Toggle Bit Polling —t
ASO 15 15 ns
Address Hold Time tWLAX tAH 45 45 ns
Address Hold Time from CE or OE High
During Toggle Bit Polling —t
AHT 0 0ns
Data Setup Time tDVWH tDS 35 35 ns
Data Hold Time tWHDX tDH 0 0ns
OE Setup Time — tOES 0 0ns
CE High During Toggle Bit Polling — tCEPH 20 20 ns
OE High During Toggle Bit Polling — tOEPH 20 20 ns
Read Recover Time Before Write
(OE High to WE Low) tGHWL tGHWL 0 0ns
Read Recover Time Before Write
(OE High to CE Low) tGHEL tGHEL 0 0ns
CE Setup Time tELWL tCS 0 0ns
WE Setup Time tWLEL tWS 0 0ns
CE Hold Time tWHEH tCH 0 0ns
WE Hold Time tEHWH tWH 0 0ns
CE Pulse Width tELEH tCP 35 35 ns
Write Pulse Width tWLWH tWP 35 35 ns
CE Pulse Width High tEHEL tCPH 25 25 ns
Write Pulse Width High tWHWL tWPH 30 30 ns
Effective Page
Programming Time
(Write Buffer Programming) Per Word tWHWH1 tWHWH1 23.5 23.5 µs
Programming Time Word 100 100 µs
Sector Erase Operation *1tWHWH2 tWHWH2 1.0 1.0 s
VCC Setup Time — tVCS 50 50 µs
Recovery Time From RY/BY —t
PB 0 0ns
Erase/Program Valid to RY/BY Delay — tBUSY 90 90 ns
Rise Time to VID *2—t
VIDR 500 500 ns
Rise Time to VACC *3—t
VACCR 500 500 ns
Voltage Transition Time *2—t
VLHT 4 4µs
MBM29PL32TM/BM90/10
41
(Continued)
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Group Protection operation.
*3 : This timing is for Accelerated Program operation.
Parameter Symbol Value
Unit90 10
JEDEC Standard Min Typ Max Min Typ Max
Write Pulse Width *2—t
WPP 100 100 µs
OE Setup Time to WE Active *2—t
OESP 4 4µs
CE Setup Time to WE Active *2—t
CSP 4 4µs
RESET Pulse Width — tRP 500 500 ns
RESET High Time Before Read — tRH 100 100 ns
Delay Time from Embedded Output
Enable —t
EOE 90 100 ns
Erase Time-out Time — tTOW 50 50 µs
Erase Suspend Transition Time — tSPD 20 20 µs
MBM29PL32TM/BM90/10
42
■ERASE AND PROGRAMMING PERFORMANCE
■TSOP (1) PIN CAPACITANCE
Notes : • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■FBGA PIN CAPACITANCE
Notes : • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
Parameter Limits Unit Remarks
Min Typ Max
Sector Erase Time — 1 15 s Excludes programming time prior to
erasure
Programming Time — 100 3000 µs
Excludes system-level overhead
Effective Page Programming
Time
(Write Buffer Programming) — 23.5 — µs
Chip Programming Time — — 300 s
Absolute Maximum
Programming Time (16 words) ——6ms
Non programming within the same
page
Erase/Program Cycle 100,000 — — cycle —
Parameter Symbol Test Setup Value Unit
Min Typ Max
Input Capacitance CIN VIN = 0 — 8 10 pF
Output Capacitance COUT VOUT = 0 — 8.5 12 pF
Control Pin Capacitance CIN2 VIN = 0 — 8 1 0 pF
RESET pin and WP/ACC Pin
Capacitance CIN3 VIN = 0 — 20 25 pF
Parameter Symbol Test Setup Value Unit
Min Typ Max
Input Capacitance CIN VIN = 0 — 8 10 pF
Output Capacitance COUT VOUT = 0 — 8.5 12 pF
Control Pin Capacitance CIN2 VIN = 0 — 8 10 pF
RESET pin and WP/ACC Pin
Capacitance CIN3 VIN = 0 — 15 20 pF
MBM29PL32TM/BM90/10
43
■SWITCHING WAVEFORMS
•Key to Switching Waveforms
Read Operation Timing Diagram
WAVEFORM INPUTS OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
“H” or “L”
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
“Off” State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OH
t
OE
Data
t
RC
Address Address Stable
High-Z Output Valid High-Z
t
OEH
MBM29PL32TM/BM90/10
44
RESET
tACC
tOH
Data
tRC
Address Address Stable
High-Z Output Valid
tRH
CE
tRP tRH tCE
Data
A1 to A0
(A-1)
A20 to A2
CE
OE
WE
Aa Ab Ac
tRC
tACC
tCE
tOE
tOH tOH tOH
tDF
tPACC tPACC
tOEH
tPRC
Da Db Dc
Address Valid
High-Z
Page Read Operation Timing Diagram
Hardware Reset/Read Operation Timing Diagram
MBM29PL32TM/BM90/10
45
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
tCH
tWP tWHWH1
tWC tAH
CE
OE
tRC
Address
Data
tAS
tOE
tWPH
tGHWL
tDH
DQ7
PD
A0h DOUT
WE
555h PA PA
tOH
Data Polling3rd Bus Cycle
tCS tCE
tDS
DOUT
tDF
Alternate WE Controlled Program Operation Timing Diagram
MBM29PL32TM/BM90/10
46
tCP
tDS
tWHWH1
tWC tAH
WE
OE
Address
Data
tAS
tCPH
tDH
DQ 7
A0h D OUT
CE
555h PA PA
Data Polling3rd Bus Cycle
tWS tWH
tGHEL
PD
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
Alternate CE Controlled Program Operation Timing Diagram
MBM29PL32TM/BM90/10
47
Address
Data
VCC
CE
OE
WE
555h 2AAh 555h 555h 2AAh SA*
tWC tAS tAH
tCS
tGHWL
tCH
tWP
tDS
tVCS
tDH
tWPH
AAh 55h 80h AAh 55h 10h/
30h
10h for Chip Erase
RY/BY
tBUSY
SA*
30h
tTOW
* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.
Chip/Sector Erase Operation Timing Diagram
MBM29PL32TM/BM90/10
48
Address
Data
CE
WE
XXXh
tWC
tCS tCH
tWP
tDS
B0h
RY/BY
tSPD
Erase Suspend Operation Timing Diagram
MBM29PL32TM/BM90/10
49
tOEH
tCH tOE
tCE
tDF
tEOE
tBUSY
tWHWH1 or 2
CE
DQ7
RY/BY
DQ6 to DQ0
DQ7DQ7 =
Valid Data
DQ6 to DQ0 =
Output Flag DQ6 to DQ0
Valid Data
OE
WE
Address
High-Z
High-Z
Data
Data
*
VA
4 µs
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Note : When checking Hardware Sequence Flags during program operations, it should be checked
4 µs after issuing program command.
Data Polling during Embedded Algorithm Operation Timing Diagram
MBM29PL32TM/BM90/10
50
* : DQ6 stops toggling (The device has completed the Embedded operation).
Note : When checking Hardw are Sequence Flags during progr am operations , it should be chec k ed
4 µs after issuing program command.
tDH tOE tCE
CE
WE
OE
DQ6/DQ2
Address
RY/BY
Data Toggle
Data Toggle
Data Toggle
Data Stop
Toggling Output
Valid
*
tBUSY
tOEH4 µs
tOEPH
tAHT tAHTtASO tAS
tCEPH
Toggle Bit l Timing Diagram during Embedded Algorithm Operations
* : DQ2 is read from the erase-suspended sector.
DQ2*
DQ6
WE Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase S uspend
Read
Enter Erase
Suspend P rogram
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Erase
Complete
Toggle
DQ
2
and D Q
6
with OE or C E
DQ2 vs. DQ6
MBM29PL32TM/BM90/10
51
Rising edge of the last WE signal
CE
RY/BY
WE
tBUSY
Entire programming
or erase operations
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
RESET
tREADY
CE, OE
tRH
tRP
RESET Timing Diagram ( Not during Embedded Algorithms )
MBM29PL32TM/BM90/10
52
tRP
RESET
tREADY
RY/BY
WE
tRB
RESET Timing Diagram ( During Embedded Algorithms )
MBM29PL32TM/BM90/10
53
t
VLHT
SGAX
A
20
, A
19
, A
18
, A
17
, A
16
A
15
, A
14
, A
13
, A
12
SGAY
A
6
, A
3
, A
2
, A
0
A
9
V
IH
t
VLHT
OE
V
IH
t
VLHT
t
VLHT
t
OESP
t
WPP
t
CSP
WE
CE
t
OE
01h
Data
V
CC
A
1
t
VCS
V
ID
V
ID
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
Sector Group Protection Timing Diagram
MBM29PL32TM/BM90/10
54
RESET
CE
WE
RY/BY t
VLHT
Program or Erase Command Sequence t
VLHT
t
VIDR
V
ID
Unprotection period
t
VCS
t
VLHT
V
CC
V
SS
, V
IL
or V
IH
Temporary Sector Group Unprotection Timing Diagram
MBM29PL32TM/BM90/10
55
SGAX: Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
SGAY
RESET
OE
WE
CE
Data
A1
V
CC
A
6
, A3, A2, A0
Address SGAXSGAX
60h
01h
40h
60h
60h
TIME-OUT
t
VCS
t
VLHT
t
VIDR
t
OE
Extended Sector Group Protection Timing Diagram
MBM29PL32TM/BM90/10
56
V
CC
CE
WE
t
VLHT
Program Command Sequence t
VLHT
t
VCS
t
VACCR
V
ACC
t
VLHT
Acceleration period
ACC
Accelerated Program Timing Diagram
MBM29PL32TM/BM90/10
57
■FLOW CHART
555h/AAh
555h/A0h
2AAh/55h
Program Address/Program Data
Programming Completed
Last Address
?
Increment Address
Verify Data
?
Data Polling
Program Command Sequence (Address/Command):
Write Program
Command Sequence
(See Below)
Start
No
No
Yes
Yes
Embedded
Program
Algorithm
in progress
EMBEDDED ALGORITHMS
Note : The sequence is applied for Word ( ×16 ) mode.
The addresses differ from Byte ( × 8 ) mode.
Embedded ProgramTM Algorithm
MBM29PL32TM/BM90/10
58
555h/AAh
555h/80h
2AAh/55h
555h/AAh
555h/10h
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
555h/AAh
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
2AAh/55h
Erasure Completed
Data = FFh
?
Data Polling
Write Erase
Command Sequence
(See Below)
Start
No
Yes
Embedded
Erase
Algorithm
in progress
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Additional sector
erase commands
are optional.
EMBEDDED ALGORITHMS
Note : The sequence is applied for Word ( ×16 ) mode.
The addresses differ from Byte ( × 8 ) mode.
Embedded EraseTM Algorithm
MBM29PL32TM/BM90/10
59
DQ 7 = Data?
*
No
No
DQ 7 = Data?
DQ 5 = 1?
Yes
Yes
No
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
Yes
Start
Fail Pass
Wait 4 µs after
issuing Program
Command
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Note : Data polling on sector-group protected sector may fail.
VA = Valid address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase operation
Data Polling Algorithm
MBM29PL32TM/BM90/10
60
*1 : Read Toggle bit twice to determine whether it is toggling.
*2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to “1”.
DQ6 = Toggle
DQ5 = 1?
Read DQ7 to DQ0
Addr. = "H" or "L"
Read DQ7 to DQ0
Addr. = "H" or "L"
Read DQ7 to DQ0
Addr. = "H" or "L"
Start
No
No
Yes
Yes
*1
*1, *2
?
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
DQ6 = Toggle
?
Read DQ7 to DQ0
Addr. = "H" or "L"
*1
Wait 4 µs after
issuing Program
Command
Toggle Bit Algorithm
MBM29PL32TM/BM90/10
61
Start
No No
No
Yes
Yes Yes
Data = 01h?
Device Failed
PLSCNT = 25?
PLSCNT = 1
Remove VID from A9
Write Reset Command
Remove VID from A9
Write Reset Command
Sector Group Protection
Completed
Protect Another Sector
Group?
Increment PLSCNT
Read from Sector Group
Addr. = SGA, A1 = VIH
A6 = A3 = A2 = A0 = VIL
Setup Sector Group Addr.
(A20, A19, A18, A17, A16,
A15, A14, A13, A12)
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
()
*
* : A-1 is VIL in Byte ( × 8 ) mode.
Sector Group Protection Algorithm
MBM29PL32TM/BM90/10
62
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Start
Temporary Sector Group
Unprotection Completed
*2
*1 : All protected sector groups are unprotected.
*2 : All previously protected sector groups are protected.
Temporary Sector Group Unprotection Algorithm
MBM29PL32TM/BM90/10
63
To Protect Sector Group
Yes
No
No
PLSCNT = 1
Protection Other Sector
Start
Sector Group Protection
Extended Sector Group
Completed
Remove VID from RESET
Write Reset Command
RESET = VID
Wait to 4 µs
Protection Entry?
To Setup Sector Group
Protection Write XXXh/60h
Write 60h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Time Out 250 µs
To Verify Sector Group Protection
Write 40h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Data = 01h?
Group?
Device is Operating in
Temporary Sector Group
Read from Sector Group
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Increment PLSCNT
No
Yes
Yes
Unprotection Mode
Address
Setup Next Sector Group
Address
No
Yes
PLSCNT = 25?
Device Failed
Remove VID from RESET
Write Reset Command
Extended Sector Group Protection Algorithm
MBM29PL32TM/BM90/10
64
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
XXXh/A0h
555h/20h
Verify Data? No
Program Address/Program Data
Data Polling
Last Address
?
Programming Completed
XXXh/90h
XXXh/F0h
Increment Address No
Yes
Yes
Set Fast Mode
In Fast Program
Reset Fast Mode
Notes : • The sequence is applied for Word ( ×16 ) mode.
• The addresses differ from Byte ( × 8 ) mode.
Embedded ProgramTM Algorithm for Fast Mode
MBM29PL32TM/BM90/10
65
■ORDERING INFORMATION
Part No. Package Access Time (ns) Remarks
MBM29PL32TM90TN 48-pin, plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
90 ns
Top Sector
MBM29PL32TM10TN 100 ns
MBM29PL32TM90PBT 48-ball, plastic FBGA
(BGA-48P-M20) 90 ns
MBM29PL32TM10PBT 100 ns
MBM29PL32BM90TN 48-pin, plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
90 ns
Bottom Sector
MBM29PL32BM10TN 100 ns
MBM29PL32BM90PBT 48-ball, plastic FBGA
(BGA-48P-M20) 90 ns
MBM29PL32BM10PBT 100 ns
MBM29PL32TM/BM
DEVICE NUMBER/DESCRIPTION
32 Mbit (4M × 8/2M × 16) MirrorFlash with Page Mode,
Boot Sector
3.0 V-only Read, Program, and Erase
PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP(1) Standard Pinout)
PBT = 48-Ball Fine pitch Ball Grid Array
Package (FBGA)
90 TN
SPEED OPTION
90 = 90 ns access time
10 = 100 ns access time
MBM29PL32TM/BM90/10
66
■PACKAGE DIMENSIONS
(Continued)
48-pin plastic TSOP(1)
(FPT-48P-M19)
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
–.003
+.001
–0.08
+0.03
.007
0.17
"A" (Stand off height)
0.10(.004)
(Mounting
height)
(.472±.008)
12.00±0.20
LEAD No.
48
2524
1
(.004±.002)
0.10(.004) M
1.10 +0.10
–0.05
+.004
–.002.043
0.10±0.05
(.009±.002)
0.22±0.05
(.787±.008)
20.00±0.20
(.724±.008)
18.40±0.20
INDEX
2003 FUJITSU LIMITED F48029S-c-6-7
C
0~8˚
0.25(.010)
0.50(.020)
0.60±0.15
(.024±.006)
Details of "A" part
*
*
MBM29PL32TM/BM90/10
67
(Continued)
48-ball plastic FBGA
(BGA-48P-M20)
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
C
2003 FUJITSU LIMITED B48020S-c-2-2
8.00±0.20(.315±.008)
0.38±0.10(.015±.004)
(Stand off)
(Mounting height)
6.00±0.20
(.236±.008)
0.10(.004)
0.80(.031)TYP
5.60(.220)
4.00(.157)
48-ø0.45±0.05
(48-ø.018±.002) M
ø0.08(.003)
HGFEDCBA
6
5
4
3
2
1
.043 –.005
+.003
–0.13
+0.12
1.08
(INDEX AREA)
MBM29PL32TM/BM90/10
FUJITSU LIMITED
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