K9K1208U0C-HCB00 - Samsung Semiconductor Division

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

Revision No.

0.0

1.0

2.0

2.1

2.2

2.3

2.4

2.5

Remark

Advance

Preliminary

History

Initial issue.

1.Pin assignment of TBGA dummy ball is changed.

(before) DNU --> (after) N.C

2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 34)

3. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 35)

4. Add the specification of Block Lock scheme.(Page 29~32)

5. Pin assignment of TBGA A3 ball is changed.

(before) N.C --> (after) Vss

1. The Maximum operating current is changed.

Read : Icc1 20mA-->30mA

Program : Icc2 20mA-->40mA

Erase : Icc3 20mA-->40mA

The min. Vcc value 1.8V devices is changed.

K9K12XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.

K9K1208U0C-HCB0,HIB0

K9K12XXQ0C-HCB0,HIB0

K9K1216U0C-HCB0,HIB0

K9K1216Q0C-HCB0,HIB0

Errata is added.(Front Page)-K9K12XXQ0C

tWC tWP tRC tREH tRP tREA tCEA

Specification 45 25 50 15 25 30 45

Relaxed value 60 40 60 20 40 40 55

1. Max. Thickness of TBGA packge is changed.

0.09±0.10(Before) --> 1.10±0.10(After)

2. New definition of the number of invalid blocks is added.

(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.)

1. The guidence of LOCKPRE pin usage is changed.

Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-

READ, connect it Vss.(Before)

--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect

it Vss or leave it N.C(After)

2. 2.65V device is added.

3. Note is added.

(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for

durations of 20 ns or less.)

Draft Date

Sep. 12th 2002

Jan. 3rd 2003

Jan. 17th 2003

Mar. 5th 2003

Mar. 13rd 2003

Mar. 17th 2003

Apr. 4th 2003

Jul. 4th 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

Revision No.

2.6

2.7

2.8

Remark

History

1. tREA value of 1.8V device is changed.

K9K12XXQ0C : tREA 30ns --> 35ns

2. Errata is deleted.

1. Command table is edited.

2. AC parameters are changed.

tWC tWH tWP tRC tREH tRP tREA tCEA

K9K12XXU0C

K9K12XXD0C 50 15 25 50 15 25 30 45

K9K12XXQ0C 60 20 40 60 20 40 40 55

1. AC parameters are changed.

tWC tWH tWP tRC tREH tRP tREA tCEA

K9K1208Q0C 50 15 25 50 15 25 35 45

K9K1216Q0C 60 20 40 60 20 40 40 55

Draft Date

Aug. 20th. 2003

Oct. 28th. 2003

Dec. 17th. 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

GENERAL DESCRIPTION

FEATURES

• Voltage Supply

- 1.8V device(K9K12XXQ0C) : 1.70~1.95V

- 2.65V device(K9F12XXD0C) : 2.4~2.9V

- 3.3V device(K9K12XXU0C) : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

- X8 device(K9K1208X0C) : (64M + 2048K)bit x 8 bit

- X16 device(K9K1216X0C) : (32M + 1024 K)bit x 16bit

- Data Register

- X8 device(K9K1208X0C) : (512 + 16)bit x 8bit

- X16 device(K9K1216X0C) : (256 + 8)bit x16bit

• Automatic Program and Erase

- Page Program

- X8 device(K9K1208X0C) : (512 + 16)Byte

- X16 device(K9K1216X0C) : (256 + 8)Word

- Block Erase :

- X8 device(K9K1208X0C) : (16K + 512)Byte

- X16 device(K9K1216X0C) : ( 8K + 256)Word

• Page Read Operation

- Page Size

- X8 device(K9K1208X0C) : (512 + 16)Byte

- X16 device(K9K1216X0C) : (256 + 8)Word

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)*

*K9K1216Q0C : 60ns(Min.)

64M x 8 Bit / 32M x 16 Bit NAND Flash Memory

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Intelligent Copy-Back

• Unique ID for Copyright Protection

• Package

- K9K12XXX0C-DCB0/DIB0

63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm)

- K9K12XXX0C-HCB0/HIB0

63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm)

- Pb-free Package

Offered in 64Mx8bit or 32Mx16bit, the K9K12XXX0C is 512M bit with spare 16M bit capacity. The device is offered in 1.8V, 2.65V,

3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can

be performed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed

in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(K9K1216Q0C :

60ns) cycle time per byte (X8 device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well

as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required ,

and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K12XXX0C′s extended

reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.

The K9K12XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable

applications requiring non-volatility.

PRODUCT LIST.

Part Number Vcc Range Organization PKG Type

K9K1208Q0C-D,H 1.70 ~ 1.95V X8

TBGA

K9K1216Q0C-D,H X16

K9K1208D0C-D,H 2.4 ~ 2.9V X8

K9K1216D0C-D,H X16

K9K1208U0C-D,H 2.7 ~ 3.6V X8

K9K1216U0C-D,H X16

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

K9K12XXX0C-DCB0,HCB0/DIB0,HIB0 X16

PIN CONFIGURATION (TBGA)

63-Ball TBGA (measured in millimeters)

PACKAGE DIMENSIONS

9.00±0.10

#A1

Side View

Top View

1.10±0.10

0.45±0.05

4321

Bottom View

11.00±0.10

63-∅0.45±0.05

0.80 x7= 5.60

11.00±0.10

0.80 x5= 4.00

0.80

0.32±0.05

0.08MAX

2.80

2.00

9.00±0.10

(Datum B)

(Datum A)

0.20 M A B

∅

0.80

0.80 x11= 8.80

0.80 x9= 7.20

6 5

9.00±0.10

(Top View) (Top View)

R/B/WE/CEVssALE/WP

/RE CLE

NCNC

NC NC Vcc

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

VssI/O6I/O4I/O3I/O2Vss

NC NC

NC NC NC

LOCKPRE

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.CN.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.CN.C

N.C N.C

N.C

R/B/WE/CEVssALE/WP

/RE CLE

I/O7I/O5

I/O12 IO14 Vcc

I/O10I/O8 I/O1

I/O9I/O0 I/O3 VccQ I/O6 I/O15

VssI/O13I/O4I/O11I/O2Vss

NC NC

NC NC NC

LOCKPRE

3456 1 2

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

PIN DESCRIPTION

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

Pin Name Pin Function

I/O0 ~ I/O7

(K9K1208X0C)

I/O0 ~ I/O15

(K9K1216X0C)

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The

I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-

ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and

output.

CLE COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation. Regarding CE control during

read operation, refer to ’Page read’ section of Device operation .

RE READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WE WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage

generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the

all blocks go to lock state.

R/B

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

VccQOUTPUT BUFFER POWER

VccQ is the power supply for Output Buffer.

VccQ is internally connected to Vcc, thus should be biased to Vcc.

Vcc POWER

VCC is the power supply for device.

Vss GROUND

N.C NO CONNECTION

Lead is not internally connected.

DNU DO NOT USE

Leave it disconnected

LOCKPRE

LOCK MECHANISM & POWER-ON AUTO-READ ENABLE

To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,

Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block

Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on

3.3V device(K9K12XXU0C)

Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

512Byte 16 Byte

Figure 1-1. K9K1208X0C (X8) FUNCTIONAL BLOCK DIAGRAM

Figure 2-1. K9K1208X0C (X8) ARRAY ORGANIZATION

VCC

X-Buffers 512M + 16M Bit

Command

NAND Flash

ARRAY

(512 + 16)Byte x 131072

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Control Logic

& High Voltage

Generator Global Buffers Output

Driver

VSS

A9 - A25

A0 - A7

Command

I/0 0

I/0 7

VCC/ VCCQ

VSS

1st half Page Register

(=256 Bytes) 2nd half Page Register

(=256 Bytes)

128K Pages

(=4,096 Blocks)

512 Byte

8 bit

16 Byte

1 Block =32 Pages

= (16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Byte

1 Block = 528 Byte x 32 Pages

= (16K + 512) Byte

1 Device = 528Bytes x 32Pages x 4,096 Blocks

= 528 Mbits

Page Register

CLE ALE

Column Address

Row Address

(Page Address)

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A8 is set to "Low" or "High" by the 00h or 01h Command.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0A1A2A3A4A5A6A7

2nd Cycle A9A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

4th Cycle A25 *L *L *L *L *L *L *L

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

256Word 8 Word

Figure 2-2. K9K1216X0C (X16) ARRAY ORGANIZATION

Page Register

(=256 Words)

128K Pages

(=4,096 Blocks)

256 Word

16 bit

8 Word

1 Block =32 Pages

= (8K + 256) Word

I/O 0 ~ I/O 15

1 Page = 264 Word

1 Block = 264 Word x 32 Pages

= (8K + 256) Word

1 Device = 264Words x 32Pages x 4096 Blocks

= 528 Mbits

Page Register

Figure 1-2. K9K1216X0C (X16) FUNCTIONAL BLOCK DIAGRAM

VCC

X-Buffers 512M + 16M Bit

Command

NAND Flash

ARRAY

(256 + 8)Word x 131072

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Control Logic

& High Voltage

Generator Global Buffers Output

Driver

VSS

A9 - A25

A0 - A7

Command

I/0 0

I/0 15

VCC/ VCCQ

VSS

CLE ALE

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 to 15

1st Cycle A0A1A2A3A4A5A6A7L*

2nd Cycle A9A10 A11 A12 A13 A14 A15 A16 L*

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 L*

4th Cycle A25 L* L* L* L* L* L* L* L*

Column Address

Row Address

(Page Address)

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

PRODUCT INTRODUCTION

The K9K12XXX0C is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528(X8 device) or 264(X16 device)

columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8

device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buff-

ers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially con-

nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A

NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2.

The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory

array consists of 4096 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase

operation is prohibited on the K9K12XXX0C.

The K9K12XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9K1216X0C allows sixteen bit wide data

transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows

systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written

through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and

Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one

bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com-

mands like Page Program and Copy-back Program and Block Erase, require three cycles: one cycle for setup and the other cycle for

execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 25 addresses(X8 device) or 24

addresses(X16 device), thereby requiring four cycles for word-level addressing: column address, low row address and high row

address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In

Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific com-

mands into the command register. Table 1 defines the specific commands of the K9K12XXX0C.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide

identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. COMMAND SETS

NOTE : 1. The 01h command is available only on X8 device(K9K1208X0C).

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1 00h/01h(1) -

Read 2 50h -

Read ID 90h -

Reset FFh -O

Page Program 80h 10h

Copy-Back Program 00h 8Ah

Lock 2Ah -

Unlock 23h 24h

Lock-tight 2Ch -

Read Block Lock Status 7Ah -

Block Erase 60h D0h

Read Status 70h -O

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9K12XXX0C-DCB0,HCB0 :TA=0 to 70°C, K9K12XXX0C-DIB0,HIB0:TA=-40 to 85°C)

Parameter Symbol K9K12XXQ0C(1.8V) K9K12XXD0C(2.65V) K9K12XXU0C(3.3V) Unit

Min Typ. Max Min Typ. Max Min Typ. Max

Supply Voltage VCC 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

Supply Voltage VCCQ 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

Supply Voltage VSS 000000000 V

ABSOLUTE MAXIMUM RATINGS

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC, +0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

1.8V DEVICE 3.3V/2.65V DEVICE

Voltage on any pin relative to VSS

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

VCC -0.2 to + 2.45 -0.6 to + 4.6

VCCQ -0.2 to + 2.45 -0.6 to + 4.6

Temperature Under Bias K9K12XXX0C-XCB0 TBIAS -10 to +125 °C

K9K12XXX0C-XIB0 -40 to +125

Storage Temperature K9K12XXX0C-XCB0 TSTG -65 to +150 °C

K9K12XXX0C-XIB0

Short Circuit Current Ios 5mA

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

Parameter Symbol Test Conditions

K9K12XXX0C

Unit1.8V 2.65V 3.3V

Min Typ Max Min Typ Max Min Typ Max

Operat-

ing

Current

Sequential Read ICC1tRC=50ns, CE=VIL

IOUT=0mA -10 20 -10 20 -10 30

Program ICC2- - 10 20 -10 20 -10 40

Erase ICC3- - 10 20 -10 20 -10 40

Stand-by Current(TTL) ISB1CE=VIH, WP=0V/VCC - - 1- - 1- - 1

Stand-by Current(CMOS) ISB2CE=VCC-0.2, WP=0V/VCC -10 50 -10 50 -10 50

µA

Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10 - - ±10

Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10 - - ±10

Input High Voltage VIH*

I/O pins VCCQ

-0.4 -VCCQ

+0.3 VCCQ

-0.4 -VCCQ

+0.3 2.0 -VCCQ

+0.3

Except I/O pins VCC

-0.4 -Vcc

+0.3 VCC

-0.4 -VCC

+0.3 2.0 -VCC

+0.3

Input Low Voltage, All inputs VIL* --0.3 -0.4 -0.3 -0.5 -0.3 -0.8

Output High Voltage Level VOH

K9K12XXQ0C :IOH=-100µA

K9K12XXD0C :IOH=-100µA

K9K12XXU0C :IOH=-400µA

VCCQ

-0.1 - - VCCQ

-0.4 - - 2.4 - -

Output Low Voltage Level VOL

K9K12XXQ0C :IOL=100uA

K9K12XXD0C :IOL=100µA

K9K12XXU0C :IOL=2.1mA - - 0.1 - - 0.4 - - 0.4

Output Low Current(R/B)IOL(R/B)K9K12XXQ0C :VOL=0.1V

K9K12XXD0C :VOL=0.1V

K9K12XXU0C :VOL=0.4V 3 4 -3 4 -8 10 -mA

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V -20 pF

Input Capacitance CIN VIN=0V -20 pF

VALID BLOCK

NOTE :

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program

factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase

cycles.

3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 4026 -4096 Blocks

AC TEST CONDITION

(K9K12XXX0C-DCB0,HCB0 :TA=0 to 70°C, K9K12XXX0C-DIB0,HCB0 :TA=-40 to 85°C

K9K12XXQ0C : Vcc=1.70V~1.95V , K9K12XXD0C : Vcc=2.4V~2.9V , K9K12XXU0C : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9K12XXQ0C K9K12XXD0C K9K12XXU0C

Input Pulse Levels 0V to VccQ0V to VccQ0.4V to 2.4V

Input Rise and Fall Times 5ns 5ns 5ns

Input and Output Timing Levels VccQ/2 VccQ/2 1.5V

K9K12XXQ0C:Output Load (VccQ:1.8V +/-10%)

K9K12XXD0C:Output Load (VccQ:2.65V +/-10%)

K9K12XXU0C:Output Load (VccQ:3.0V +/-10%) 1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

K9K12XXU0C:Output Load (VccQ:3.3V +/-10%) - - 1 TTL GATE and CL=100pF

MODE SELECTION

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE ALE CE WE RE LOCKPRE WP Mode

HL L HX X Read Mode Command Input

LHLHX X Address Input(4clock)

HL L HXHWrite Mode Command Input

LHLHXHAddress Input(4clock)

L L L HXHData Input

LLLHX X Data Output

X X X X HX X During Read(Busy) on the devices

X X X X X X HDuring Program(Busy)

X X X X X X HDuring Erase(Busy)

X X(1) X X X X LWrite Protect

X X HX X 0V/VCC(2 0V/VCC(2) Stand-by

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

PROGRAM/ERASE CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Program Time tPROG -200 500 µs

Dummy Busy Time for the Lock or Lock-tight Block tLBSY -5 10 µs

Number of Partial Program Cycles

in the Same Page Main Array Nop - - 2cycles

Spare Array - - 3cycles

Block Erase Time tBERS -2 3 ms

AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT

NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

Parameter Symbol

Min Max Unit

K9K1208X0C

K9K12XXD0C

K9K12XXU0C K9K1216Q0C K9K1208X0C

K9K12XXD0C

K9K12XXU0C K9K1216Q0C

CLE setup Time tCLS 0 0 - - ns

CLE Hold Time tCLH 10 10 - - ns

CE setup Time tCS 0 0 - - ns

CE Hold Time tCH 10 10 - - ns

WE Pulse Width tWP 25(1) 40 - - ns

ALE setup Time tALS 0 0 - - ns

ALE Hold Time tALH 10 10 - - ns

Data setup Time tDS 20 20 - - ns

Data Hold Time tDH 10 10 - - ns

Write Cycle Time tWC 50 60 - - ns

WE High Hold Time tWH 15 20 - - ns

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

AC CHARACTERISTICS FOR OPERATION

NOTE: 1. K9F5608Q0C tREA = 35ns.

2. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

Parameter Symbol

Min Max

Unit

K9K1208X0C

K9K12XXD0C

K9K12XXU0C K9K1216Q0C K9K1208X0C

K9K12XXD0C

K9K12XXU0C K9K1216Q0C

Data Transfer from Cell to Register tR- - 10 10 µs

ALE to RE Delay tAR 10 10 - - ns

CLE to RE Delay tCLR 10 10 - - ns

Ready to RE Low tRR 20 20 - - ns

RE Pulse Width tRP 25 40 - - ns

WE High to Busy tWB - - 100 100 ns

Read Cycle Time tRC 50 60 - - ns

RE Access Time tREA - - 30/35(1) 40 ns

CE Access Time tCEA - - 45 55 ns

RE High to Output Hi-Z tRHZ - - 30 30 ns

CE High to Output Hi-Z tCHZ - - 20 20 ns

RE or CE High to Output hold tOH 15 15 - - ns

RE High Hold Time tREH 15 20 - - ns

Output Hi-Z to RE Low tIR 0 0 - - ns

WE High to RE Low tWHR1 60 60 - - ns

WE High to RE Low in Block Lcok tWHR2 100 100 - - ns

Device Resetting Time(Read/Program/ tRST --5/10/500(2) 5/10/500(2) µs

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

NAND Flash Technical Notes

Identifying Invalid Block(s)

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality

level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design

must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaran-

teed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid

block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the

1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8

device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the

information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original

invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of

the original invalid block information is prohibited.

*Check "FFh" at the column address

Figure 3. Flow chart to create invalid block table.

Start

Set Block Address = 0

Check "FFh" ?

Increment Block Address

Last Block ?

End

Yes

Create (or update) No

Invalid Block(s) Table of the 1st and 2nd page in the block

517(X8 device) or 256 and 261(X16 device)

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

NAND Flash Technical Notes (Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

Write 00h

I/O 0 = 0 ?

If ECC is used, this verification

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Write Address

Wait for tR Time

Verify Data No

Program Completed

or R/B = 1 ?

Program Error

Yes

Program Error

Yes

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

operation is not needed.

Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-

ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block

replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Write

Erase Failure Status Read after Erase --> Block Replacement

Program Failure Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Read Single Bit Failure Verify ECC -> ECC Correction

ECC : Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another block.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

NAND Flash Technical Notes (Continued)

Block Replacement

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)

* Step3

Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.

* Step4

Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

Buffer memory of the controller.

1st Block A

Block B

(n-1)th

nth

(page)

{

∼

1st

(n-1)th

nth

(page)

{

∼

an error occurs.

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

00h

(1) Command input sequence for programming ’A’ area

Address / Data input

80h 10h 00h 80h 10h

Address / Data input

The address pointer is set to ’A’ area(0~255), and sustained

01h

(2) Command input sequence for programming ’B’ area

Address / Data input

80h 10h 01h 80h 10h

Address / Data input

’B’, ’C’ area can be programmed.

It depends on how many data are inputted. ’01h’ command must be rewritten before

every program operation

The address pointer is set to ’B’ area(256~511), and will be reset to

’A’ area after every program operation is executed.

50h

(3) Command input sequence for programming ’C’ area

Address / Data input

80h 10h 50h 80h 10h

Address / Data input

Only ’C’ area can be programmed. ’50h’ command can be omitted.

The address pointer is set to ’C’ area(512~527), and sustained

’00h’ command can be omitted.

It depends on how many data are inputted.

’A’,’B’,’C’ area can be programmed.

Pointer Operation of K9K1208X0C(X8)

Table 2. Destination of the pointer

Command Pointer position Area

00h

01h

50h

0 ~ 255 byte

256 ~ 511 byte

512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

"A" area

256 Byte

(00h plane) "B" area

(01h plane) "C" area

(50h plane)

256 Byte 16 Byte

"A" "B" "C"

Internal

Page Register

Pointer select

commnad

(00h, 01h, 50h) Pointer

Figure 4. Block Diagram of Pointer Operation

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’

command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets

the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole

page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective

only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the

address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted

before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from

’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command

sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the

starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-

mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is

written. A complete read operation prior to ’80h’ command is not necessary.

00h

(1) Command input sequence for programming ’A’ area

Address / Data input

80h 10h 00h 80h 10h

Address / Data input

The address pointer is set to ’A’ area(0~255), and sustained

50h

(2) Command input sequence for programming ’B’ area

Address / Data input

80h 10h 50h 80h 10h

Address / Data input

Only ’B’ area can be programmed. ’50h’ command can be omitted.

The address pointer is set to ’B’ area(256~263), and sustained

’00h’ command can be omitted.

It depends on how many data are inputted.

’A’,’B’ area can be programmed.

Pointer Operation of K9K1216X0C(X16)

Table 3. Destination of the pointer

Command Pointer position Area

00h

50h 0 ~ 255 word

256 ~ 263 word main array(A)

spare array(B)

"A" area

256 Word

(00h plane) "B" area

(50h plane)

8 Word

"A" "B"

Internal

Page Register

Pointer select

command

(00h, 50h) Pointer

Figure 5. Block Diagram of Pointer Operation

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

System Interface Using CE don’t-care.

WE tWP

tCH

tCS

Start Add.(4Cycle)80h Data Input

CLE

ALE

Data Input

CE don’t-care

≈

10h

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal

528byte(x8 device), 264word(x16 device) page registers are utilized as seperate buffers for this operation and the system design

gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE

during the data-loading and reading would provide significant savings in power consumption.

Start Add.( 4Cycle)00h

CLE

ALE

Data Output(sequential)

CE don’t-care

≈

R/BtR

Figure 6. Program Operation with CE don’t-care.

Figure 7. Read Operation with CE don’t-care.

I/Ox

tCEA

out

tREA

I/O0~15

tOH

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Command Latch Cycle

CLE

ALE

I/Ox Command

tCLS

tCS

tCLH

tCH

tWP

tALS tALH

tDS tDH

NOTE: 1. I/O8~15 must be set to "0" during command or address input.

I/O8~15 are used only for data bus.

Device I/O DATA

I/Ox Data In/Out

K9K1208X0C(X8 device) I/O 0 ~ I/O 7 ~528byte

K9K1216X0C(X16 device) I/O 0 ~ I/O 151) ~264word

Address Latch Cycle

CLE

ALE

I/OXA0~A7

tCLS

tCS tWC

tWP

tALS

tDS tDH

tALH tALS

tWH

tWC

tWP

tDS tDH

tALH tALS

tWH

tWC

tWP

tDS tDH

tALH tALS

tWH tALH

tDS tDH

tWP

A9~A16 A17~A24 A25

tCH

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Input Data Latch Cycle

CLE

DIN 0 DIN 1 DIN n

ALE tALS

tCLH

tWC

tCH

tDS tDH tDS tDH tDS tDH

tWP

tWH

tWP tWP

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

R/B

Dout Dout Dout

tRC

tREA

tRR

tOH

tREA

tREH tREA tOH

tRHZ*

≈

≈≈≈≈

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

I/Ox

tRHZ*

tCHZ*

tRP

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Status Read Cycle

CLE

I/Ox 70h Status Output

tCLR

tCLH

tCS

tWP tCH

tDS tDH tREA

tIR tOH

tOH

tWHR1

tCEA

tCLS

tRHZ

tCHZ

tOH

READ1 OPERATION(READ ONE PAGE)

X8 device : m = 528 , Read CMD = 00h or 01h

X16 device : m = 264 , Read CMD = 00h

CLE

R/B

I/OX

ALE

Busy

00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2

Column

Address Page(Row)

Address

tWB tAR

tRtRC tRHZ

tRR

Dout m

tWC

≈≈ ≈

A25

N Address

tOH

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Read1 Operation(Intercepted by CE)

CLE

R/B

I/OX

ALE

Busy

00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2

Page(Row)

Address

Column

tWB tAR tCHZ

tRR

tRC

A25

tOH

Read2 Operation(Read One Page)

CLE

R/B

I/OX

ALE

50h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout n+m

M Address

n+M

tAR

tWB

tRR

A0~A3 : Valid Address

A4~A7 : Don′t care

≈

A25

Selected

Row

Start

address M

512 16

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Page Program Operation

CLE

R/B

I/OX

ALE

80h 70h I/O 0

Din

NDin 10h

527

A0 ~ A7A17 ~ A24A9 ~ A16

Sequential Data

Input Command Column

Address Page(Row)

Address 1 up to 528 Byte Data

Serial Input Program

Command Read Status

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

tPROGtWB

tWC tWC tWC

≈≈

≈

A25

≈

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Copy-Back Program Operation

CLE

R/B

I/OX

ALE

00h 70h I/O08AhA0~A7A17~A24A9~A16

Column

Address Page(Row)

Address Read Status

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

tPROG

tWB

tWC

≈

A0~A7A17~A24A9~A16

Column

Address Page(Row)

Address

Busy

tWB

Busy

≈

A25 A25 10h

Copy-Back Data

Input Command

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CLE

R/B

I/OX

ALE

60h A17 ~ A24A9 ~ A16

Auto Block Erase Setup Command Erase Command Read Status

Command I/O 0=1 Error in Erase

DOh 70h I/O 0

Busy

tWB tBERS

I/O0=0 Successful Erase

Page(Row)

Address

tWC

≈

A25

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

MANUFACTURE & DEVICE ID READ OPERATION

CLE

ALE

90h

Read ID Command Maker Code Device Code

00h

tREA

Address. 1cycle

tAR

I/Ox ECh Device

Device Device Code*

K9K12XXQ0C 36h

K9K1208D0C 76h

K9K1208U0C 76h

K9K1216D0C XX56h

K9K1216U0C XX56h

Code*

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-

ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-

tion. Two types of operations are available : random read, serial page read.

The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data

within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion of

this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in

50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column

address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin].

The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512

~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input

pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are

ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the

main area. Figures 8, 9 show typical sequence and timings for each read operation.

Figure 8. Read1 Operation

Start Add.( 4Cycle)

00h

X8 device : A0 ~ A7 & A9 ~ A25

Data Output(Sequential)

(00h Command)

Data Field Spare Field

CLE

ALE

R/B

Main array

(01h Command)

Data Field Spare Field

1st half array 2st half array

NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half

array (00h) at next cycle. 01h command is only available on X8 device(K9K1208X0C).

I/Ox

X16 device : A0 ~ A7 & A9 ~ A25 1)

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Figure 9. Read2 Operation

50h Data Output(Sequential)

Spare Field

CLE

ALE

R/B

Start Add.(4Cycle)

X8 device : A0 ~ A3 & A9 ~ A25

Main array

Data Field Spare Field

X16 device : A0 ~ A2 & A9 ~ A25

X8 device : A4 ~ A7 Don’t care

X16 device : A3 ~ A7 are "L"

I/Ox

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive

bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page program-

ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array.

The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which

up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile program-

ming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the attached

technical notes.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and

then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com-

mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-

gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,

thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be

entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by mon-

itoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid

while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The

internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read

Status command mode until another valid command is written to the command register.

Figure 10. Program Operation

80h

R/B

Address & Data Input I/O0Pass

10h 70h

Fail

tPROG

COPY-BACK PROGRAM

The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within

the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are

removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of

the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution

of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with

"00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16

device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah"

may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into

the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the

copied pages is prohibited before erase. Since the memory array is internally partitioned into four different planes, copy-back program

is allowed only within the same memory plane. Thus, A14 and A25, the plane address, of source and destination page address must

be the same."When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure

page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. For this reason,

two bit ECC is recommended for copy-back operation."

Figure 11. Copy-Back Program Operation

00h

R/B

Add.( 4Cycles) I/O0Pass

8Ah 70h

Fail

tPROG

Add.(4Cycles)

Source Address Destination Address

I/Ox

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Figure 12. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup com-

mand(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address

loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory

contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

60h

Block Add. : A9 ~ A25

R/B

Address Input(3Cycle) I/O0Pass

D0h 70h

Fail

tBERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

cycle, a read command(00h or 50h) should be given before serial access cycle.

Table4. Read Status Register Definition

I/O # Status Definition

I/O 0 Program / Erase "0" : Successful Program / Erase

"1" : Error in Program / Erase

I/O 1

Reserved for Future

Use

"0"

I/O 2 "0"

I/O 3 "0"

I/O 4 "0"

I/O 5 "0"

I/O 6 Device Operation "0" : Busy "1" : Ready

I/O 7 Write Protect "0" : Protected "1" : Not Protected

I/O 8~15 Not use Don’t care

I/Ox

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Figure 13. Read ID Operation

CLE

ALE

90h 00h

Address. 1cycle Maker code Device code

tCEA

tAR

tREA

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register

remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.

tWHR1

Figure 14. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is

already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST

after the Reset command is written. Refer to Figure 14 below.

Table5. Device Status

After Power-up After Reset

Operation Mode Read 1 Waiting for next command

FFh

R/BtRST

ECh Device

I/Ox

Device Device Code*

K9K12XXQ0C 36h

K9K1208D0C 76h

K9K1208U0C 76h

K9K1216D0C XX56h

K9K1216U0C XX56h

Code*

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block

Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data by allowing those blocks to be locked

or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first allows software control(command input

method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control(WP low pulse

input method) before locking can be changed that is useful for protecting infrequently changed code blocks.

The followings summarized the locking functionality.

- All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks.

- The Lock-tight command locks blocks and prevents from being unlocked.

And Lock-tight state can be returned to lock state only by Hardware control(WP low pulse input).

Block Lock Mode

- Command Sequence: Lock block Command(2Ah)

- All blocks default to locked by power-up and Hardware control(WP low pulse input)

- Partial block lock is not available; Lock block operation is based on all block unit

- Unlocked blocks can be locked by using the Lock block command, and a lock block’s status can be changed to unlock or lock-tight

using the appropriate commands

1. Block lock operation

1) Lock

> In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is

regarded as NAND Flash without LOCKPRE pin.

CLE

2Ah

Lock Command

I/Ox

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

- Command Sequence: Lock-tight block Command(2Ch)

- Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block that is lock-

tighten can’t have it’s state changed by software control, only by hardware control(WP low pulse input); Unlocking multi area is not

available

- Only locked blocks can be lock-tighten by lock-tight command.

3) Lock-tight

- Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address

- Unlocked blocks can be programmed or erased.

- An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate commands.

- Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available.

- Start block address must be nearer to the logical LSB(Least Significant Bit) than End blcok address.

- One block is selected for unlocking block when Start block address is same as End block address.

2) Unlock

CLE

ALE

23h

Unock Command

Add.1

Start Block Address 3cycles

I/Ox 24h

Add.2

End Block Address 3 cycles Unlock Command

CLE

2Ch

Lock-tight Command

I/Ox

Add.3 Add.1 Add.2 Add.3

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Program/Erase OPERATION(In Locked or Lock-tighten Block)

On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10

s(tLBSY)

60h(80h)

R/B

Address(&Data Input) D0h(10h)

tLBSY

I/Ox

Locked or Lock-tighten Block address

unlock

Lock

Lock-tight

Power-up

WPx = H &

Unlock block Command (23h) + Start Block Address

+ Command (24h) + End Block Address

Block Lock reset

WPx = L (>100ns)

Block Lock reset

WPx = L (>100ns)

WPx = H &

Lock block command (2Ah)

WPx = H &

Lock-tight block command (2Ch)

unlock

Figure 15. State diagram of Block Lock

Lock-tight

Lock-tight block command (2Ch)

Lock

Lock-tight

WPx = H &

Unlock block Command (23h) + Start Block Address

+ Command (24h) + End Block Address

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be pro-

grammed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the

content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control

allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or

CE does not need to be toggled for updated status. Blcok Lock Status Read is prohibited while the device is busy state.

Refer to table 6 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further

commands are issued to it. In high state of LOCKPRE pin, write protection status can be checked by Block Lock Status

Read(7Ah) while in low state by Status Read(70h).

2. Block Lock Status Read

CLE

ALE

7Ah

Read Block Lock Block Lock Status

Add.1

Block Address 3cycle

I/Ox Dout

Add.2

Table6. Block Lock Status Register definitions

status Command

tWHR2

Add.3

IO7~IO3 IO2(Unlock) IO1(Lock) IO0(Lock-tight)

Read 1) block

case X0 1 0

Read 2) block

case X1 1 0

Read 3) block

case X0 0 1

Read 4) block

case X1 0 1

(1)Lock

(2)unlock

(3)Lock-tight

(4)unlock

(1)Lock (3)Lock-tight

(1)Lock (2)Unlock (3)Lock-tight

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

Power-On Auto-Read

The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.

An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of

auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state. Serial access may be done

after power-on without latency. Power-On Auto Read mode is available only on 3.3V device(K9K12XXU0C).

Figure 16. Power-On Auto-Read (3.3V device only)

VCC

CLE

I/OX

ALE

1st

~ 1.8V

LOCKPRE

R/B

2nd 3rd .... n th

≈ ≈ ≈ ≈ ≈ ≈≈

≈≈

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-

ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is

an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be

determined by the following guidance.

VCC

R/B

open drain output

Device

GND

Figure 17. Rp vs tr ,tf & Rp vs ibusy

ibusy

Busy

Ready Vcc

VOH

tf tr

VOL

1.8V device - VOL : 0.1V, VOH : VccQ-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

2.65V device - VOL : 0.4V, VOH : VccQ-0.4V

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

tr,tf [s]

Ibusy [A]

Rp(ohm)

Ibusy

@ Vcc = 3.3V, Ta = 25°C , CL = 100pF

1K 2K 3K 4K

100n

200n

300n 3m

100

200

300

400

3.6 3.6 3.6 3.6

2.4

1.2

0.8

0.6

Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.)

IOL + ΣIL = 1.85V

3mA + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)

IOL + ΣIL = 3.2V

8mA + ΣIL

tr,tf [s]

Ibusy [A]

Rp(ohm)

Ibusy

@ Vcc = 1.8V, Ta = 25°C , CL = 30pF

1K 2K 3K 4K

100n

200n

300n 3m

60 90 120

1.7 1.7 1.7 1.7

1.7

0.85

0.57 0.43

Rp(min, 2.65V part) = VCC(Max.) - VOL(Max.)

IOL + ΣIL = 2.5V

3mA + ΣIL

tr,tf [s]

Ibusy [A]

Rp(ohm)

Ibusy

@ Vcc = 2.65V, Ta = 25°C , CL = 30pF

1K 2K 3K 4K

100n

200n

300n 3m

60 90 120

2.3 2.3 2.3 2.3

2.3

1.1

0.75 0.55

FLASH MEMORY

K9K1216D0C

K9K1216U0C

K9K1208D0C

K9K1208U0C

K9K1208Q0C K9K1216Q0C

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard-

ware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is

required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for

program/erase provides additional software protection.

Figure 18. AC Waveforms for Power Transition

VCC

High

≈

1.8V device : ~ 1.5V

Data Protection & Power up sequence

3.3V device : ~ 2.5V

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

10µs

≈≈

2.65V device : ~ 2.0V 2.65V device : ~ 2.0V