MX29LA640E H/L 64M-BIT [4M x 16/8M x 8] CMOS EQUAL SECTOR FLASH MEMORY FEATURES GENERAL FEATURES * 8M Bytes/4M Words switchable * 128 Equal Sectors with 64K Bytes (32K words) each - Any combination of sectors can be erased with erase suspend/resume function * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1.0V to 1.5 x Vcc * Low Vcc write inhibit is equal to or less than VLKO * Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE * High Performance - Access time: 70ns - Program time: 11us/word - Erase time: 0.7s/sector, 45s/chip (typical) * Low Power Consumption - Low active read current: 9mA (typical) at 5MHz - Low standby current: 5uA(typical) * 100,000 erase/program cycles (typical) * 10 years data retention SOFTWARE FEATURES * Support Common Flash Interface (CFI) - Flash device parameters stored on the device and provide the host system to access * Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased * Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion or not HARDWARE FEATURES * Ready/Busy (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion * Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode * ACC input pin - Provides accelerated program capability * WP#/ACC input - Write protect (WP#) function allows protection all sectors, regardless of sector protection settings SECURITY * Sector Protection/Chip Unprotect - Provides sector protect function to prevent program or erase operation in the protected sector - Provides chip unprotect function to allow code changes - Provides temporary sector unprotect function for code changes in previously protected sector P/N:PM1424 REV. 1.3, MAY 19, 2010 1 MX29LA640E H/L * Sector Permanent Lock - A unique lock bit feature allows the content to be permanently locked (Please contact Macronix sales for specific information regarding this permanent lock feature) * Secured Silicon Sector - Provides a 128-word area for code or data that can be permanently protected - Once this sector is protected, it is prohibited to program or erase within the sector again PACKAGE * 64-ball FBGA * All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX29LA640E H/L is a 64Mbit flash memory that can be organized as 8Mbytes of 8 bits each or as 4Mbytes of 16 bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 128 equal 64 Kilo byte blocks. The MX29LA640E H/L is offered in a 64-ball BGA(FBGA) JEDEC standard package. The package is offered in leaded, as well as lead-free version that is compliant to the RoHS specifications. The software algorithm used for this device also adheres to the JEDEC standard for single power supply devices. These flash parts can be programmed in system or on commercially available EPROM/Flash programmers. Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When used with high speed processors, the 70ns read access time of this flash memory permits operation with minimal time lost due to system timing delays. The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write. The user only needs to provide a write command to the command register. The on-chip state machine automatically controls the program and erase functions including all necessary internal timings. Since erase and write operations take much longer time than read operations, erase/write can be interrupted to perform read operations in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation. The device is manufactured at the Macronix fabrication facility using the time tested and proven Macronix advanced technology. This proprietary non-epi process provides a very high degree of latch-up protection for stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC. With low power consumption and enhanced hardware and software features, this flash memory retains data reliably for at least ten years. Erase and programming functions have been tested to meet a typical specification of 100,000 cycles of operation. P/N:PM1424 REV. 1.3, MAY 19, 2010 2 MX29LA640E H/L PIN CONFIGURATION 64 BGA 8 NC NC NC VI/O GND NC NC NC 7 A13 A12 A14 A15 A16 BYTE# Q15/ A-1 GND 6 A9 A8 A10 A11 Q7 Q14 Q13 Q6 5 WE# RESET# A21 A19 Q5 Q12 VCC Q4 4 RY/ BY# WP#/ ACC A18 A20 Q2 Q10 Q11 Q3 3 A7 A17 A6 A5 Q0 Q8 Q9 Q1 2 A3 A4 A2 A1 A0 CE# OE# GND 1 NC NC NC NC NC VI/O NC NC C D E F G H A B PIN DESCRIPTION LOGIC SYMBOL SYMBOL PIN NAME A0~A21/A-1 Address Input/LSB addr (Byte Mode) Q0~Q15 CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# 22 Data Inputs/Outputs A0-A21 (A-1) CE# Hardware Reset Pin, Active Low OE# Hardware Write Protect/Programming WP#/ACC Acceleration input RY/BY# Read/Busy Output BYTE# VCC V I/O GND NC 16 Q0-Q15 WE# RESET# Selects 8 bits or 16 bits mode WP#/ACC +3.0V single power supply V I/O Output Power Supply (2.7V~3.6V), which is tied to VCC Device Ground RY/BY# Pin Not Connected Internally P/N:PM1424 REV. 1.3, MAY 19, 2010 3 MX29LA640E H/L BLOCK DIAGRAM VCC GND CE# OE# WE# RESET# WP# ACC CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER Y-DECODER AND STATE X-DECODER ADDRESS A0-A21 (A-1) WRITE FLASH REGISTER ARRAY ARRAY Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER V I/O P/N:PM1424 REV. 1.3, MAY 19, 2010 4 MX29LA640E H/L Table 1. BLOCK STRUCTURE MX29LA640E SECTOR ARCHITECTURE Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 Sector Address A21-A15 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh P/N:PM1424 (x16) Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh REV. 1.3, MAY 19, 2010 5 MX29LA640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 Sector Address A21-A15 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 (x8) Address Range 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh P/N:PM1424 (x16) Address Range 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh REV. 1.3, MAY 19, 2010 6 MX29LA640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Address A21-A15 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 (x8) Address Range 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh P/N:PM1424 (x16) Address Range 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh REV. 1.3, MAY 19, 2010 7 MX29LA640E H/L Table 2-1. BUS OPERATION Byte# RESET# CE# WE# OE# Address Data I/O Q0~Q7 L Vcc 0.3V H X Vcc 0.3V L X X X HighZ Vil Vih Data (I/O) Q8~Q15 HighZ HighZ X X X HighZ HighZ HighZ H H H X HighZ HighZ HighZ L/H Read Mode H L H L AIN DOUT DOUT L/H Write (Note1) H L L H AIN DIN DIN H Accelerate Program H L L H AIN DIN DIN Vhv Temporary Sector-Group Unprotect Vhv X X X AIN DIN HighZ DIN H Sector-Group Protect (Note2) Vhv L L H Sector Address, DIN, A6=L, A1=H, A0=L DOUT X X H Chip Unprotect (Note2) Vhv L L H Sector Address, DIN, A6=L, A1=H, A0=L DOUT X X H Mode Select Device Reset Standby Mode Output Disable Q8-Q14= HighZ, Q15=A1 WP#/ ACC L/H Notes: 1. All sectors will be unprotected if WP#/ACC=Vhv. 2. All sectors are protected if WP#/ACC=Vil. 3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm. 4. In Word Mode (Byte#=Vih), the addresses are AM to A0. In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15). 5. AM: MSB of address. P/N:PM1424 REV. 1.3, MAY 19, 2010 8 MX29LA640E H/L Table 2-2. BUS OPERATION Item A21 A14 to to A9 WE# A15 A10 Control Input A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 Q8 to Q15 Q7 to Q0 CE# OE# enable L H SA X Vhv X L X X H L X Note 1 enable L H X X Vhv X L X X H H X Note 2 enable L H X X Vhv X L X L L L 00 C2h Cycle 1 enable L H X X Vhv X L X L L H 22 7Eh Cycle 2 enable L H X X Vhv X L X H H L 22 13h 640EH enable L H X X Vhv X L X H H H 22 01h 640EL enable L H X X Vhv X L X H H H 22 00h Sector Lock Status Verification Read Indicator Bit (Q7) for Security Sector Manufacturer ID Device ID Cycle 3 Legend: L=Logic Low=Vil, H=Logic High=Vih, SA=Sector Address, X=Don't care, Vhv=10.00.5V. Notes: 1. Sector unprotected code: 00h, sector protected code:01h. 2. Factory locked code: For 29LA640EL: 88h. For 29LA640EH: 98h. Factory unlocked code: For 29LA640EL: 08h. For 29LA640EH: 18h. P/N:PM1424 REV. 1.3, MAY 19, 2010 9 MX29LA640E H/L WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. ACCELERATED PROGRAM OPERATION The accelerated program can improve programming performance compared with word/byte program. By applying Vhv on WP#/ACC pin, the device will enter accelerated program and draw current no more than IACC from WP#/ACC pin. Removing the Vhv from WP#/ACC pin will put the device back to normal operation (not accelerated). P/N:PM1424 REV. 1.3, MAY 19, 2010 10 MX29LA640E H/L RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read the boot-up firware from flash memory. SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29LA640E H/L provides two methods for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for the algorithm for this method. The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. CHIP UNPROTECT OPERATION MX29LA640E H/L provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors are unprotected when shipped from the factory. The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for algorithm of the operation. The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. P/N:PM1424 REV. 1.3, MAY 19, 2010 11 MX29LA640E H/L WRITE PROTECT (WP#) This Write Protect function provides a hardware protection method to protect all sectors without using Vhv. By driving the WP#/ACC pin Low, the device disable program and erase function in all sectors. If the WP#/ACC is held high (Vih to Vcc), these sectors revert to their previous protected/unprotected status. AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. MX29LA640E H/L provide hardware method to access the silicon ID read operation. Which method requires Vhv on A9 pin, Vil on CE#, OE# and A6 pins. Which apply A1=Vil, A0=Vil, the device will output MXIC's manufacture code of C2h. Which apply A1=Vil, A0=Vih, the device will output device code of 227Eh. Table 2 shows the sequence for reading MX29LA640E H/L device codes. VERIFY SECTOR PROTECT STATUS OPERATION MX29LA640E H/L provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A15 to A21 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected. SECURITY SECTOR FLASH MEMORY REGION The Security Sector region is an extra OTP memory space of 128 words in length. The security sectors can be locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. In factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". Factory Locked: Security Sector Programmed and Protected at the Factory In a factory locked device, the security silicon region is permanently locked after shipping from factory. The device will have a 16-byte (8-word) ESN in the security region at address : 000000h - 000007h. The secured silicon sector address space in this device is allocated as follows. Secured Silicon Sector Express Flash Standard Factory Locked Address Range Factory Locked ESN or Determined by 000000h-000007h ESN Customer 000008h-00007Fh Unavailable Determined by Customer P/N:PM1424 Customer Lockable Determined by Customer REV. 1.3, MAY 19, 2010 12 MX29LA640E H/L Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. The first method is to write a three-cycle command of Enter Security Region, and then follow the sector protect algorithm as illustrated in Figure 15, except that RESET# pin may at either Vih or Vhv. The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate method of sector protect with A9, OE# at Vhv. After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until Vcc is greater than VLKO. System must provide proper signals on control pins after Vcc is larger than VLKO to avoid unintentional program or erase operation WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29LA640E H/L is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. P/N:PM1424 REV. 1.3, MAY 19, 2010 13 MX29LA640E H/L POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1424 REV. 1.3, MAY 19, 2010 14 MX29LA640E H/L TABLE 3. MX29LA640E H/L COMMAND DEFINITIONS 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Word 555 AA 2AA 55 555 90 Byte AAA AA 555 55 AAA 90 4th Bus Cycle Addr X00 X00 X01 X02 X03 X06 Data C2h C2h ID1 ID1 98/18(T) 88/08(B) 98/18(T) 88/08(B) 5th Bus Cycle 6th Bus Cycle X0E ID2 X0F ID3 X1C ID2 X1E ID3 Addr Data Addr Data Addr Data Reset Mode Addr Data XXX F0 Automatic Select Security Sector Factory Protect Verify Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 Device ID (*Notes) Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 Command Read Mode Manufacturer ID Addr Data Addr Data Enter Security Sector Region Enable Word Byte Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data 6th Bus Cycle Addr 555 AA 2AA 55 555 88 AAA AA 555 55 AAA 88 Data Device ID Interface MX29LA640EH MX29LA640EL Word 227E 227E ID1 Sector Protect Verify Word 555 AA 2AA 55 555 90 (Sector) X02 Byte AAA AA 555 55 AAA 90 (Sector) X04 00/01 00/01 Exit Sector Erase Erase CFI Read Security Program Chip Erase Erase Suspend Resume Sector Word Byte Word Byte Word Byte Word Byte Word Byte Byte/Word Byte/Word 555 AAA 555 AAA 555 AAA 555 AAA AA AA AA AA AA AA AA AA 2AA 555 2AA 555 2AA 555 2AA 555 55 55 55 55 55 55 55 55 555 AAA 555 AAA 555 AAA 555 AAA 90 90 A0 A0 80 80 80 80 XXX XXX Addr Addr 555 AAA 555 AAA 00 00 Data Data AA AA AA AA 2AA 555 2AA 555 55 55 55 55 Sec- Sec555 AAA tor tor 10 10 30 30 Byte 7E 7E Word 2213 2213 ID2 Byte 13 13 P/N:PM1424 Word 2201 2200 ID3 55 98 AA 98 XXX B0 XXX 30 Byte 01 00 REV. 1.3, MAY 19, 2010 15 MX29LA640E H/L RESET In the following situations, executing reset command will reset device back to read array mode: * Among erase command sequence (before the full command set is completed) * Sector erase time-out period * Erase fail (while Q5 is high) * Among program command sequence (before the full command set is completed, erase-suspended program included) * Program fail (while Q5 is high, and erase-suspended program fail is included) * Read silicon ID mode * Sector protect verify * CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Identifier Code Manufacturer ID Device ID, cycle 1 Device ID, cycle 2 Device ID, cycle 3 Secured Silicon Sector Protect Verify Word/Byte Mode Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Address X00 X00 X01 X02 X0E X1C X0F X1E X03 X06 (Sector address) X 02 (Sector address) X 04 Data (Hex) C2 C2 227E 7E 2213 13 2201/2200 01/00 98/18 (H) 98/18 (H) 00/01 00/01 Representation 29LA640E H/L Factory locked/unlocked Factory locked/unlocked Unprotected/protected Unprotected/protected There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1424 REV. 1.3, MAY 19, 2010 16 MX29LA640E H/L AUTOMATIC PROGRAMMING The MX29LA640E H/L can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LA640E H/L is less than 45 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress *1 Finished Exceed time limit Q7 Q7# Q7 Q7# Q6 Toggling Stop toggling Toggling Q5 0 0 1 RY/BY# *2 0 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector. P/N:PM1424 REV. 1.3, MAY 19, 2010 17 MX29LA640E H/L CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress Finished Exceed time limit Q7 0 1 0 Q6 Toggling Stop toggling Toggling Q5 0 0 1 Q2 Toggling 1 Toggling RY/BY# 0 1 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Time-out period In progress Finished Exceeded time limit Q7 0 0 1 0 Q6 Toggling Toggling Stop toggling Toggling Q5 0 0 0 1 Q3 0 1 1 1 Q2 Toggling Toggling 1 Toggling RY/BY#*2 0 0 1 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. P/N:PM1424 REV. 1.3, MAY 19, 2010 18 MX29LA640E H/L SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A toggle 1 Erase suspend read in non-erase suspended sector Data Data Data Data Data 1 Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A 0 Erase suspend read in erase suspended sector When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 4ms interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1424 REV. 1.3, MAY 19, 2010 19 MX29LA640E H/L QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LA640E H/L features CFI mode. Host system can retrieve the operating characteristics, structure and vendor-specified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the system writes the CFI Query command "98H" to address "55H" any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. A reset command is required to exit CFI mode and go back to ready array mode or erase suspend mode. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code Address for alternate algorithm extended query table Address (h) (Word Mode) 10 11 12 13 14 15 16 17 18 19 1A Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 Address (h) (Word Mode) 1B 1C 1D 1E 1F Address (h) (Byte Mode) 36 38 3A 3C 3E 20 40 0000 21 22 23 24 25 42 44 46 48 4A 000A 0000 0005 0000 0004 26 4C 0000 Data (h) 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI Mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us (00h, not support) Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms (00h, not support) Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical (00h, not support) P/N:PM1424 Data (h) 0027 0036 0000 0000 0004 REV. 1.3, MAY 19, 2010 20 MX29LA640E H/L Table 4-3. CFI Mode: Device Geometry Data Values Description Device size = 2n in number of bytes Flash device interface description (02=asynchronous x8/x16) Maximum number of bytes in buffer write = 2n (not support) Number of erase regions within device Index for Erase Bank Area 1: [2E,2D] = # of same-size sectors in region 1-1 [30, 2F] = sector size in multiples of 256K-bytes Index for Erase Bank Area 2 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1424 Address (h) (Word Mode) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C Address (h) (Byte Mode) 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Data (h) 0017 0002 0000 0000 0000 0001 007F 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 REV. 1.3, MAY 19, 2010 21 MX29LA640E H/L Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Address (h) (Word Mode) 40 41 42 43 44 45 46 47 48 49 4A 4B Address (h) (Byte Mode) 80 82 84 86 88 8A 8C 8E 90 92 94 96 4C 98 0000 Minimum ACC(acceleration) supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV 4D 9A 0095 Maximum ACC(acceleration) supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV 4E 9C 00A5 WP# Protection 04=Uniform sectors bottom WP# protect 05=Uniform sectors top WP# protect 4F 9E 0004/ 0005 Description Query - Primary extended table, unique ASCII string, PRI Major version number, ASCII Minor version number, ASCII Unlock recognizes address (0= recognize, 1= don't recognize) Erase suspend (2= to both read and program) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode (0=not supported) Page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) P/N:PM1424 Data (h) 0050 0052 0049 0031 0033 0000 0002 0001 0001 0004 0000 0000 REV. 1.3, MAY 19, 2010 22 MX29LA640E H/L ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias Storage Temperature Voltage Range VCC RESET#, A9, ACC and OE# The other pins. Output Short Circuit Current (less than one second) -65oC to +125oC -65oC to +150oC -0.5V to +4.0 V -0.5V to +10.5 V -0.5V to Vcc +0.5V 200 mA Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions. OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ) Industrial (I) Grade Surrounding Temperature VCC Supply Voltages VCC range (TA ) 0C to +70C -40C to +85C +2.7 V to 3.6 V P/N:PM1424 REV. 1.3, MAY 19, 2010 23 MX29LA640E H/L DC CHARACTERISTICS Symbol Description Min Typ Max Remark Iilk Input Leak Iilk9 A9 Leak Iolk Output Leak Icr1 Icr2 Read Current (5MHz) Read Current (1MHz) 9mA 2mA 16mA 4mA Icw Write Current 26mA 30mA Isb Standby Current 5uA 15uA Isbr Reset Current 5uA 15uA Isbs Sleep Mode Current 5uA 15uA 5mA 10mA CE#=Vil, OE#=Vih 15mA 30mA CE#=Vil, OE#=Vih Icp1 Icp2 Vil Vih Vhv Vol Accelerated Pgm Current, WP#/Acc pin(Word/Byte) Accelerated Pgm Current, Vcc pin, (Word/Byte) Input Low Voltage Input High Voltage Very High Voltage for hardware Protect/ Unprotect/Auto Select/Temporary Unprotect/Accelerated Program Output Low Voltage 2.0uA 35uA A9=10.5V 1.0uA -0.5V 0.7xVcc 0.8V Vcc+0.3V 9.5V 10.5V 0.45V CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih, WE#=Vil Vcc=Vcc max, other pin disable Vcc=Vccmax, RESET# enable, other pin disable Iol=4.0mA Voh1 Ouput High Voltage 0.85xVI/O Ioh1=-2mA Voh2 Ouput High Voltage VI/O-0.4V Ioh2=-100uA Vlko Low Vcc Lock-out voltage 2.3V P/N:PM1424 2.5V REV. 1.3, MAY 19, 2010 24 MX29LA640E H/L SWITCHING TEST CIRCUITS Vcc R2 TESTED DEVICE 0.1uF CL R1 +3.3V DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF Rise/Fall Times : 5ns In/Out reference levels :1.5V Input Pulse level : 0.0 ~ 3.0V SWITCHING TEST WAVEFORMS 3.0V 1.5V 1.5V Test Points 0.0V INPUT OUTPUT P/N:PM1424 REV. 1.3, MAY 19, 2010 25 MX29LA640E H/L AC CHARACTERISTICS Symbol Description 0 Trc Twc Tcwc Tas Tah Tds Tdh Tvcs Tcs Tch Toes Valid data output after address Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high Output hold time from the earliest rising edge of address,CE#, OE# Read period time Write period time Command write period time Address setup time Address hold time Data setup time Data hold time Vcc setup time Chip enable Setup time Chip enable hold time Output enable setup time Unit ns ns ns ns ns 70 70 70 0 45 45 0 100 0 0 0 ns ns ns ns ns ns ns us ns ns ns Toeh Output enable hold time Read Toggle & Data# Polling 0 10 ns ns Tws WE# setup time 0 ns WE# hold time CE# pulse width CE# pulse width high WE# pulse width WE# pulse width high 0 45 30 35 30 ns ns ns ns ns ns ns ns us us us sec us Taa Tce Toe Tdf Toh Twh Tcep Tceph Twp Twph Min Max 70 70 30 30 70 Tbusy Program/Erase active time by RY/BY# Tghwl Read recover time before write Tghel Read recover time before write Twhwh1 Program operation Typ 0 0 Byte Word Twhwh1 Acc program operation(Word/Byte) Twhwh2 Sector erase operation Tbal Sector add hold time 9 11 7 0.7 50 P/N:PM1424 REV. 1.3, MAY 19, 2010 26 MX29LA640E H/L Figure 1. COMMAND WRITE OPERATION Tcwc CE# Disable Enable Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Data Vih Vil DIN VA: Valid Address P/N:PM1424 REV. 1.3, MAY 19, 2010 27 MX29LA640E H/L READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS CE# Tce Vih Vil Tsrw Vih WE# OE# Vil Toeh Tdf Toe Vih Vil Toh Taa Trc Vih Addresses Outputs ADD Valid Vil Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1424 REV. 1.3, MAY 19, 2010 28 MX29LA640E H/L AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 50 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write MAX 20 us Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1424 REV. 1.3, MAY 19, 2010 29 MX29LA640E H/L ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM Disable CE# Enable Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address 2AAh VA SA Tds Data Read Status Tah Tas Tdh 55h VA In Progress Complete 10h Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1424 REV. 1.3, MAY 19, 2010 30 MX29LA640E H/L Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1424 REV. 1.3, MAY 19, 2010 31 MX29LA640E H/L Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status Disable CE# Enable Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Data Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h Tbusy 30h Trb RY/BY# P/N:PM1424 REV. 1.3, MAY 19, 2010 32 MX29LA640E H/L Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1424 REV. 1.3, MAY 19, 2010 33 MX29LA640E H/L Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 NO ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1424 REV. 1.3, MAY 19, 2010 34 MX29LA640E H/L Figure 9. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us No Data = 01h ? Yes Device Failed Write Reset Command Secured Sector Protect Complete P/N:PM1424 REV. 1.3, MAY 19, 2010 35 MX29LA640E H/L Figure 10. AUTOMATIC PROGRAM TIMING WAVEFORMS Disable CE# Enable Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle 555h Address Last 2 Read Status Cycle Tah Tas VA PA Tds Tdh A0h Data VA Status PD DOUT Tbusy Trb RY/BY# Figure 11. Accelerated Program Timing Diagram Vhv (9.5V ~ 10.5V) WP#/ACC Vil or Vih Vil or Vih 250ns 250ns P/N:PM1424 REV. 1.3, MAY 19, 2010 36 MX29LA640E H/L Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1424 REV. 1.3, MAY 19, 2010 37 MX29LA640E H/L Figure 13. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Twhwh1 or Twhwh2 Tcep Disable CE# Enable Tceph Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h Status PD DOUT Tbusy RY/BY# P/N:PM1424 REV. 1.3, MAY 19, 2010 38 MX29LA640E H/L SECTOR PROTECT/CHIP UNPROTECT Figure 14. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 150us: Sector Protect 15ms: Chip Unprotect 1us CE# Disable Enable WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv RESET# Vih VA: valid address P/N:PM1424 REV. 1.3, MAY 19, 2010 39 MX29LA640E H/L Figure 15-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Set Up Sector Address Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No Retry Count=25? Yes No Data=01h? Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1424 REV. 1.3, MAY 19, 2010 40 MX29LA640E H/L Figure 15-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No Retry Count=1000? Yes Device fail No Data=00h? Yes Last sector verified? No Yes Temporary Unprotect RESET#=Vih Write reset CMD Chip Unprotect Done P/N:PM1424 REV. 1.3, MAY 19, 2010 41 MX29LA640E H/L AC CHARACTERISTICS Parameter Tvlht Twpp1 Twpp2 Toesp Description Voltage transition time Write pulse width for sector protect Write pulse width for chip unprotect OE# setup time to WE# active Test Setup Min. Min. Min. Min. All Speed Options 4 100 100 4 Unit us ns ns us Figure 16. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control) A1 A6 10V 3V A9 10V 3V Tvlht Verify OE# Tvlht Tvlht Twpp1 WE# CE# Disable Toesp Enable Data 01H F0H Toe A21-A15 Sector Address P/N:PM1424 REV. 1.3, MAY 19, 2010 42 MX29LA640E H/L Figure 17. SECTOR PROTECTION ALGORITHM (A9, OE# Control) START Set Up Sector Addr PLSCNT=1 OE#=Vhv, A9=Vhv, CE#=Vil A6=Vil Activate WE# Pulse Time Out 150us Set WE#=Vih, CE#=OE#=Vil A9 should remain Vhv Read from Sector Addr=SA, A1=1 No PLSCNT=32? No Data=01H? Yes Device Failed Protect Another Sector? Yes Remove Vhv from A9 Write Reset Command Sector Protection Complete P/N:PM1424 REV. 1.3, MAY 19, 2010 43 MX29LA640E H/L Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control) A1 10V 3V A9 Tvlht A6 10V 3V Verify OE# Tvlht Tvlht Twpp2 WE# CE# Disable Toesp Enable Data 00H F0H Toe P/N:PM1424 REV. 1.3, MAY 19, 2010 44 MX29LA640E H/L Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control) START Protect All Sectors PLSCNT=1 Set OE#=A9=Vhv CE#=Vil, A6=1 Activate WE# Pulse Time Out 15ms Increment PLSCNT Set OE#=CE#=Vil A9=Vhv, A1=1 Set Up First Sector Addr Read Data from Device Data=00H? Increment Sector Addr Yes No All sectors have been verified? No No PLSCNT=1000? Yes Device Failed Yes Remove Vhv from A9 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1424 REV. 1.3, MAY 19, 2010 45 MX29LA640E H/L AC CHARACTERISTICS Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 20. TEMPORARY SECTOR UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# Disable Enable WE# Tvhhwl RY/BY# Vhv 10V RESET# 0 or Vih Vil or Vih Trpvhh Trpvhh P/N:PM1424 REV. 1.3, MAY 19, 2010 46 MX29LA640E H/L Figure 21. TEMPORARY SECTOR UNPROTECT FLOWCHART Start Apply Reset# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from Reset# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=9.5~10.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected. P/N:PM1424 REV. 1.3, MAY 19, 2010 47 MX29LA640E H/L Figure 22. SILICON ID READ TIMING WAVEFORM VCC 3V Vhv Vih Vil ADD A9 ADD A0 Vih Vil Taa A1 Taa Taa Taa Vih Vil A2 Vih Vil ADD CE# WE# Vih Vil Disable Enable Tce Vih Vil OE# Vih Toe Tdf Vil Toh DATA Q0-Q15 Toh Toh Toh Vih Vil DATA OUT DATA OUT DATA OUT DATA OUT Manufacturer ID Device ID Cycle 1 Device ID Cycle 2 Device ID Cycle 3 P/N:PM1424 REV. 1.3, MAY 19, 2010 48 MX29LA640E H/L WRITE OPERATION STATUS Figure 23. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Disable Enable Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Status Data Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1424 REV. 1.3, MAY 19, 2010 49 MX29LA640E H/L Figure 24. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) No Q7 = Data# ? Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address No Q7 = Data# ? (Note 2) Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1424 REV. 1.3, MAY 19, 2010 50 MX29LA640E H/L Figure 25. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Disable Enable Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# VA : Valid Address P/N:PM1424 REV. 1.3, MAY 19, 2010 51 MX29LA640E H/L Figure 26. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice Q6 Toggle ? (Note 1) NO YES NO Q5 = 1? YES Read Q7~Q0 Twice Q6 Toggle ? NO YES PGM/ERS fail Write Reset CMD PGM/ERS Complete Note: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1424 REV. 1.3, MAY 19, 2010 52 MX29LA640E H/L Figure 27. Q6 versus Q2 Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase Erase Complete Q6 Q2 NOTES: The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended. P/N:PM1424 REV. 1.3, MAY 19, 2010 53 MX29LA640E H/L RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly. Vcc Vcc(min) GND Tvr Tvcs Tf CE# WE# Tce Disable Enable Vih Vil Tf OE# WP#/ACC Tr Vil Taa Vih Tr or Tf Valid Address Vil Voh DATA Toe Vih Tr or Tf ADDRESS Tr High Z Valid Ouput Vol Vih Vil Figure A. AC Timing at Device Power-Up Symbol Parameter Min. Max. Unit 80 500000 us/V Tvr Vcc Rise Time Tr Input Signal Rise Time 20 us/V Tf Input Signal Fall Time 20 us/V Tvcs Vcc Setup Time 200 P/N:PM1424 us REV. 1.3, MAY 19, 2010 54 MX29LA640E H/L ERASE AND PROGRAMMING PERFORMANCE PARAMETER MIN. Sector Erase Time Chip Erase Time Word Programming Time Byte Programming Time Accelerated Byte/Word Program Time Byte mode Word mode Chip Programming Time Erase/Program Cycles LIMITS TYP. (1) 0.7 45 11 9 7 50 45 100,000 MAX. (2) 2 65 360 300 210 160 140 UNITS sec sec us us us sec sec Cycles Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0V VCC. Programming specifications assume checkboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. Erase/Program cycles comply with JEDEC JESD-47 & A117 standard. DATA RETENTION PARAMETER Condition Min. Data retention 55C 10 Max. UNIT years LATCH-UP CHARACTERISTICS MIN. -1.0V -1.0V -100mA Input Voltage voltage difference with GND on WP#/ACC, A9, OE, Reset# pins Input Voltage voltage difference with GND on all normal pins input Vcc Current All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing MAX. 10.5V Vcc x 1.5Vcc +100mA PIN CAPACITANCE Parameter Symbol CIN2 COUT CIN Parameter Description Control Pin Capacitance Output Capacitance Input Capacitance Test Set VIN=0 VOUT=0 VIN=0 TYP. 7.5 8.5 6 MAX. 9 12 7.5 UNIT pF pF pF Notes: 1. Test conditions TA=25C, f=1.0MHz. P/N:PM1424 REV. 1.3, MAY 19, 2010 55 MX29LA640E H/L ORDERING INFORMATION ACCESS TIME Ball Pitch / (ns) Ball Size MX29LA640EHXCI-70G 70 MX29LA640ELXCI-70G 70 PART NO. PACKAGE Remark 1.0mm/0.4mm 64 BGA Pb-free 1.0mm/0.4mm 64 BGA Pb-free P/N:PM1424 REV. 1.3, MAY 19, 2010 56 MX29LA640E H/L PART NAME DESCRIPTION MX 29 LA 640 E H XC I 70 G OPTION: G: Lead-free package SPEED: 70: 70ns TEMPERATURE RANGE: I: Industrial (-40 C to 85 C) PACKAGE: X: FBGA (CSP) XC - 1.0mm Ball PRODUCT TYPE: H: Highest Address Sector L: Lowest Address Sector REVISION: E DENSITY & MODE: 640: 64M (x8/x16) Equal Sector TYPE: LA: 3V Security DEVICE: 29:Flash P/N:PM1424 REV. 1.3, MAY 19, 2010 57 MX29LA640E H/L PACKAGE INFORMATION P/N:PM1424 REV. 1.3, MAY 19, 2010 58 MX29LA640E H/L REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" 2. Revised CFI data - Sector protect (N=# of sectors/group), data from 0004 to 0001 1.1 1. Correct typo error 1.2 1. Added condition of data retention 1.3 1. Added 64-FBGA information on package pin configuration, ordering and part name 2. Modified notes 4 P/N:PM1424 Page P1 P22 Date DEC/19/2008 P1,2 P55 P3,56,57 FEB/25/2009 MAY/04/2009 MAY/19/2010 P55 REV. 1.3, MAY 19, 2010 59 MX29LA640E H/L Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. Copyright(c) Macronix International Co., Ltd. 2008~2010. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo, are trademarks or registered trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix's Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 60