CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D
TTL-Compatible Inputs and
CMOS-Compatible Outputs
D
Distributes One Clock Input to Six Clock
Outputs
D
Polarity Control Selects True or
Complementary Outputs
D
Distributed VCC and GND Pins Reduce
Switching Noise
D
High-Drive Outputs (–32-mA IOH,
32-mA IOL)
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (D)
description
The CDC329A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and
complementary outputs can be obtained.
The CDC329A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS OUTPUT
T/C A Y
L L L
LHH
HLH
HHL
logic symbol†
12
A
N1
15
N2
13
1Y1
16
1
1Y2
2
1
2Y1
3
2
N3
10
N4
9
2Y2
5
2
3Y
6
3
4Y
8
4
1T/C
2T/C
3T/C
4T/C
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
1Y2
2Y1
GND
2Y2
3Y
GND
4Y
1Y1
1T/C
VCC
2T/C
A
VCC
3T/C
4T/C
CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1Y1
1Y2
2Y1
2Y2
3Y
4Y
16
2
3
5
6
8
15
13
12
10
9
1T/C
A
2T/C
3T/C
4T/C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 0.77 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS Technology
Data Book
, literature number SCBD002B.
CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 VCC V
IOH High-level output current –32 mA
IOL Low-level output current 32 mA
∆t/∆vInput transition rise or fall rate 5 ns/V
fclock Input clock frequency 80 MHz
TAOperating free-air temperature –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –1.2 V
VOH VCC = 4.75 V, IOH = – 32 mA 3.85 V
VOL VCC = 4.75 V, IOL = 32 mA 0.55 V
IIVCC = 5.25 V, VI = VCC or GND ±1µA
ICC
VCC = 5 25 V
VI=V
CC or GND IO=0
Outputs high 10
mA
I
CC
V
CC =
5
.
25
V
,
V
I =
V
CC
or
GND
,
I
O =
0
,Outputs low 40
mA
CiVI = 2.5 V or 0.5 V 3 pF
†All typical values are at VCC = 5 V, TA = 25°C
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN TYP MAX UNIT
tPLH
A
Any Y
25.9
ns
tPHL
A
An
y
Y
1.7 5.9
ns
tPLH
T/C
Any Y
1.5 5
ns
tPHL
T/C
An
y
Y
1.5 5
ns
tk( )
A
Any Y (same phase) 0.6
ns
t
sk(o)
A
Any Y (any phase) 1.5
ns
tr1.3 ns
tf0.85 ns
CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
500 Ω
tPLH tPHL
1.5 V 1.5 V 3 V
0 V
70% 70% VOH
VOL
30% 30%
tf
tr
Input
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output 50% VCC
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPLH1
2Y2
2Y1
2T/C
1Y2
1Y1
1T/C
A
tPHL1 tPLH5 tPHL5
tPLH2 tPHL2 tPLH6 tPHL6
tPLH3 tPHL3 tPHL7 tPLH7
tPLH4 tPHL4 tPHL8 tPLH8
NOTES: A. Output skew , tsk(o), from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control
inputs (T/C) are at the same logic level. It is calculated as the greater of:
– The difference between the fastest and slowest of tPHL from A↓ to any Y (e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6)
– The difference between the fastest and slowest of tPHL from A↓ to any Y (e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6)
– The difference between the fastest and slowest of tPLH from A↓ to any Y (e.g., tPLHn, n = 7 to 8)
– The difference between the fastest and slowest of tPHL from A↑ to any Y (e.g., tPHLn, n = 7 to 8)
B. Output skew , tsk(o), from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs
(T/C) are at the same or different logic levels. It is calculated as the greater of:
– The difference between the fastest and slowest of tPLH from A↑ to any Y or tPHL from A↑ to any Y (e.g., tPLHn, n = 1 to 4;
or tPLHn, n = 5 to 6, and tPHLn, n = 7 to 8)
– The difference between the fastest and slowest of tPHL from A↓ to any Y or tPLH from A↓ to any Y (e.g., tPHLn, n = 1 to 4;
or tPHLn, n = 5 to 6, and tPLHn, n = 7 to 8)
Figure 2. Waveforms for Calculation of tsk(o)
CDC329A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS328B – DECEMBER 1992 – REVISED OCT OBER 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDC329AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC329ADBLE OBSOLETE SSOP DB 16 TBD Call TI Call TI
CDC329ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC329ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC329ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Nov-2005
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CDC329ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDC329ADR SOIC D 16 2500 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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