SAR Control
DOUT
Comparator
S/H Amp CS/SHDN
DCLOCK
+In
VREF
–In CDAC Serial
Interface
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
10/8/12-BIT HIGH SPEED 2.7 V microPOWER™ SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES DESCRIPTION
•High Throughput at Low Supply Voltage The ADS7826/27/29 is a family of 10/8/12-bit sampling
(2.7 V VCC)analog-to-digital converters (A/D) with assured specifi-
– ADS7829: 12-bit 125 KSPS cations at 2.7-V supply voltage. It requires very little
– ADS7826: 10-bit 200 KSPS power even when operating at the full sample rate. At
– ADS7827: 8-bit 250 KSPS lower conversion rates, the high speed of the device
enables it to spend most of its time in the power down
•Very Wide Operating Supply VoltageL: mode— the power dissipation is less than 60 µW at 7.5
2.7 V to 5.25 V (as Low as 2.0 V With Reduced kHz.
Performance) The ADS7826/27/29 also features operation from 2.0 V
•Rail-to-Rail, Pseudo Differential Input to 5 V, a synchronous serial interface, and a differential
•Wide Reference Voltage: 50 mV to VCC input. The reference voltage can be set to any level
within the range of 50 mV to VCC.
•Micropower Auto Power-Down:
– Less Than 60 µW at 75 kHz, 2.7 V VCC Ultra-low power and small package size make the
ADS7826/27/29 family ideal for battery operated sys-
•Low Power Down Current: 3 µA Max tems. It is also a perfect fit for remote data acquisition
•Ultra Small Chip Scale Package: modules, simultaneous multichannel systems, and iso-
8-pin 3 x 3 PDSO (SON, Same Size as QFN) lated data acquisition. The ADS7826/27/29 family is
available in a 3 x 3 8-pin PDSO (SON, same size as
•SPI™ Compatible Serial Interface QFN) package.
APPLICATIONS
•Battery Operated Systems
•Remote Data Acquisition
•Isolated Data Acquisition
•Simultaneous Sampling, Multichannel
Systems
microPOWER is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
cludetestingofallparameters.
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ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
MAXIMUM LINERARITY ERROR SPECIFICATION
(LSB) TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT INTEGRAL DIFFERENTIAL PACKAGE (1) RANGE MARKING (2) NUMBER MEDIA
ADS7829I ±2±2 SON-8 -40°C to 85°C F29 ADS7829IDRBR Tape and reel
ADS7829IB ±1.25 -1/1.25 SON-8 -40°C to 85°F29 ADS7829IBDRBR Tape and reel
ADS7826I ±1±1 SON-8 -40°C to 85°C F26 ADS7826IDRBR Tape and reel
ADS7827I ±1±1 SON-8 -40°C to 85°C F27 ADS7827IDRBR Tape and reel
ADS7829I ±2±2 SON-8 -40°C to 85°C F29 ADS7829IDRBT Tape and reel
ADS7829IB ±1.25 -1/1.25 SON-8 -40°C to 85°C F29 ADS7829IBDRBT Tape and reel
ADS7826I ±1±1 SON-8 -40°C to 85°C F26 ADS7826IDRBT Tape and reel
ADS7827I ±1±1 SON-8 -40°C to 85°C F27 ADS7827IDRBT Tape and reel
(1) For detail drawing and dimension table, see end of this data sheet or package drawing file on web.
(2) Performance Grade information is marked on the reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VCC 6 V
Analog input -0.3 V to (VCC + 0.3 V)
Logic input -0.3 V to 6 V
Case temperature 100°C
Junction temperature 150°C
Storage temperature 125°C
External reference voltage 5.5 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
SPECIFICATIONS
At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
ADS7829IB ADS7829 ADS7826I ADS7827I
TEST
PARAMETER UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale input +In - (-In) 0 Vref 0 Vref 0 Vref 0 Vref V
span
Absolute input +In -0.2 VCC +0.2 -0.2 VCC +0.2 -0.2 VCC +0.2 -0.2 VCC +0.2 V
range -IN -0.2 1.0 -0.2 1.0 -0.2 1.0 -0.2 1.0 V
Capacitance 25 25 25 25 pF
Leakage current ±1±1±1±1 µA
SYSTEM PERFORMANCE
Resolution 12 12 10 8 Bits
No missing codes 12 11 10 8 Bits
Integral linearity error -1.25 ±0.4 1.25 -2 ±0.8 2 -1 ±0.3 1 -1 ±0.2 1 LSB (1)
Differential linearity error -1 ±0.4 1.25 -2 ±0.8 2 -1 ±0.3 1 -1 ±0.2 1 LSB
Offset error -3 ±0.3 3 -3 ±0.6 3 -2 ±0.4 2 -1 ±0.4 1 LSB
Gain error -2 ±0.3 2 -2 ±0.6 2 -1 ±0.3 1 -1 ±0.2 1 LSB
Noise 33 33 33 33 µVrms
Power supply rejection 82 82 94 98 dB
SAMPLING DYNAMICS
Conversion time 12 12 10 8 DCLOCK
Cycles
Acquisition time 1.5 1.5 1.5 1.5 DCLOCK
Cycles
fDCLOCK 16 x fsample 16 x fsample 14 x fsample 12 x fsample kHz
Throughput 2.7 V ≤VCC 125 125 200 250 kHz
(sample rate) ≤5.25 V (2)
fsample 2.0 V ≤VCC 75 75 85 100 kHz
< 2.7 V (3) (2)
DYNAMIC CHARACTERISTICS
Total harmonic distortion -82 -80 -78 -72 dB
SINAD VIN = 2.5 Vpp at 72 70 62 50 dB
1 kHz
Spurious free VIN = 2.5 Vpp at 85 82 81 68 dB
dynamic range 1 kHz
(SFDR)
REFERENCE INPUT
Voltage range 2.7 V ≤VCC≤3.6 V 0.05 VCC-0.2 0.05 VCC-0.2 0.05 VCC-0.2 0.05 VCC-0.2 V
Resistance CS = GND, 5 5 5 5 GΩ
fSAMPLE = 0 Hz
CS = VCC 5555GΩ
Current drain Full speed at Vref/2 12 60 12 60 20 100 24 120 µA
fSAMPLE = 7.5 kHz 0.8 0.8 0.8 0.8 µA
CS = VCC 0.001 3 0.001 3 0.001 3 0.001 3 µA
DIGITAL INPUT/OUTPUT
Logic family CMOS CMOS CMOS CMOS
Logic levels
VIH IIH = +5 µA 2.0 5.5 2.0 5.5 2.0 5.5 2.0 5.5 V
VIL IIL = +5 µA -0.3 0.8 -0.3 0.8 -0.3 0.8 -0.3 0.8 V
(1) LSB means Least Significant Bit and is equal to Vref /2Nwhere N is the resolution of ADC. For example, with Vref equal to 2.5 V, one
LSB is 0.61 mV for a 12 bit ADC (ADS7829).
(2) See the Typical Performance Curves for VCC = 5 V and Vref = 5 V.
(3) The maximum clock rate of the ADS7826/27/29 are less than 1.2 MHz at 2 V ≤VCC <2.7 V. The recommended regerence voltage is
between 1.25 V to 1.024 V.
3
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ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
SPECIFICATIONS (continued)
At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
ADS7829IB ADS7829 ADS7826I ADS7827I
TEST
PARAMETER UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
VOH IOH = -250 µA 2.2 2.1 2.1 2.1 V
VOL IOL = 250 µA 0.4 0.4 0.4 0.4 V
Data format Straight binary Straight binary Straight binary Straight binary
POWER SUPPLY REQUIREMENTS
VCC Operating range 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V
See (3) and (2) 2.0 2.7 2.0 2.7 2.0 2.7 2.0 2.7 V
See (2) 3.6 5.25 3.6 5.25 3.6 5.25 3.6 5.25 V
Quiescent cur- Full speed (4) 220 350 220 350 250 350 260 350 µA
rent fSAMPLE = 7.5 kHz 20 20 20 20 µA
(5),
fSAMPLE = 7.5 kHz 180 180 180 180 µA
(6)
Power down CS = VCC 3 3 3 3 µA
TEMPERATURE RANGE
Specified performance -40 85 -40 85 -40 85 -40 85 °C
(4) Full speed: 125 ksps for ADS7829, 200 ksps for ADS7826, and 250 ksps for ADS7827.
(5) fDCLOCK = 1.2 MHz, CS = VCC for 145 clock cycles out of every 160 for the ADS7829I and ADS7829IB.
(6) See the Power Dissipation section for more information regarding lower sample rates.
At -40°C to 85°C, VCC = 5 V, Vref = 5 V, unless otherwise specified.
ADS7829IB ADS7829 ADS7826I ADS7827I
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
SYSTEM PERFORMANCE
Resolution 12 12 10 8 Bits
No missing codes 12 11 10 8 Bits
Integral linearity error ±0.6 ±0.8 ±0.15 ±0.1 1 LSB (7)
Differential linearity error ±0.5 ±0.8 ±0.15 ±0.1 1 LSB
ANALOG INPUT
Offset error ±2.6 ±2.6 ±1.2 ±0.7 LSB
Gain error ±1.2 ±1.2 ±0.2 ±0.1 LSB
REFERENCE INPUT
Voltage range 0.05 VCC 0.05 VCC 0.05 VCC 0.05 VCC V
(7) LSB means Least Significant Bit . With Vref equal to 5 V, one LSB is 1.22 mV for a 12 bit ADC.
4
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8
7
6
5
REF
+IN
−IN
GND
+VDD
DCLOCK
DOUT
CS/ SHDN
PDSO (SON−8) PACKAGE
(TOP VIEW)
1
2
3
4
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
DEVICE INFORMATION
PIN DESCRIPTION
Terminal Functions
PIN NAME DESCRIPTION
1 Vref Reference input
2 +In Noninverting input
3 -In Inverting input. Connect to ground or to remote ground sense point.
4 GND Ground
5 CS/SHDN Chip select when LOW, shutdown mode when HIGH
6 DOUT The serial output data word is comprised of 12 bits of data. In operation the data is valid
on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS
enables the serial output. After one null bit, the data is valid for the next 12 edges.
7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.
8 +VCC Power supply
5
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-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584
Integral Linearity - LSB
Decimal Code
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 128 256 384 512 640 768 896
Decimal Code
Integral Linearity - LSB
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224
Decimal Code
Integral Linearity - LSB
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 INTEGRAL LINEARITY
Figure 1
ADS7826 INTEGRAL LINEARITY
Figure 2
ADS7827 INTEGRAL LINEARITY
Figure 3
6
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-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584
Decimal Code
Differential Linearity - LSB
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 128 256 384 512 640 768 896
Decimal Code
Differential Linearity - LSB
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224
Decimal Code
Differential Linearity - LSB
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 DIFFERENTIAL LINEARITY
Figure 4
ADS7826 DIFFERENTIAL LINEARITY
Figure 5
ADS7827 DIFFERENTIAL LINEARITY
Figure 6
7
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−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −20 0 20 40 60 80
ADS7829
Delta From 25
TA − Free-Air Temperature − °C
C
°− LSB
ADS7826
ADS7827
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −20 020 40 60 80
ADS7826
ADS7827
ADS7829
Delta From 25
TA − Free-Air Temperature − °C
C
°− LSB
−0.1
0
0.1
0.2
0.3
0.4
0.5
−40 −20 0 20 40 60 80
ADS7826
ADS7827
ADS7829
Delta From 25
TA − Free-Air Temperature − °C
C
°− LSB
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −20 0 20 40 60 80
ADS7827
Delta From 25
TA − Free-Air Temperature − °C
C
°− LSB
ADS7829
ADS7826
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN MINIMUM INTEGRAL LINEARITY CHANGE IN MAXIMUM INTEGRAL LINEARITY
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 7. Figure 8.
CHANGE IN MINIMUM DIFFERENTIAL LINEARITY CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
CHANGE IN OFFSET ERROR CHANGE IN GAIN ERROR
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 11. Figure 12.
8
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−50
−40
−30
−20
−10
0
10
20
30
40
50
−40 −20 20 40 60 800
Quiescent Current − mA
IO−
TA − Free-Air Temperature − °C
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
2.7 3.2 3.7 4.2 4.7 5.2
ADS7826
ADS7827
ADS7829
Vref = 2.5 V
VCC − Supply Voltage − V
Delta From 2.7 V − LSB
−0.1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
2.7 3.2 3.7 4.2 4.7 5.2
ADS7826
Vref = 2.5 V
VCC − Supply Voltage − V
Delta From 2.7 V − LSB
ADS7829
ADS7827
0
1
2
3
4
5
6
2.7 3.2 3.7 4.2 4.7 5.2
ADS7826
ADS7827
ADS7829
VCC − Supply Voltage − V
Delta From 2.7 V − LSB
Vref = 2.5 V
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN QUIESCENT CURRENT CHANGE IN MAXIMUM INTEGRAL LINEARITY
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 13. Figure 14.
CHANGE IN MINIMUM INTEGRAL LINEARITY CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 15. Figure 16.
CHANGE IN MINIMUM INTEGRAL LINEARITY CHANGE IN OFFSET ERROR
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 17. Figure 18.
9
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0
20
40
60
80
100
120
140
160
180
200
2.7 3.2 3.7 4.2 4.7 5.2
ADS7829
Vref = 2.5 V ADS7827
VCC − Supply Voltage − V
Delta From 2.7 V − Aµ
ADS7826
0
0.2
0.4
0.6
0.8
1
1.2
2.7 3.2 3.7 4.2 4.7 5.2
ADS7826
ADS7827
ADS7829
VCC − Supply Voltage − V
Delta From 2.7 V − LSB
Vref = 2.5 V
Sample Rate − kHz
15
10
5
0 25 50 75 100 125 150
Reference Current −
20
30
175 200 225 250
25
0
Aµ
Reference Voltage - V
0.2
0
-0.4
1 2 3
Change in Offset - LSB
0.6
0.8
1.2
4 5
1
-0.2
-0.8
0.4
-0.6
VCC = 5 V
Reference Voltage - V
5
4
2
0.1 1
Peak-To-Peak Noise - LSB
6
8
10
10
9
3
1
7
VCC = 5 V
0
Reference Voltage - V
0.5
0
-1
0 2 3
Change in Gain - dB
1
1.5
2.5
4 5
2
-0.5
-1.5
VCC = 5 V
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN GAIN CHANGE IN QUIESCENT CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 19. Figure 20.
ADS7829
REFERENCE CURRENT CHANGE IN OFFSET ERROR
vs vs
SAMPLE RATE REFERENCE VOLTAGE
Figure 21. Figure 22.
ADS7829 ADS7829
CHANGE IN GAIN ERROR PEAK-TO-PEAK NOISE
vs vs
REFERENCE VOLTAGE REFERENCE VOLTAGE
Figure 23. Figure 24.
10
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Reference Voltage - V
11
10.75
10.25
0.1 1
Effective Number of Bits - rms
11.25
11.5
12
10
11.75
10.5
10
VCC = 5 V
Change in Integral
Linearity - LSB
Change in Differential
Linearity - LSB
VCC = 5 V
Reference Voltage - V
0.05
-0.05
1 2 3 4
Data From 2.5 V Reference - LSB
0.10
0.20
5
0.15
0
-0.10
0
10
20
30
40
50
60
70
80
90
100
110 100 1000
f − Frequency − kHz
Spurious Free Dynamic Range
Signal-To-Noise Ratio − dB
Spurious Free Dynamic Range
Signal-To-Noise
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
f - frequency - kHz
Signal-To-Noise+Distortion - dB
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
f − Frequency − kHz
Spurious Free Dynamic Range
Signal-To-Noise Ratio − dB
Spurious Free Dynamic Range
Signal-To-Noise
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1000
f - Frequency - kHz
THD - Total Harmonic Distortion - dB
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829
CHANGE IN INTEGRAL and ADS7829
DIFFERENTIAL LINEARITY EFFECTIVE NUMBER OF BITS
vs vs
REFERENCE VOLTAGE REFERENCE VOLTAGE
Figure 25. Figure 26.
ADS7829
SPURIOUS FREE DYNAMIC RANGE ADS7829
and SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTION
vs vs
SAMPLE FREQUENCY FREQUENCY
Figure 27. Figure 28.
ADS7826
ADS7829 SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION and SIGNAL-TO-NOISE RATIO
vs vs
FREQUENCY FREQUENCY
Figure 29. Figure 30.
11
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-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1000
f - Frequency - kHz
THD - Total Harmonic Distortion - dB
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
f - frequency - kHz
Signal-To-Noise+Distortion - dB
0
20
40
60
80
100
1 10 100 1000
f − Frequency − kHz
Spurious Free Dynamic Range
Signal-To-Noise Ratio − dB
Spurious Free Dynamic Range
Signal-To-Noise
0
20
40
60
80
100
110 100 1000
f - frequency - kHz
Signal-To-Noise+Distortion - dB
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1000
f - Frequency - kHz
THD - Total Harmonic Distortion - dB
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7826 ADS7826
SIGNAL-TO-NOISE + DISTORTION TOTAL HARMONIC DISTORTION
vs vs
FREQUENCY FREQUENCY
Figure 31. Figure 32.
ADS7827
SPURIOUS FREE DYNAMIC RANGE ADS7827
and SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTION
vs vs
FREQUENCY FREQUENCY
Figure 33. Figure 34.
ADS7827
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
Figure 35.
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ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
THEORY OF OPERATION
The ADS7826/27/29 is a family of micropower classic The input current on the analog inputs depends on a
successive approximation register (SAR) number of factors: sample rate, input voltage, source
analog-to-digital (A/D) converters. The architecture is impedance, and power down mode. Essentially, the
based on capacitive redistribution which inherently current into the ADS7826/27/29 family charges the
includes a sample/hold function. The converter is internal capacitor array during the sample period.
fabricated on a 0.6 µm CMOS process. The After this capacitance has been fully charged, there is
architecture and process allow the ADS7826/27/29 no further input current. The source of the analog
family to acquire and convert an analog signal at up input voltage must be able to charge the input
to 200K/250K/125K conversions per second capacitance (25 pF) to a 10/8/12-bit settling level
respectively while consuming very little power. within 1.5 DCLOCK cycles. When the converter goes
into the hold mode or while it is in the power down
The ADS7826/27/29 family requires an external mode, the input impedance is greater than 1 GΩ.
reference, an external clock, and a single power
source (VCC). The external reference can be any Care must be taken regarding the absolute analog
voltage between 50 mV and VCC. The value of the input voltage. To maintain the linearity of the
reference voltage directly sets the range of the converter, the -In input should not drop below GND -
analog input. The reference input current depends on 200 mV or exceed GND + 1 V. The +In input should
the conversion rate of the ADS7826/27/29 family. always remain within the range of GND - 200 mV to
VCC + 200 mV. Outside of these ranges, the
The minimum external clock input to DCLOCK can be converter’s linearity may not meet specifications.
as low as 10 kHz. The maximum external clock
frequency is 2 MHz for ADS7829, 2.8 MHz for REFERENCE INPUT
ADS7826 and 3 MHz for ADS7827 respectively. The
The external reference sets the analog input range.
duty cycle of the clock is essentially unimportant as
The ADS7826/27/29 family operates with a reference
long as the minimum high and low times are at least
in the range of 50 mV to VCC. There are several
400 ns (VCC = 2.7 V or greater). The minimum
important implications of this.
DCLOCK frequency is set by the leakage on the
capacitors internal to the ADS7826/27/29 family. As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced.
The analog input is provided to two input pins: +In
This is often referred to as the LSB (least significant
and -In. When a conversion is initiated, the differential
bit) size and is equal to the reference voltage divided
input on these pins is sampled on the internal
by 2N(where N is 12 for ADS7829, 10 for ADS7826,
capacitor array. While a conversion is in progress,
and 8 for ADS7827). This means that any offset or
both inputs are disconnected from any internal
gain error inherent in the A/D converter appears to
function.
increase, in terms of LSB size, as the reference
The digital result of the conversion is clocked out by voltage is reduced.
the DCLOCK input and is provided serially, most
The noise inherent in the converter also appears to
significant bit first, on the DOUT pin. The digital data
increase with lower LSB size. With a 2.5 V reference,
that is provided on the DOUT pin is for the conversion
the internal noise of the converter typically contributes
currently in progress—there is no pipeline delay.
only 0.32 LSB peak-to-peak of potential error to the
ANALOG INPUT output code. When the external reference is 50 mV,
the potential error contribution from the internal noise
The +In and -In input pins allow for a differential input is 50 times larger —16 LSBs. The errors due to the
signal. Unlike some converters of this type, the -In internal noise are gaussian in nature and can be
input is not re-sampled later in the conversion cycle. reduced by averaging consecutive conversion results.
When the converter goes into the hold mode, the
voltage difference between +In and -In is captured on For more information regarding noise, consult the
the internal capacitor array. typical performance curves Effective Number of Bits
vs Reference Voltage and Peak-to-Peak Noise vs
The range of the -In input is limited to -0.2 V to 1 V. Reference Voltage (only curves for ADS7829 are
Because of this, the differential input can be used to shown). Note that the effective number of bits
reject only small signals that are common to both (ENOB) figure is calculated based on the converter’s
inputs. Thus, the -In input is best used to sense a signal-to-(noise + distortion) ratio with a 1 kHz, 0 dB
remote signal ground that may move slightly with input signal. SINAD is related to ENOB as follows:
respect to the local ground potential.
13
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tCYC
Power
Down
tSU(CS)
tCSD
Hi-Z Null
Bit B11
(MSB)B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B01
Null
Bit B11 B10 B9 B8
Hi-Z
tSMPL tCONV tDATA
CS/SHDN
DCLOCK
DOUT
tCYC
Power
Down
tSU(CS)
tCSD
Hi-Z Null
Bit B9
(MSB)B8 B4 B3 B2 B1 B01
Null
Bit
MSB
Hi-Z
CS/SHDN
DCLOCK
DOUT
Hi-Z Null
Bit B7
(MSB)B6 B4 B3 B2 B1 B01
Null
Bit
MSB
Hi-Z
tSMPL tCONV
ADS7826
DOUT
ADS7827
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
Serial Interface
SINAD = 6.02 ×ENOB + 1.76
The ADS7826/27/29 family communicates with
With lower reference voltages, extra care should be
microprocessors and other digital systems via a
taken to provide a clean layout including adequate
synchronous 3-wire serial interface. Timings for
bypassing, a clean power supply, a low-noise
ADS7829 are shown in Figure 36 and Table 1. The
reference, and a low-noise input signal. Because the
DCLOCK signal synchronizes the data transfer with
LSB size is lower, the converter is more sensitive to
each bit being transmitted on the falling edge of
external sources of error such as nearby digital
DCLOCK. Most receiving systems capture the
signals and electromagnetic interference.
bitstream on the rising edge of DCLOCK. However, if
DIGITAL INTERFACE the minimum hold time for DOUT is acceptable, the
system can use the falling edge of DCLOCK to
Signal Levels capture each bit.
The digital inputs of the ADS7826/27/29 family can The timings for ADS7826 and ADS7827 serial
accommodate logic levels up to 6 V regardless of the interface are shown in Figure 37 and Table 1. The
value of VCC. Thus, the ADS7826/27/29 family can be DCLOCK signal synchronizes the data transfer with
powered at 3 V and still accept inputs from logic each bit being transmitted on the falling edge of
powered at 5 V. DCLOCK. Most receiving systems capture the
bitstream on the rising edge of DCLOCK. However, if
The CMOS digital output (DOUT) swings 0 V to VCC. If
the minimum hold time for DOUT is acceptable, athe
VCC is 3 V and this output is connected to a 5-V
system can use the fallng edge of DCLOCK to
CMOS logic input, then that IC may require more
capture each bit.
supply current than normal and may have a slightly
longer propagation delay.
After completing the data transfer, if further clocks are applied with CS LOW, the A/D outputs LSB-First data then
followed with zeroes indefinitely.
Figure 36. ADS7829 Timing
Figure 37. ADS7826 and ADS7827 Timing
14
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www.ti.com
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
Table 1. Timing Specifications (VCC = 2.7 V and Above -40°C to 85°C
SYMBOL DESCRIPTION MIN TYP MAX UNIT
tSAMPLE Analog input sample time 1.5 2.0 DCLOCK
Cycles
tCONV Conversion time ADS7829I or ADS7829IB 12 DCLOCK
Cycles
ADS7826I 11
ADS7827I 9
tCYC Cycle time ADS7829I or ADS7829IB 16 DCLOCK
Cycles
ADS7826 14
ADS7827 12
tCSD CS falling to DCLOCK LOW 0 ns
tSU(CS) CS falling to DCLOCK rising 30 ns
th(DO) DCLOCK falling to current DOUT not valid 15 ns
td(DO) DCLOCK falling to next DOUT valid 130 200 ns
tdis CS rising to DOUT 3-state 40 80 ns
ten DCLOCK falling to DOUT enabled 75 175 ns
tfDOUT fall time 90 200 ns
trDOUT rise time 110 220 ns
A falling CS signal initiates the conversion and data
DATA FORMAT
transfer. The first 1.5 to 2.0 clock periods of the
conversion cycle are used to sample the input signal. The output data from the ADS7826/27/29 family is in
After the second falling DCLOCK edge, DOUT is straight binary format. ADS7829 out is shown in
enabled and outputs a LOW value for one clock Table 2, as an example. This table represents the
period. For the next N (N is 12 for ADS7829, 10 for ideal output code for the given input voltage and does
ADS7826, and 8 for ADS7827) DCLOCK periods, not include the effects of offset, gain error, or noise.
DOUT outputs the conversion result, most significant For ADS7826 the last two LSB’s are don’t cares,
bit first. After the least significant bit has been sent, while for ADS7827 the last four LSB’s are don’t
DOUT goes to 3-state after the rising edge of CS. A cares.
new conversion is initiated only when CS has been
taken high and returned low again.
Table 2. Ideal Input Voltages and Output Codes (ADS7829 Shown as an Example)
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
FULL SCALE RANGE Vref STRAIGHT BINARY
LEAST SIGNIFICANT BIT (LSB) Vref/4096 BINARY CODE HEX CODE
Full scale Vref - 1 LSB 1111 1111 1111 FFF
Midscale Vref/2 1000 0000 0000 800
Midscale - 1 LSB Vref/2 - 1 LSB 0111 1111 1111 7FF
Zero 0 V 0000 0000 0000 000
15
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DOUT
1.4 V
Test Point
3 k
100 pF
CLOAD
tr
DOUT
tf
Test Point
3 k
CS/SHDN
DOUT
DOUT
90%
10%
1
B11
2
CS/SHDN
DCLOCK
DOUT
DCLOCK VIL
100 pF
Voltage Waveforms for ten
DOUT
th(DO)
Voltage Waveforms for DOUT Delay Times, tdDO
VOH
VOL
VOH
VOL
DOUT
th(DO)
CLOAD
VCC tdisWaveform 2, ten
tdisWaveform 1
Load Circuit for tdis and ten
tdis
VIH
Voltage Waveforms for tdis
Waveform 1 (1)
Waveform 2 (2) ten
VOL
Load Circuit for tdDO, tr, and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
(1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control.
(2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.
Figure 38. Timing Diagrams and Test Circuits for the Parameters in Table 1.
POWER DISSIPATION
The architecture of the converter, the semiconductor This way, the converter spends the longest possible
fabrication process, and a careful design allows the time in the power down mode. This is very important
ADS7826/27/29 family to convert at the full sample as the converter not only uses power on each
rate while requiring very little power. But, for the DCLOCK transition (as is typical for digital CMOS
absolute lowest power dissipation, there are several components) but also uses some current for the
things to keep in mind. analog circuitry, such as the comparator. The analog
section dissipates power continuously, until the
The power dissipation of the ADS7826/27/29 family power-down mode is entered.
scales directly with conversion rate. Therefore, the
first step to achieving the lowest power dissipation is The current consumption of the ADS7826/27/29
to find the lowest conversion rate that satisfies the family versus sample rate. For this graph, the
requirements of the system. converter is clocked at maximum DCLOCK rate
regardless of the sample rate —CS is HIGH for the
In addition, the ADS7826/27/29 family is in power remaining sample period. Figure 4 also shows current
down mode under two conditions: when the consumption versus sample rate. However, in this
conversion is complete and whenever CS is HIGH. case, the minimum DCLOCK cylce time is used—CS
Ideally, each conversion occurs as quickly as is HIGH for one DCLOCK cycle.
possible, preferably, at DCLOCK rate.
16
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www.ti.com
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
There is an important distinction between the power The reference should be similarly bypassed with a
down mode that is entered after a conversion is 0.1-µF capacitor. Again, a series resistor and large
complete and the full power-down mode which is capacitor can be used to lowpass filter the reference
enabled when CS is HIGH. While both shutdown the voltage. If the reference voltage originates from an
analog section, the digital section is completely op-amp, be careful that the op-amp can drive the
shutdown only when CS is HIGH. Thus, if CS is left bypass capacitor without oscillation (the series
LOW at the end of a conversion and the converter is resistor can help in this case). Keep in mind that
continually clocked, the power consumption is not as while the ADS7826/27/29 family draws very little
low as when CS is HIGH. current from the reference on average, there are still
instantaneous current demands placed on the
Power dissipation can also be reduced by lowering external reference circuitry.
the power supply voltage and the reference voltage.
The ADS7826/27/29 family operates over a VCC Also, keep in mind that the ADS7826/27/29 family
range of 2.0 V to 5.25 V. However, at voltages below offers no inherent rejection of noise or voltage
2.7 V, the converter does not run at the maximum variation in regards to the reference input. This is of
sample rate. See the typical performance curves for particular concern when the reference input is tied to
more information regarding power supply voltage and the power supply. Any noise and ripple from the
maximum sample rate. supply appears directly in the digital results. While
high frequency noise can be filtered out as described
LAYOUT in the previous paragraph, voltage variation due to
the line frequency (50 Hz or 60 Hz), can be difficult to
For optimum performance, care should be taken with remove.
the physical layout of the ADS7826/27/29 family
circuitry. This is particularly true if the reference The GND pin on the ADS7826/27/29 family must be
voltage is low and/or the conversion rate is high. At a placed on a clean ground point. In many cases, this
125-kHz to 250-kHz conversion rate, the is the analog ground. Avoid connecting the GND pin
ADS7826/27/29 family makes a bit decision every too close to the grounding point for a microprocessor,
800 ns to 400 ns. That is, for each subsequent bit microcontroller, or digital signal processor. If needed,
decision, the digital output must be updated with the run a ground trace directly from the converter to the
results of the last bit decision, the capacitor array power supply connection point. The ideal layout
appropriately switched and charged, and the input to includes an analog ground plane for the converter
the comparator settled, for example the ADS7829, to and associated analog circuitry.
a 12-bit level all within one clock cycle.
APPLICATION CIRCUITS
The basic SAR architecture is sensitive to spikes on
the power supply, reference, and ground connections Figure 39 and Figure 40 show some typical
that occur just prior to latching the comparator output. application circuits the ADS7826/27/29 family. Figure
Thus, during any single conversion for an n-bit SAR 39 uses an ADS7826/27/29 and a multiplexer to
converter, there are n windows in which large provide for a flexible data acquisition circuit. A
external transient voltages can easily affect the resistor string provides for various voltages at the
conversion result. Such spikes might originate from multiplexer input. The selected voltage is buffered
switching power supplies, digital logic, and high and driven into Vref. As shown in Figure 39, the input
power devices, to name a few. This particular source range of the ADS7826/27/29 family programmable to
of error can be very difficult to track down if the glitch 100 mV, 200 mV, 300 mV, or 400 mV. The 100-mV
is almost synchronous to the converter’s DCLOCK range would be useful for sensors such as
signal—as the phase difference between the two thermocouple shown.
changes with time and temperature, causing sporadic Figure 39 shows a basic data acquisition system. The
misoperation. ADS7826/27/29 family input range is 0 V to VCC, as
With this in mind, power to the ADS7826/27/29 family the reference input is connected directly to the power
should be clean and well bypassed. A 0.1-µF ceramic supply. The 5-Ωresistor and 1-µF to 10-µF capacitor
bypass capacitor should be placed as close to the filters the microcontroller noise on the supply, as well
ADS7826/27/29 family package as possible. In as any high-frequency noise from the supply itself.
addition, a 1-µ to 10-µF capacitor and a 5-Ωor 10-ΩThe exact values should be picked such that the filter
series resistor may be used to lowpass filter a noisy provides adequate rejection of the noise.
supply.
17
www.ti.com
ADS7826/27/29
µP
DCLOCK
DOUT
CS/SHDN A0
A1
U3
U4
U1
U2
Thermocouple
ISO Thermal Block
MUX
OPA237 0.3 V
0.4 V
0.2 V
0.1 V
+3 V
R2
59 kΩ
R4
1 kΩ
R3
500 kΩ
R5
500 Ω
R7
5 Ω
C3
0.1 µF
C4
10 µFC5
0.1 µF
R6
1 MΩ
R1
1
TC2
TC1
TC3
+3 V
C2
0.1 µFC1
10 µF
+3 V R8
26 kΩ
R9
1 kΩ
R10
1 kΩ
R11
1 kΩ
R12
1 kΩ
VREF
ADS7826/27/29
VCC
CS
DOUT
DCLOCK
VREF
+In
–In
GND
+
+
5
Microcontroller
+2.7V to +3.6V
1 F to
10 F
1 F to
10 F
0.1 F
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
Figure 39. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7826/27/29 family
Figure 40. Basic Data Acquisition System
18
PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7826IDRBR ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7826IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7826IDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7826IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7827IDRBR ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7827IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7827IDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7827IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7829IBDRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IBDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IBDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IBDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IDRBR ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
ADS7829IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7826IDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ADS7826IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ADS7827IDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ADS7827IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7826IDRBR SON DRB 8 2500 367.0 367.0 35.0
ADS7826IDRBT SON DRB 8 250 210.0 185.0 35.0
ADS7827IDRBR SON DRB 8 2500 367.0 367.0 35.0
ADS7827IDRBT SON DRB 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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