a
AD8568/AD8569/AD8570
REV. C
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16 V Rail-to-Rail
Buffer Amplifiers
PIN CONFIGURATIONS
6-Lead SOT-23
(RT Suffix)
GND IN B
34
IN A V+
25
OUT A OUT B
16
AD8568
10-Lead MSOP
(RM Suffix)
56
IN A
V+
IN B
OUT C
IN D
GND
IN C
OUT D
29
38
47
110
AD8569
OUT B
OUT A
32-Lead LFCSP
(CP Suffix)
PIN 1
INDICATOR
TOP VIEW
24 GND
23 NC
22 OUT C
21 OUT D
V+ 1
NC 2
IN C 3
32 NC
20 OUT E
19 OUT F
18 NC
17 GND
NC 9
IN G 10
IN H 11
NC 12
NC 13
OUT H 14
OUT G 15
NC 16
IN D 4
IN E 5
IN F 6
NC 7
V+ 8
31 IN B
30 IN A
29 NC
28 NC
27 OUT A
26 OUT B
25 NC
AD8570
NC = NO CONNECT
20-Lead TSSOP
20
19
18
17
16
15
14
13
12
11 OUT 8
OUT 7
V–
OUT 2
V–
OUT 3
OUT 6
OUT 5
OUT 4
OUT 1
AD8570-ARU
TOP VIEW
1
2
3
4
5
6
7
8
9
10
IN 8
IN 7
V+
IN 2
V+
IN 3
IN 6
IN 5
IN 4
IN 1
FEATURES
Single-Supply Operation: 4.5 V to 16 V
Input Capability Beyond the Rails
Rail-to-Rail Output Swing
Continuous Output Current: 35 mA
Peak Output Current: 250 mA
Offset Voltage: 10 mV Max
Slew Rate: 6 V/s
Stable with 1 F Loads
Supply Current
APPLICATIONS
LCD Reference Drivers
Portable Electronics
Communications Equipment
GENERAL DESCRIPTION
The AD8568, AD8569, and AD8570 are low-cost, single-supply
buffer amplifiers with rail-to-rail input and output capability. They
are optimized for LCD monitor applications and built on an
advanced high voltage CBCMOS process. The AD8568 includes
two buffers, the AD8569 includes four buffers, and the AD8570
includes eight buffers.
These LCD buffers have high slew rates, 35 mA continuous
output drive, and high capacitive load drive capability. They
have a wide supply range and offset voltages below 10 mV.
The AD8568, AD8569, and AD8570 are specified over the –40°C
to +85°C temperature range. They are available on tape and reel,
with the AD8568 packaged in a 6-lead SOT-23, the AD8569
in a 10-lead MSOP, and the AD8570 in a 32-lead LFCSP and
20-lead TSSOP.
–2– REV. C
AD8568/AD8569/AD8570–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
210mV
Offset Voltage Drift ∆V
OS
/∆T–40°C ≤ T
A
≤ +85°C5µV/°C
Input Bias Current I
B
80 600 nA
–40°C ≤ T
A
≤ +85°C800 nA
Input Voltage Range –0.5 –V
S
+ 0.5 V
Input Impedance Z
IN
400 kΩ
Input Capacitance C
IN
1pF
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
I
L
= 100 µAV
S
– 0.005 V
V
S
= 16 V, I
L
= 5 mA 15.85 15.95 V
–40°C ≤ T
A
≤ +85°C15.75 V
V
S
= 4.5 V, I
L
= 5 mA 4.2 4.38 V
–40°C ≤ T
A
≤ +85°C4.1 V
Output Voltage Low V
OL
I
L
= 100 µA5mV
V
S
= 16 V, I
L
= 5 mA 42 150 mV
–40°C ≤ T
A
≤ +85°C250 mV
V
S
= 4.5 V, I
L
= 5 mA 95 300 mV
–40°C ≤ T
A
≤ +85°C400 mV
Continuous Output Current I
OUT
35 mA
Peak Output Current I
PK
V
S
= 16 V 250 mA
TRANSFER CHARACTERISTICS
Gain A
VCL
R
L
= 2 kΩ0.995 0.9985 1.005 V/V
–40°C ≤ T
A
≤ +85°C0.995 0.9980 1.005 V/V
Gain Linearity NL R
L
= 2 kΩ, V
O
= 0.5 to (V
S
– 0.5 V) 0.01 %
POWER SUPPLY
Supply Voltage V
S
4.5 16 V
Power Supply Rejection Ratio PSRR V
S
= 4 V to 17 V
–40°C ≤ T
A
≤ +85°C7090 dB
Supply Current/Amplifier I
SY
V
O
= V
S
/2, No Load 700 850 µA
–40°C ≤ T
A
≤ +85°C1mA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 kΩ, C
L
= 200 pF 4 6 V/µs
Bandwidth BW –3 dB, R
L
= 10 kΩ, C
L
= 10 pF 6 MHz
Phase Margin Øo R
L
= 10 kΩ, C
L
= 10 pF 65 Degrees
Channel Separation 75 dB
NOISE PERFORMANCE
Voltage Noise Density e
n
f = 1 kHz 26 nV/√Hz
e
n
f = 10 kHz 25 nV/√Hz
Current Noise Density i
n
f = 10 kHz 0.8 pA/√Hz
Specifications subject to change without notice.
(4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25C, unless otherwise noted.)
–3–
AD8568/AD8569/AD8570
REV. C
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
S
+ 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Package Type
JA
1
JC
JB2
Unit
6-Lead SOT-23 (RT) 250 140 °C/W
10-Lead MSOP (RM) 200 44 °C/W
20-Lead TSSOP (RU) 72 45 °C/W
32-Lead LFCSP (CP) 35 13 °C/W
NOTES
1
θ
JA
is specified for worst-case conditions, i.e., θ
JA
is specified for a device soldered
onto a circuit board for surface-mount packages.
2
⌿
JB
is applied for calculating the junction temperature by reference to the board
temperature.
ORDERING GUIDE
Temperature Package Package Branding
Model Range Description Option Information
AD8568ART-R2 –40°C to +85°C6-Lead SOT-23 RT-6 AWA
AD8568ART-REEL –40°C to +85°C6-Lead SOT-23 RT-6 AWA
AD8568ART-REEL7 –40°C to +85°C6-Lead SOT-23 RT-6 AWA
AD8569ARM-R2 –40°C to +85°C10-Lead MSOP RM-10 AXA
AD8569ARM-REEL –40°C to +85°C10-Lead MSOP RM-10 AXA
AD8569ARMZ-REEL*–40°C to +85°C10-Lead MSOP RM-10 AXA
AD8570ACP-R2 –40°C to +85°C32-Lead LFCSP CP-32-2
AD8570ACP-REEL –40°C to +85°C32-Lead LFCSP CP-32-2
AD8570ACP-REEL7 –40°C to +85°C32-Lead LFCSP CP-32-2
AD8570ARU –40°C to +85°C20-Lead TSSOP RU-20
AD8570ARU-REEL –40°C to +85°C20-Lead TSSOP RU-20
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8568/AD8569/AD8570 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
AD8568/AD8569/AD8570
REV. C
INPUT OFFSET VOLTAGE (mV)
100
0
12 9
QUANTITY (Amplifiers)
63036912
90
50
30
20
10
80
70
40
60
TA = 25C
4.5V < VS < 16V
TPC 1. Input Offset Voltage Distribution
TCVOS (V/C)
300
150
0
0 10010
QUANTITY (Amplifiers)
20 30 40 50 60 70 80 90
250
200
100
50
4.5V < V
S
< 16V
TPC 2. Input Offset Voltage Drift Distribution
TEMPERATURE (C)
0
0.25
1.50 40
INPUT OFFSET VOLTAGE (mV)
25 85
0.50
0.75
1.00
1.25
VCM = VS/2
VS = 16V
VS = 4.5V
TPC 3. Input Offset Voltage vs. Temperature
TEMPERATURE (C)
0
50
350
40
INPUT BIAS CURRENT (nA)
25 85
150
200
250
300
VCM = VS/2
VS = 16V
VS = 4.5V
100
TPC 4. Input Bias Current vs. Temperature
TEMPERATURE (C)
5
5
40
INPUT OFFSET CURRENT (nA)
25 85
2
3
4
V
S
= 16V
V
S
= 4.5V
1
4
3
2
1
0
TPC 5. Input Offset Current vs. Temperature
TEMPERATURE (C)
15.96
15.86
40
OUTPUT VOLTAGE SWING (V)
25 85
15.89
15.88
15.87
VS = 16V
VS = 4.5V
15.90
15.95
15.94
15.93
15.92
15.91
ILOAD = 5mA
4.46
4.36
4.39
4.38
4.37
4.40
4.45
4.44
4.43
4.42
4.41
TPC 6. Output Voltage Swing vs. Temperature
–Typical Performance Characteristics
–5–
AD8568/AD8569/AD8570
REV. C
TEMPERATURE (C)
150
0
40
OUTPUT VOLTAGE SWING (mV)
25 85
45
30
15
V
S
= 16V
V
S
= 4.5V
60
135
120
105
90
75
I
LOAD
= 5mA
TPC 7. Output Voltage Swing vs. Temperature
TEMPERATURE (C)
0.9999
0.9995
40
GAIN ERROR (V/V)
25 85
RL = 2k
4.5V < VS < 16V
VOUT = 0.5V TO 15V
0.9997
RL = 600
TPC 8. Voltage Gain vs. Temperature
LOAD CURRENT (mA)
10
0.1
0.001 1000.01
OUTPUT VOLTAGE (mV)
0.1 1 10
1
100
1k
TA = 25C
VS = 16V
VS = 4.5V
TPC 9. Output Voltage to Supply Rail vs. Load Current
TEMPERATURE (C)
0.80
0.50
40
SUPPLY CURRENT/AMPLIFIER (mA)
25 85
0.65
0.60
0.55
VS = 16V
VS = 4.5V
0.70
VCM = VS/2
0.75
TPC 10. Supply Current/Amplifier vs. Temperature
TEMPERATURE (C)
7
0
40
SLEW RATE (V/s)
25 85
3
2
1
V
S
= 16V
V
S
= 4.5V
4
R
L
= 10k
C
L
= 200pF
5
6
TPC 11. Slew Rate vs. Temperature
SUPPLY VOLTAGE (V)
1.0
00182
SUPPLY CURRENT/AMPLIFIER (mA)
4681012 14 16
0.9
0.5
0.3
0.2
0.1
0.8
0.7
0.4
0.6
T
A
= 25C
A
V
= +1
V
O
= V
S
/2
TPC 12. Supply Current/Amplifier vs. Supply Voltage
–6–
AD8568/AD8569/AD8570
REV. C
FREQUENCY (Hz)
10
40
100k 100M
GAIN (dB)
10M1M
35
30
25
20
15
10
5
5
0
1k
10k
560
150
TA = 25C
VS = 8V
VIN = 50mV rms
CL = 40pF
AV = +1
TPC 13. Frequency Response vs. Resistive Loading
FREQUENCY (Hz)
25
100k 100M
GAIN (dB)
10M1M
25
20
15
10
5
20
0
1040pF
TA = 25C
VS = 8V
VIN = 50mV rms
RL = 10k
AV = +1
10
5
15
50pF
100pF
540pF
TPC 14. Frequency Response vs. Capacitive Loading
FREQUENCY (Hz)
100 10M1k
IMPEDANCE ()
10k 100k 1M
500
450
0
400
350
300
250
200
150
100
V
S
= 16V
V
S
= 4.5V
50
TPC 15. Closed-Loop Output Impedance vs. Frequency
OUTPUT SWING (V p-p)
FREQUENCY (Hz)
10M1M100k10k1k10010
0
2
4
6
8
10
12
14
16
18
TA = 25C
VS = 16V
AV = +1
RL = 10k
DISTORTION < 1%
TPC 16. Closed-Loop Output Swing vs. Frequency
FREQUENCY (Hz)
100 10M1k
POWER SUPPLY REJECTION RATIO (dB)
10k 100k 1M
160
140
40
120
100
80
60
40
20
0
+PSRR
20
PSRR
T
A
= 25C
V
S
= 16V
TPC 17. Power Supply Rejection Ratio vs. Frequency
FREQUENCY (Hz)
100 10M1k
POWER SUPPLY REJECTION RATIO (dB)
10k 100k 1M
160
140
40
120
100
80
60
40
20
0
+PSRR
20
PSRR
T
A
= 25C
V
S
= 4.5V
TPC 18. Power Supply Rejection Ratio vs. Frequency
–7–
AD8568/AD8569/AD8570
REV. C
FREQUENCY (Hz)
1,000
100
110 10k100
VOLTAG E NOISE DENSITY (nV/ Hz)
1k
10
TA = 25C
4.5V VS 16V
TPC 19. Voltage Noise Density vs. Frequency
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
100M10M1M100k10k1k100
180
140
120
100
80
60
40
20
0
20
T
A
= 25C
4.5V < V
S
< 16V
160
TPC 20. Channel Separation vs. Frequency
LOAD CAPACITANCE (pF)
100
90
010 1k100
OVERSHOOT (%)
80
70
60
50
40
30
20
10
T
A
= 25C
V
S
= 16V
V
CM
= 8V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 10k
OS
+OS
TPC 21. Small Signal Overshoot vs. Load Capacitance
LOAD CAPACITANCE (pF)
100
90
010 1k100
OVERSHOOT (%)
80
70
60
50
40
30
20
10
T
A
= 25C
V
S
= 4.5V
V
CM
= 2.25V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 10k
OS +OS
TPC 22. Small Signal Overshoot vs. Load Capacitance
SETTLING TIME (s)
15
10
15 02.00.5
OUTPUT SWING FROM 0V TO V
1.0 1.5
5
0
5
10
T
A
= 25C
V
S
= 8V
R
L
= 10k
OVERSHOOT SETTLING TO 0.1%
UNDERSHOOT SETTLING TO 0.1%
TPC 23. Settling Time vs. Step Size
TIME (2s/DIV)
0
0000
VOLTAGE (3V/DIV)
000000
0
0
0
0
0
0
0
T
A
= 25C
V
S
= 16V
A
V
= +1
R
L
= 10k
C
L
= 300pF
TPC 24. Large Signal Transient Response
–8–
AD8568/AD8569/AD8570
REV. C
TIME (2s/DIV)
0
0000
VOLTAGE (1V/DIV)
000000
0
0
0
0
0
0
0
T
A
= 25C
V
S
= 4.5V
A
V
= +1
R
L
= 10k
C
L
= 300pF
TPC 25. Large Signal Transient Response
TIME (1s/DIV)
0
0000
VOLTAGE (50mV/DIV)
000000
0
0
0
0
0
0
0
T
A
= 25C
V
S
= 16V
A
V
= +1
R
L
= 10k
C
L
= 100pF
TPC 26. Small Signal Transient Response
TIME (1s/DIV)
0
0000
VOLTAGE (50mV/DIV)
000000
0
0
0
0
0
0
0
T
A
= 25C
V
S
= 4.5V
A
V
= +1
R
L
= 10k
C
L
= 100pF
TPC 27. Small Signal Transient Response
TIME (40s/DIV)
0
0000
VOLTAGE (3V/DIV)
000000
0
0
0
0
0
0
0
T
A
= 25C
V
S
= 16V
A
V
= +1
R
L
= 10k
TPC 28. No Phase Reversal
–9–
AD8568/AD8569/AD8570
REV. C
APPLICATIONS
Theory of Operation
This family of buffers is designed to drive large capacitive loads in
LCD applications. Each has high output current drive and rail-
to-rail input/output operation and can be powered from a single
16 V supply. They are also intended for other applications where
low distortion and high output current drive are needed.
Input Overvoltage Protection
As with any semiconductor device, whenever the input exceeds
either supply voltage, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the magnitude
of the fault current. When the input voltage exceeds either supply
by more than 0.6 V, the internal pn junctions will allow current
to flow from the input to the supplies.
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using the
buffers where the input exceeds the supply by more than 0.6 V,
an external series resistor should be added. The size of the resis-
tor can be calculated by using the maximum overvoltage divided
by 5 mA. This resistance should be placed in series with the input
exposed to an overvoltage.
Output Phase Reversal
The buffer family is immune to phase reversal. Although the
device’s output will not change phase, large currents due to input
overvoltage could damage the device. In applications where
the possibility exists of an input voltage exceeding the supply
voltage, overvoltage protection should be used as described in
the previous section.
Power Dissipation
The maximum allowable internal junction temperature of 150°C
limits the device’s maximum power dissipation. As the ambient
temperature increases, the maximum power dissipated by the
device must decrease linearly to maintain the maximum junc-
tion temperature. If this maximum junction temperature is
exceeded momentarily, the device will still operate properly once
the junction temperature is reduced below 150°C. If the maximum
junction temperature is exceeded for an extended period of time,
overheating could lead to permanent damage of the device.
The maximum safe junction temperature, T
JMAX
, is 150°C. Using
the following formula, we can obtain the maximum power that
the buffer family can safely dissipate as a function of temperature.
PTT
DISS A A
=−
()
JMAX J
/θ
where:
P
DISS
= the power dissipation.
T
J
MAX
= the maximum allowable junction temperature
(150°C).
T
A
= the ambient temperature of the circuit.
θ
J
A
= the AD856x package thermal resistance,
junction-to-ambient.
The power dissipated by the device can be calculated as
PVV I
DISS S OUT LOAD
=−
()
×
where:
V
S
= the supply voltage.
V
OUT
= the output voltage.
I
LOAD
= the output load current.
Figure 1 shows the maximum power dissipation versus temperature.
To achieve proper operation, use the previous equation to calculate
P
DISS
for a specific package at any given temperature, or see Figure 1.
AMBIENT TEMPERATURE – C
1.00
0.75
0
35 85
15
MAXIMUM POWER DISSIPATION – W
5254565
0.50
0.25
10-LEAD MSOP
6-LEAD SOT-23
Figure 1. Maximum Power Dissipation vs. Temperature
for 6- and 10-Lead Packages
Total Harmonic Distortion + Noise (THD+N)
The buffer family features low THD+N. The total harmonic
distortion plus noise for the buffer over the entire supply range
is below 0.08%. When the device is powered from a 16 V supply,
the THD+N stays below 0.03%. Figure 2 shows the AD8568
THD+N versus frequency performance.
FREQUENCY – Hz
20 30k
THD + N – %
100 1k 10k
10
1
0.01
0.1
V
S
= 2.5V
V
S
= 8V
Figure 2. AD8568 THD+N vs. Frequency
Short-Circuit Output Conditions
The buffer family does not have internal short-circuit protection
circuitry. As a precautionary measure, do not short the output
directly to the positive power supply or to ground.
It is not recommended to operate the AD856x with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using the following equation.
RV
mA
X
S
≥35
For a 5 V single-supply operation, R
X
should have a minimum
value of 143 Ω.
–10–
AD8568/AD8569/AD8570
REV. C
OUTLINE DIMENSIONS
6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
1 3
4 5
2
6
2.90 BSC
PIN 1
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.22
0.08
10
4
0
0.50
0.30
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AB
10-Lead Micro Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.23
0.08
0.80
0.60
0.40
8
0
0.15
0.00
0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
32-Lead Lead Frame Chip Scale Package [LFCSP]
5 x 5 mm Body
(CP-32-2)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12 MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ SQ
3.25
3.10
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
–11–
AD8568/AD8569/AD8570
REV. C
Revision History
Location Page
12/03—Data Sheet changed from REV. B to REV. C.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5/02—Data Sheet changed from REV. A to REV. B.
Added 20-Lead TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Added Package Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Added TSSOP Package to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC 1.20
MAX 0.20
0.09 0.75
0.60
0.45
8
0
COMPLIANT TO JEDEC STANDARDS MO-153AC
COPLANARITY
0.10
OUTLINE DIMENSIONS
–12–
C02612–0–12/03(C)
