UC1851
UC2851
UC3851
Programmable, Off-Line, PWM Controller
FEATURES
•All Control, Driving, Monitoring, and Protec tion
Functions Included
•Low-Current Off Line Start Circuit
•Vo ltage Feed For ward or Current Mode Control
•High Current Totem P ole Output
•50% Absolute Max Duty Cycle
•PWM Latch for Single Pulse Per Period
•Pulse-by-Pulse Current Limiting plus Shutdown
for Over-Cur rent F au lt
•No Start- Up or Shutdown Transient s
•Slow Turn-O n Both Initially and After F au lt
Shutdown
•Shutdown Upon Over or Under Vo ltage Sensing
•Latch Of f or Continuous Retry After Fault
•1% Reference Accurac y
•500kHz Operation
•18 Pin DIL or 20 Pin PLCC Packa ge
DESCRIPTION
The UC1851 family of PWM controllers are optimized for off-
line primary side control. These devices include a high current
totem pole output stage and a toggle flip-flop for absolute 50%
duty cycle limiting. In a ll other respects this line of controllers is
pin for pi n compatible wit h the UC1841 series. Inclusion of all
majo r housekee ping functions in these high performance con-
trollers makes them ideal for use in cost sensitive applicat ions.
Important features of these controllers include low current
start-up, linear feed-forward for constant volt-second operation,
and compati bility w ith both vol tage or curre nt mode control. In
addition, these devices include a programmable start thresh-
old, as well as programmable over-voltage, under- voltage, and
over current fault thresholds. The fault latch on these devices
can be configured for automatic restart, or latched off response
to a fault.
These devi ces are packaged in 18-pin plastic or ceramic dual-
in-line packages, or for surface mount applications, a 20 Pin
PLCC. The UC1851 is characterized for -55°C to +125°C op-
erati on whil e the UC2851 and UC3851 are designed for -40°C
to +85°C and 0°C to +7 0°C, respectively.
BL OCK DIAG RAM
10/94
UC1851
UC2851
UC3851
Su pply Volt age, +V IN (Pin 15)
Volt age Driven. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V
Cur rent Driven, 100 mA m aximum. . . . . . . . . . . Self-limiting
PWM Out put Volta ge (Pin 12 ) . . . . . . . . . . . . . . . . . . . . . . . 40V
PW M O utput Current , Steady- Stat e (Pin 12). . . . . . . . . 400mA
PWM Out put Peak E nergy Disc harge . . . . . . . . . . . . 20µJoules
Driver Bias Current (Pin 14). . . . . . . . . . . . . . . . . . . . . -200mA
Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA
Slow-St art Sink Cur ren t (Pin 8) . . . . . . . . . . . . . . . . . . . . 20m A
VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA
Cu rrent Limit Input s (Pins 6 & 7) . . . . . . . . . . . . . -0.5 t o +5.5 V
Stop Inp ut (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0. 3 to +5. 5V
Co mp ara to r Inputs
(Pins 1–7 , 9–11, 16). . . . . . . . . . . . . . Intern a lly cla mped at 12V
Po wer Dissipa tion at T A = 25°C (Not e 3). . . . . . . . . . . 1000mW
Po wer Dissipa tion at T C = 25°C (Not e 3). . . . . . . . . . . 2000 mW
Op era ting Junct ion Te mp era tu re. . . . . . . . . . . -55°C to +150°C
Storage Temperat ure Ra nge. . . . . . . . . . . . . . -65°C to +1 50°C
L ead Te mp era ture (Solder ing, 10 sec) . . . . . . . . . . . . . +3 00°C
No te 1:All voltages are with res pect to gro und, Pin 13.
Currents are positive-into, negative-out of the
specif ie d terminal
No te 2:All pin number s are refer enc ed t o DIL-18 packa ge.
No te 3:Co nsult Packaging Sect ion of Dat abo ok for ther ma l
limitat ions an d cons ideration s of packa ge.
DIL -18, SO IC- 18 (T O P VI EW)
J or N, DW Package
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTIONS
FUNCTION PIN
COMP 1
START/UV 2
OV SENSE 3
STOP 4
RESET 5
CUR THRESH 7
CUR SENSE 8
SLOW START 9
RT/CT10
RAMP 11
VIN SENSE 12
PWM OUT 13
GROUND 14
DRIVE BI A S 15
+VIN SUPPLY 17
5.0V REF 18
INV. INPUT 19
N.I. INPUT 20
PLCC-20, LCC-20
(TOP VIEW)
Q, L PACKAGE
ABSOL UTE MAXIMUM RATING S ( Note 1)
Unless ot her w ise stat ed, these sp ecif icat io ns apply for TA = -55 °C to +125°C f or the
UC1851, -40°C to +8 5°C for the UC2851, and 0°C to 70°C for the UC3851; VIN =
20 V, R T = 2 0kΩ, CT = .001 m fd , RR = 10kΩ, CR = .001mfd. Curren t Limit Threshold
= 20 0m V, T A = TJ.
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDI TION S UC1851 / UC2851 UC3851 UNITS
MIN TYP MAX MIN TYP MAX
Power In puts
Start - Up Curr ent VIN = 30V, Pin 2 = 2.5 V 4.5 6 4.5 6 mA
Oper at ing Cur ren t VIN = 30V, Pin 2 = 3.5V 15 21 15 21 mA
Supply OV Clamp VIN = 20mA 333945333945V
Refere nce S ec tio n
Reference Voltage TJ = 25° C 4. 95 5 .0 5. 05 4 .9 5.0 5 .1 V
Line Reg ulat ion VIN = 8 to 30V 10 15 10 20 mV
Load Regulat ion IL = 0 to 10mA 1020 1030mV
Total Ref Variat io n Over Op era ting Temper at ure Range 4.9 5.1 4 .85 5.1 5 V
Short Circuit Current VREF = 0, TJ = 25°C -80 -100 -80 -100 mA
Oscillator
Nominal Fre quen cy TJ = 25°C 47 50 53 45 50 55 kHz
Voltage St ability V IN = 8 to 30V 0.5 1 0.5 1 %
Total Ref Variat io n Over Op era ting Temper at ure Range 45 55 43 57 kH z
Maximum Frequency RT = 2k Ω, CT = 330pF 500 500 kHz
2
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDI TION S UC1851 / UC2851 UC3851 UNITS
MIN TYP MAX MIN TYP MAX
Ram p G e nerat o r
Ramp Curren t, M in imum ISENSE = −10µA-11 -14 -11 -14 µA
Ramp Cur ren t, Maximum ISENSE = 1. 0mA -0.9 -.9 5 -0.9 -.9 5 mA
Ramp Valley 0.3 0.4 0.6 0.3 0.4 0.6 V
Ramp Peak Clamp ing Leve l 3.9 4.2 4. 5 3.9 4.2 4. 5 V
Error Amplifier
Input O ffset Vo ltage VCM = 5.0V 0 .5 5 2 10 mV
Input Bias Curren t 0.5 2 1 5 µA
Input O ffset Cu rr ent 0.5 0.5 µA
Open Loop Gain ∆VO = 1 to 3V 60 66 60 66 dB
Output Swing (Max O utput ≤
Ramp Peak - 100mV) Minimum Tot al Range 0.3 3.5 0.3 3.5 V
CMRR VCM = 1.5 to 5.5V 70 80 70 80 dB
PSRR VIN = 8 to 30V 70 80 70 80 dB
Short Circuit Current VCOMP = 0V - 4 -10 - 4 -1 0 mA
Gain Band w idth (Not e 1) TJ = 25 °C, A VOL = 0dB 1 2 1 2 MHz
Slew Rate (Not e 1) TJ = 25°C, AVCL = 0dB 0.8 0.8 V/µs
PWM Se cti o n
Continuo us Dut y Cycle Range
(other than zero) (Note 1) Minimum Tot al Cont inuou s Range
Ramp Peak < 4. 2V 246246%
Output High Level ISOURCE = 20mA 18 18. 5 18 18. 5 V
ISOURCE = 200mA 17 18.5 1 7 1 8.5 V
Rise Time (Not e 1) TJ = 25 °C, C L = 1nF 50 150 50 150 ns
Fall Time (Note 1) T J = 25 °C, C L = 1nF 50 150 50 150 ns
Out put Satur at ion IOUT = 20mA 0.2 0.4 0.2 0.4 V
IOUT = 200 m A 1. 7 2. 2 1. 7 2.2 V
Comparat or Dela y (Note 1) P in 8 t o Pin 12, T J = 25°C, RL = 1kΩ300 500 300 500 ns
Sequencing Functions
Compar at or Thre sholds Pins 2, 3, 5 2.8 3. 0 3.2 2. 8 3. 0 3.2 V
Input Bias Cur ren t Pins 3, 5 = 0V -1. 0 -4.0 -1.0 -4.0 µA
Input Leakage Pins 3, 5 = 10V 0.1 2.0 0.1 2.0 µA
Start /UV Hyst er esis Cur ren t Pin 2 = 2.5V 1 70 200 2 20 17 0 200 2 30 µA
Ext. Stop Threshold Pin 4 0.8 1.6 2.4 0.8 1.6 2.4 V
Error Latch Act ivat e Cur ren t Pin 4 = 0V, Pin 3 > 3V -120 -20 0 -120 -200 µA
Driver Bias Satur at ion Volta ge,
VIN-VOH IB = -50mA 2 3 2 3 V
Driver Bias Leakage V B = 0V -0.1 -10 -0.1 -10 µA
Slow-Start Saturation IS = 10mA 0.2 0.5 0.2 0.5 V
Slow-Start Leakage VS = 4.5V 0 .1 2.0 0.1 2.0 µA
Curren t Contro l
Curren t Lim it Off set 0 5 0 10 mV
Curren t Shu tdown O ffs et 370 4 00 430 360 4 00 440 mV
Input Bias Current Pin 7 = 0V -2 -5 -2 -5 µA
Comm on M ode Ran ge (No te 1) -0. 4 3.0 -0. 4 3.0 V
Curren t Limit Delay (Note 1) TJ = 25 °C, Pin 7 to 12, R L = 1k 200 400 200 400 ns
No te 1:Guara nt eed by design. Not 100% tested in pr oduction .
UC1851
UC2851
UC3851
Unless ot her w ise stat ed, these sp ecif icat io ns apply for TA = -55°C to +125°C f or the
UC1851, -40°C to +8 5°C for the UC2851, and 0°C to 70°C for the UC3851; VIN =
20 V, R T = 20kΩ, CT = .001 m fd , R R = 10kΩ, CR = .001mfd. Curren t Limit Threshold
= 20 0m V, T A = TJ.
3
UC1851
UC2851
UC3851
PWM CONTRO L
1. Oscillator G e ner ates a fixed- frequ ency inter nal clock f rom an external RT and CT.
F req uenc y = KC
RTCT where KC is a f ir st -order cor rectio n fa ctor ≈ 0.3 log (CT x 1 0 12).
2. Ramp Generat or : Develops linear ramp with slope defin ed exter nally by dV
dT = sense voltage
RRCR.
CR is norma l ly selected ≤ CT and its value w ill have som e eff ect upon val ley duty cyc le.
L imit ing th e minimum value for ISENSE into pin 11 wi ll estab lish a m ax imum duty cy cle clam p.
CR ter mina l can be use d as an input port for cur rent mod e contr ol.
3. Error Am plifier Co nven tion al oper at ional am p lifier for closed -loop gain and ph ase co mp ensa tion .
L ow out put imp edance; unity-g ain st able.
T he out pu t is held low by the slow start volta ge at tu rn on in order to m inim ize over sho ot .
4. Ref ere nce Ge n era tor: Precision 5.0 V for inte rna l and exter nal usag e to 50mA.
T rac king 3.0V re fe ren ce f or inter nal usag e only with nom inal a ccur acy of ±2%.
4 0V clam p zener for chip O V prot ect ion, 100mA maximum curren t.
5. PWM Compar at or : G e ner at es outpu t pu lse which star ts at termina tion of clock pulse and ends when t he ramp input
cros ses t he lowes t of two posit ive input s.
6. PWM Lat ch : Terminat es t he PWM out put pulse when set by inputs from either the PW M co mp arator, th e
p ulse- by- pulse co mparato r, or the erro r latch. Resets wit h each internal clock pulse.
7. PWM Out put Switch: T otem pole out put stage capab le of sourc in g and sinkin g 1 amp peak current . The active "on" stat e
is high.
SEQUENCING FUNCTIONS
1. Sta rt/UV Se nse: Wit h an incr easing volta ge, this com par at or gener at es a turn -on signal and r elease s the slow start
cla mp at a star t thr esh old.
Wit h a decr eas ing volt age, it gener at es a turn -off comm and at a lower level separ at ed by a 200µA
h yster esis cur re nt .
2. Drive Swit ch: Disa bles most of the chip to hold interna l curr ent cons um ptio n low, and Driver Bias OFF, unt i l inpu t
volta ge re ache s start thre shold.
3. Driver Bias: Su pplies dr ive to ext ern al circuit ry upon star t-up .
4. Slo w Start : Clamps low to hold PWM OF F. Upon re lease, rise s with rat e contr o lled by RSCS for slow increase of
o ut put pulse width.
Ca n also be us ed as an alter nat e maxim um dut y cycle clamp with an ex terna l voltag e divider .
PROTECTI O N FUNCTIO NS
1. Error Latc h: Whe n set by mom ent ar y input , this latch insu res im mediat e PW M shut down an d hold off unt il reset.
Inputs to Error Latch are:
a . OV > 3.2V (Typically 3V)
b . Stop > 2.4V (Typica lly 1.6V)
c. Curre nt Sense 40 0m V over thresh old. (Typic al).
Erro r Latch rese ts when slow st ar t voltag e falls to 0.4V if Res et Pin < 2. 8V. With Pin 5 > 3.2V,
Error Latch will remain set.
2. Curr ent Limiting: Differe nt ia l input comp ara tor terminates indiv idual out put pulse s each tim e sense volt age r ises
above threshold.
Wh e n sense volt age r ises t o 400mV (t yp ical) abo ve t hre shold, a shutd own signa l is sent to Error
Latch.
3. Ext ern al Stop : A volt ag e over 2.4 w ill set th e Error La tc h and ho ld th e output of f.
A volta g e less than 0. 8V will defeat the error latch and pre vent shu td own.
A capacit or here will s low the action of the error latch f or transien t protect ion by provid ing a Typical
Delay of 13ms/µF.
F UNCTIO NAL DES CRIP TIO N
4
UC1851
UC2851
UC3851
Start/UV Hysteresis Current Output Saturation Characteristics
Osci llator Frequ en cy PWM Outp ut Mini mum Pu lse Wid th
E rror Ampl ifier Op en-Loop Gain and Ph as e Sh utdo w n T iming
5
UC1851
UC2851
UC3851
OPE N-LOO P CIRCUIT
High Pe ak cu rrents a ssocia ted w ith capaci tive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 13 in a single ground point.
Programmab le So ft Start and Restart Delay Circuit
For fur ther ap plication information see UC1840/UC1841
Data Sheets
UC1851 Power MO SFET Drive Inte rfac e
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • F AX (603) 424-3460
No minal Frequency = 1
RTCT = 50kHz
Star t Voltage = 3
R1 + R2 + R3
R2 + R3
+0.2R1 = 12V
UV Fault Voltage
=
3
R1 + R2 + R3
R2 + R3
= 8V
OV Fault Voltage
=
3
R1 + R2 + R3
R3
=
32V
Current Limit = 200mV
Cu rr ent Fault Voltage = 600mV
Duty Cycle Clamp = 50%
@VIN = 15V, Duty Cycle = 48%
@VIN = 30V, Duty Cycle = 24%
6
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