White Electronic Designs CompactFlashTM Cards CFA45 Series CFA45 Series CompactFlashTM CARDS, 8MB to 512MB PRODUCT DESCRIPTION CFA45 series CompactFlashTM cards are built with NAND flash memory components operating as solid-state disk. They comply with the CompactFlashTM card standard and are suitable for use as a data storage memory medium for PCs or other electronic equipment. The read/write unit is 1 sector (512 bytes) sequential access. ISA standard and Read/Write unit is 512 bytes (sector) sequential access High performance: FEATURES Maximum card density is 512 MB 3 variations of mode access PC Card-ATA/True IDE/ I/O Card mode compatible host interface Automatic sensing of PC Card ATA and IDE mode Host data transfer rate 20.0 MB/sec Flash data transfer rate 10.0 MB/sec Memory card mode I/O card mode True-IDE mode Internal self-diagnostic program operates at VCC power on High data reliability Included 256-byte CIS ROM Support the five PC Card ATA addressing modes Host Interface bus width: 8/16-bit Access Endurance: 100,000 Program / Erase cycles Flash Interface bus width: 8-bit Access Support 3 power save mode: standby / idle / active High reliability based on internal ECC (Error Correcting Code) function 2-bit ECC Data reliability is 1 error in 1014 bits read. Auto power down function 2-bit ECC function Operating Voltage: 3.3V and 5.0V Power Consumption Active mode 30 mA (typ.), 40 mA (max.) Idle mode 10 mA Stop mode 400 A CARD BLOCK DIAGRAM VCC GND Internal VCC Data In/Out Host Interface Samsung Samsung NAND Flash Control Controller White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs Card Capacities (CF Type I Blank Housing) Capacity 8 MB 16 MB 32 MB 48 MB 64 MB 96 MB 128 MB 256 MB 512 MB Part Number WED7P008CFA4501C25 WED7P016CFA4501C25 WED7P032CFA4501C25 WED7P048CFA4501C25 WED7P064CFA4501C25 WED7P096CFA4501C25 WED7P128CFA4501C25 WED7P256CFA4501C25 WED7P512CFA4501C25 Sectors/Card 15,616 31,488 62,976 94,464 25,952 188,928 251,904 503,808 1,029,168 Cylinder 122 246 492 738 246 369 492 984 1,021 Sector/Track 32 32 32 32 32 32 32 32 63 Heads 4 4 4 4 16 16 16 16 16 PHYSICAL SPECIFICATION The CFA45 series physical specification complies with CompactFlashTM standard card format. CF CARD SIZE AND OUTLINE 0.8mm 0.6mm 42.8mm 36.4 mm 3.3mm BOTTOM 2x 25.78mm 2x 1mm 2x 12mm Pin # 26 Pin # 50 BOTTOM 1.60mm 1.00mm TOP Pin # 1 1.27mm(Pitch) Pin # 25 White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs INTERFACE SPECIFICATION Signal Pin Assignments Pin NO. Memory Card Mode Signal name I/O I/O Card Mode Signal name I/O True IDE Mode Signal name 1 GND -- GND -- GND I/O -- 2 D3 I/O D3 I/O D3 I/O 3 D4 I/O D4 I/O D4 I/O 4 D5 I/O D5 I/O D5 I/O 5 D6 I/O D6 I/O D6 I/O 6 D7 I/O D7 I/O D7 I/O 7 CE1# I CE1# I CE1# I 8 A10 I A10 I A10 I 9 OE# I OE# I ATASEL# I 10 A9 I A9 I A9 I 11 A8 I A8 I A8 I 12 A7 I A7 I A7 I 13 VCC -- VCC -- VCC -- 14 A6 I A6 I A6 I 15 A5 I A5 I A5 I 16 A4 I A4 I A4 I 17 A3 I A3 I A3 I 18 A2 I A2 I A2 I 19 A1 I A1 I A1 I 20 A0 I A0 I A0 I 21 D0 I/O D0 I/O D0 I/O 22 D1 I/O D1 I/O D1 I/O 23 D2 I/O D2 I/O D2 I/O 24 WP O IOIS16# O IOIS16# O 25 CD2# O CD2# O CD2# O 26 CD1# O CD1# O CD1# O 27 D11 I/O D11 I/O D11 I/O 28 D12 I/O D12 I/O D12 I/O 29 D13 I/O D13 I/O D13 I/O 30 D14 I/O D14 I/O D14 I/O 31 D15 I/O D15 I/O D15 I/O 32 CE2# I CE2# I CE2# I 33 VS1# O VS1# O VS1# O 34 IORD# I IORD# I IORD# I 35 IOWR# I IOWR# I IOWR# I 36 WE# I WE# I WE# I 37 RDY/BSY# O IREQ# O INTRQ O 38 VCC -- VCC -- VCC -- 39 CSEL# I CSEL# I CSEL# I 40 VS2# O VS2# O VS2# O 41 RESET I RESET I RESET# I 42 WAIT# O WAIT# O IORD#Y O 43 INPACK# O INPACK# O INPACK# O 44 REG# I REG# I REG# I 45 BVD2 I/O SPKR# I/O DASP# I/O 46 BVD1 I/O STSCHG# I/O PDIAG# I/O 47 D8 I/O D8 I/O D8 I/O 48 D9 I/O D9 I/O D9 I/O 49 D10 I/O D10 I/O D10 I/O 50 GND -- GND -- GND -- White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Interface Signals Description Symbol A0 - A10 Type INPUT Name and Function D0 - D15 INPUT/ OUTPUT DATA BUS: These signal lines carry the Data, Commands and Status information between the host and the controller. D0 is the LSB of the even byte of the word. D8 is the LSB of the odd byte of the word. This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task File operations occur in byte mode on the low order bus D0-D7 while all data transfers are 16 bit using D0-D15. CE1#, CE2# INPUT CARD ENABLE: CE1# and CE2# are card select signals, active low. These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. CE2# always accesses the odd byte of the word. CE1# accesses the even byte or the Odd byte of the word depending on A0 and CE2#. A multiplexing scheme based on A0, CE1#, CE2# allows 8 bit hosts to access all data on D0-D7. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE mode, CE1# is the chip select for the task file registers while CE2# is used to select the Alternate Status Register and the Device Control Register. OE#, ASTEL INPUT OUTPUT ENABLE, ATA SELECT: OE# is used for the control of data read in Attribute area or Common memory area. To enable True IDE Mode this input should be grounded by the host (in power up). WE# INPUT WRITE ENABLE: WE# is used for the control of data write in Attribute memory area or Common memory area. This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode, this input signal is not used and should be connected to VCC by the host. IORD# INPUT I/O READ: IORD# is used for control of read data in the Task File area. This card does not respond to IORD# until I/O card interface setting up. IOWR# INPUT I/O WRITE: IOWR# is used for control of data write in the Task File area. This card does not respond to IOWR# until I/O card interface setting up. This signal is not used in memory mode. The I/O write strobe pulse is used to clock I/O data on the card data bus into the CF Card controller registers when the CF Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In True IDE mode, this signal has the same function as in PC Card I/O Mode. RDY/ BSY#, IREQ#, INTRQ OUTPUT READY/BUSY, INTERRUPT REQUEST: In memory mode, this signal is set high when the CF Card is ready to accept a new data transfer operation and held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY# signal is held low (busy) until the CF Card has completed its power up or reset function. No access of any type should be made to the CF Card during this time. The RDY/BSY# signal is held high (disabled from being busy) whenever the following condition is true: The CF Card has been powered up with RESET continuously disconnected or asserted. I/O operation - After the CF Card has been configured for I/O operation, this signal is used as Interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE mode, this signal is the active high Interrupt request to the host. CD1#, CD2# OUTPUT CARD DETECTION: CD1# and CD2# are the card detection signals. CD1# and CD2# are connected to ground in this card, so the host can detect if the card is inserted or not. WP, IOIS16# OUTPUT WRITE PROTECT, 16 BIT I/O PORT: In memory card mode, WP is held low because this card does not have a write protect switch. In the I/O card mode, IOIS16# is asserted when Task File registers are accessed in 16-bit mode. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. REG# INPUT ATTRIBUTE MEMORY AREA SELECTION: REG# should be high level during common memory area accessing, and low level during Attribute area accessing. The attribute memory area is located only in an even address, so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses are invalid in the byte access mode. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In True IDE Mode this input signal is not used and should be connected to VCC. BVD2, SPKR#, DASP# INPUT/ OUTPUT BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT: In memory card mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In the I/O card mode, SPKR# is held High because this card does not have digital audio output. In True IDE Mode DASP# is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. ADDRESS BUS: These address lines along with the REG# signal are used to select the following: The I/O port address registers within the PC Storage Card, the memory mapped port address registers within the PC Storage Card, a byte in the Card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A [2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Interface Signals Description cont. Symbol RESET, RESET# Type INPUT Name and Function WAIT#, IORDY OUTPUT WAIT#: This signal outputs low level for the purpose of delaying memory access cycle or I/O access cycle. In True IDE Mode this output signal may be used as IORD#Y. As for this controller, this output is high impedance state constantly. INPACK# OUTPUT INPUT ACKNOWLEDGE: This signal is not used in the memory card mode. The Input acknowledge signal is asserted by the CF Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CF Card and the CPU. In True IDE mode, this output signal is not used and should be connected to VCC at the host. BVD1, STSCHG#, PDIAG# INPUT/ OUTPUT BATTERY VOLTAGE DETECTION, STATUS CHANGE, PASS DIAGNOSTIC: In the memory card mode, BVD1 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In the I/O card mode, STSCHG# is used for changing the status of the Configuration status register in the Attribute area, while the card is set I/O card interface. In True IDE Mode, PDIAG# is the Pass Diagnostic signal in the Master/Slave handshake protocol. VS1#, VS2# OUTPUT VCC VOLTAGE SENSE: These signals are intended to notify the socket of the CF Card's CIS VCC requirement. VS1# is held low and VS2# is not connected in this card. CSEL# INPUT RESET: By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY# signal turns to high level. In True IDE Mode RESET# is the active low hardware reset from the host. CARD SELECT: This signal is not used in the memory card mode and I/O card mode. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. COMPACTFLASHTM/PCMCIA-ATA REGISTER MAPPING ADDRESS. CompactFlashTM/PCMCIA-ATA I/O Mapping Address REG# Primary I/O Secondary I/O L L L L L L L L L L L L L A[10:0] 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H ------3F6H 3F7H A[10:0] 170H 171H 172H 173H 174H 175H 176H 177H ------376H 377H A[3:0] 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H 0DH 0EH 0FH IORD# = L IOWR# = L Read Even Data Error Register Sector Count Sector Number Cylinder Low Cylinder High Drive/Head Status Register Duplicate Read Even Data Duplicate Read Odd Data Duplicate Error Alternate Status Drive Address Write Even Data Feature Register Sector Count Sector Number Cylinder Low Cylinder High Drive/Head Command Duplicate Write Even Data Duplicate Write Odd Data Duplicate Feature Device Control Reserved White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs REG# H H H H H H H H H H H H H H H A10 L L L L L L L L L L L L L H H CompactFlashTM Cards CFA45 Series CompactFlashTM /PCMCIA-ATA Memory Mapping Address A[9:4] X X X X X X X X X X X X X X X A[3] L L L L L L L L H H H H H X X A[2] L L L L H H H H L L H H H X X A[1] L L H H L L H H L L L H H X X A[0] L H L H L H L H L H H L H L H IORD# = L Read Data Error Register Sector Count Sector Number Cylinder Low Cylinder High Drive/Head Status Register Duplicate Read Even Data Duplicate Read Odd Data Duplicate Error Alternate Status Drive Address Read Even Data Read Odd Data IOWR# = L Write Data Feature Sector Count Sector Number Cylinder Low Cylinder High Drive/Head Command Duplicate Write Even Data Duplicate Write Odd Data Duplicate Feature Device Control Reserved Write Even Data Write Odd Data THE ATA REGISTERS AND PCMCIA REGISTERS STATUS REGISTER DIRECTION - This register is read-only by the host. ACCESS RESTRICTION - The contents of this register, except for BSY, will be ignored when BSY is set to one. BSY is valid at all time. The contents of the register and all other Command Block registers are not valid while a device is in the Sleep mode. FUNCTIONAL DESCRIPTION - This register contains the device status. The contents of this register are updated to reflect the current state of the device and the progress of any command being executed by the device. Bit Description 7 BSY 6 DRDY 5 DF 4 DSC 3 DRQ 2 CORR 1 IDX 0 ERR BIT 0 ERR (Error) indicates that an error occurred during execution of the previous command. The Error register has additional information regarding the cause of the error when this bit is asserted. BIT 1 IDX (Index) is vendor specific. BIT 2 CORR (Corrected Data) is used to indicate a correctable data error. The definition of what constitutes a correctable error is vendor specific. BIT 3 DRQ (Data Request) indicates that the device is ready to transfer a word or byte between the host and the device. BIT 4 DSC (Device Seek Complete) indicates that the device heads are settled over a track. BIT 5 DF (Device Fault) indicates a device fault error has been detected. The internal status or internal conditions that causes this error to be indicated is vendor specific. BIT 6 DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes. This bit will be cleared at power on. BIT 7 BSY (Busy) is set whenever the device has control of the command block registers. When the BSY bit is equal to one, the commands written to this register will be ignored by the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series COMMAND REGISTER DIRECTION - This register is write-only by host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. The contents of this register and all other Command Block registers are not valid while a device is in the Sleep mode. FUNCTIONAL DESCRIPTION - This register contains the command code being sent to the device. Command execution begins immediately after this register is written. Bit Description 7 6 5 4 3 2 1 0 Command Code ERROR REGISTER DIRECTION - This register is read-only by host. ACCESS RESTRICTION - The contents of this register shall be valid when BSY and DRQ are equal to zero and ERR is asserted. FUNCTIONAL DESCRIPTION - This register contains the operation status for the current command. Bit Description 7 6 5 4 3 2 1 0 R UNC MC IDNF MCR ABRT TKONF AMNF BIT 0 AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct ID field. BIT 1 TKONF (Track 0 Not Found) indicates the track 0 has not been found during a RECALIBRATE command. BIT 2 ABRT (Aborted Command) indicates the requested command has been aborted because the command code or a command parameter is invalid or some other error has occurred. BIT 3 MCR (Media Change Requested) is used by removable media devices. BIT 4 IDNF (ID Not Found) indicates the requested sector's ID field could not be found. BIT 5 MC (Media Change) is used by removable media devices. BIT 6 UNC (Uncorrectable Data Error) indicate an uncorrectable data error has been encountered. BIT 7 Reserved FEATURE REGISTER DIRECTION - This register is write-only by host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register is command specific. Bit Description 7 6 5 4 3 2 1 0 Command Specific White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs SECTOR NUMBER REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the starting sector number for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 7-0 of the LBA for any media access. Bit Description CHS 7 6 5 4 3 2 1 0 2 1 0 Sector (7:0) LBA 7 6 5 4 3 LBA (7:0) SECTOR COUNT REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register contains the number of sector of data requested to be transferred on a read or write operation between the host and the device. If the value in this register is zero, a count of 256 sectors is specified. Bit Description 7 6 5 4 3 Sector Count 2 1 0 CYLINDER LOW REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 15-8 of the LBA for any media access. Bit Description CHS 7 6 5 4 3 Cylinder (7:0) 2 1 0 2 1 0 LBA 7 6 5 4 3 LBA (15:8) White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs CYLINDER HIGH REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 23-16 of the LBA for any media access. Bit Description CHS 7 6 5 4 3 Cylinder (7:0) 2 1 0 2 1 0 LBA 7 6 5 4 3 LBA (15:8) DEVICE/HEAD REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register selects the device, defines address translation as CHS or LBA, and provides the head address if CHS mode or LBA (27:24) if LBA mode. Bit Description CHS (cylinder-head-sector) 7 1 6 LBA 5 1 4 DEV 7 1 6 LBA 5 1 4 DEV 3 HS3 2 HS2 1 HS1 0 HS0 1 0 LBA (logic block address) 3 LBA 2 (27:24) BIT 0~3 If LBA is equal to zero (CHS), these contain the head address of the starting CHS address. The HS3 bit is the most significant bit. If LBA is equal to one (LBA), these bits represent bits 27 through 24 of the LBA. BIT 4 DEV is the device address. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected. BIT 5 Bit 5 is set to one for backward compatibility. BIT 6 LBA mode if this bit is set to one, otherwise, CHS mode. BIT 7 Bit 7 is set to one for backward compatibility. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs DATA REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRUCTIONS - This register can be written or the content is valid on read when DRQ is set to one. FUNCTIONAL DESCRIPTION - The data register is 16-bit wide. Bit Description 15 14 13 12 11 10 9 8 3 2 1 0 2 Configuration Index 1 0 Data (15:8) 7 6 5 4 Data (7:0) PCMICA CONFIGURATION OPTION REGISTER DIRECTION - This register is read-only by host. FUNCTION DESCRIPTION - Direct map to 0x200H in the Attribute Memory. Bit Description 7 SRESET BIT 0~5 6 LevlReq 5 4 3 Configuration Index: 0 : common memory mode 1 : Independent IO mode 2 : Primary IO mode 3 : Secondary IO mode BIT 6 LevlReq (level Mode IREQ) : Level Mode Interrupts are selected when this bit is set to one, otherwise it is Pulse Mode Interrupts. BIT 7 SRESET (Soft Reset): Setting this bit to one places the card in the reset state. This is equivalent to assertion of the RESET signal. PCMICA CARD CONFIGURATION AND STATUS REGISTER DIRECTION - This register is bi-directional for the drive and host. FUNCTION DESCRIPTION - Direct map to 0x202H in the Attribute Memory. Bit Description 7 SCDect BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 6 SigChg 5 IOis8 4 ResrV 3 SPKR/DASP 2 PwrDn 1 Intr 0 ResrV Reserved Intr (Interrupt Request Pending) : The real time status of the host interrupt signal pin. PwrDn (Power Down): This bit will enable the power down mode. SPKR/DASP: Setting this bit to 1 will enable DASP- to the BVD2 pin of the PCMCIA connector, otherwise, the BVD2 will be held at high-impedance. ResrV: Reserved bit must be 0. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs BIT 5 BIT 6 BIT 7 IOis8 (I/O Cycles Occur Only as 8-bit Transfer): When the host can provide I/O cycle only using the D7:D0 data path, the PCMCIA software will set this bit to 1. SigChg (Signal Change Enable/Disable): If this bit is set to one, the Signal Changed output is enabled. SCDect (Status Change Detected): This bit indicates that at least one bit of the Pin replacement Register is set one. PCMICA PIN REPLACEMENT REGISTER DIRECTION - This register is read-only by host. FUNCTION DESCRIPTION - Direct map to 0x204H in the Attribute Memory. Bit Description 7 ResrV 6 ResrV 5 CRdy 4 3 CWProt 2 ResrV ResrV 1 CSRdy 0 CSWProt BIT 0 CSWProt (Current State of Write Protect) : This bit represents the current the state of the Write Protect. BIT 1 CSRdy (Current State of Ready) : This bit represents the internal state of the READY signal. BIT 2~3 Reserved. BIT 4 CWProt (Change Write Protect) : This bit is set to one when CSWProt changes state. BIT 5 CRdy (Changed Ready) : This bit is set to one when CSRdy changes state. BIT 6~7 ResrV : Reserved bit must be 0. PCMICA SOCKET AND COPY REGISTER DIRECTION - This register is bi-directional for the drive and host. FUNCTION DESCRIPTION - Direct map to 0x206H in the Attribute Memory. Bit Description 7 ResrV 6 5 4 Copy Number 3 BIT 0~2 Socket Number : The first Socket is numbered 0. BIT 3~5 Copy Number BIT 6~7 ResrV : Reserved bit must be 0. 2 1 Socket Number 0 White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Symbol VCC VIN IIN TSTG Parameter Supply voltage Input voltage DC input current Storage temperature Ratings - 0.3 to + 7.0 - 0.3 to VCC + 0.3 - 10 - 40 to + 80 Unit V V mA C Recommended Operating Conditions Symbol VCC Parameter DC supply voltage 5V 3.3V Storage temperature Ta Ratings 4.5 to + 5.5 3.0 to 3.6 0 to + 60 Unit V V C D.C. Electrical Characteristics @ 3.3V (Ta = 0 to +60C, VCC = 3.3V 5%) Symbol VIH VIL VT VT+ VTIIH IIL VOH VOL IOZ IDD Iidle Ids Parameter High level input voltage Low level input voltage Switching threshold Switching trigger, positive-going threshold Switching trigger, negative-going threshold High level input current Low level input current Conditions CMOS CMOS CMOS CMOS Min 2.0 Typ Max 1.0 1.4 2.0 CMOS 1.0 Input buffer Input buffer with pull-up Input buffer Input buffer with pull-up VIN = VCC VIN = VSS High level output voltage Low level output voltage Tri-state output leakage current Maximum operating current Idle current Stop current IOH = -8 mA IOL = 8 mA VOUT = VSS or VCC VCC = 5.0V, fMCK = 20 MHz -10 10 -10 -160 2.4 Unit V V V V V 30 -30 -10 30 10 60 10 -10 0.4 10 40 10 300 uA uA V V uA mA mA uA White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Electrical Characteristics @ 5V (Ta = 0 to 60C, VCC = 5V 10%) Symbol VIH High level input voltage CMOS TTL VIL Low level input voltage CMOS TTL VT Switching threshold CMOS TTL VT+ Switching trigger, positive-going threshold CMOS TTL VT- Switching trigger, negative-going threshold CMOS TTL IIH High level input current IIL VOH VOL IOZ IDD Iidle Ids Parameter Low level input current Conditions Min 3.5 2.0 Typ Max Unit V 1.5 0.8 V 2.5 1.4 V 4.0 2.0 1.0 0.8 Input buffer Input buffer with pull-up Input buffer Input buffer with pull-up VIN = VCC VIN = VSS High level output voltage Low level output voltage Tri-state output leakage current Maximum operating current Idle current Stop current IOH = -8 mA IOL = 8 mA VOUT = VSS or VCC VCC = 5.0V, fMCK = 24 MHz -10 10 -10 -100 2.4 50 -50 -10 30 V V 10 100 10 -10 0.4 10 40 10 400 uA uA V V uA mA mA uA Environmental and Reliability Specifications ITEM Vibration Shock Relative Humidity (non-condensing) MTBF Endurance Data Reliability SPECIFICATION 15G peak to peak Max. 15G peak to peak Max. 2,000G Max. 2,000G Max. 8% ~ 95% 8% ~ 95% > 1,000,000 hours 100,000 erase program cycles < 1 non-recoverable error in 1014 bits read Operating Non-Operating Operating Non-Operating Operating Non-Operating Operating Operating Operating White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series INTERFACE SIGNAL TIMING There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard. The PC Card conforms to the timing in that reference document. PC CARD INTERFACE Attribute Memory Read Timing Parameter Symbol IEEE Symbol Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable Time from OE# Address Setup Time Output Enable Time from CE Output Enable Time from OE# Data Valid from Address Change tC(R) tA(A) tA(CE) tA(OE#) tDIS(CE) tDIS(OE#) tSU(A) tEN(CE) tEN(OE#) tV(A) tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAVWL tELQNZ tGLQNZ tAXQX 300ns Min. ns 300 Max. ns 300 300 150 100 100 30 5 5 0 NOTE: All times are in nanosecond. DOUT signifies data provided by the PC Card to the system. The CE# signal or both the OE# signal & the WE# signal must be de-asserted between consecutive cycle operations. ATTRIBUTE MEMORY READ TIMING DIAGRAM tC (R) An tA (A) REG# tSU (A) CE# tV (A) tA (CE) tEN (CE) tDIS (CE) tA (OE) OE# tDIS (OE) tEN (OE) DOUT White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs Attribute Memory Write Timing Note: A host cannot write to CIS. This timing is specified only for the write to Configuration Register. Parameter Symbol IEEE Symbol Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Data Setup Time for WE Data Hold Time tC(W) tW(WE) tSU(A) tREC(WE) tSU(D-WEH) tH(D) tAVAV tWLWH tAVWL tWMAX tDVWH tWMDX 250ns Min. ns 250 150 30 30 80 30 Max. ns NOTE: All times are in nanosecond. DIN signifies data provided by the system to the PC Card. ATTRIBUTE MEMORY WRITE TIMING DIAGRAM tC (W) REG# An tREC (WE) tSU (A) WE# tW (WE) tSU (D-WEH) tH (D) CE# OE# DOUT Data In Valid White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 15 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Common Memory Read Timing Parameter Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE Wait Delay Falling from OE Data Setup for Wait Release Wait Width Time Symbol tA (OE) tDIS (OE) tSU (A) tH (A) tSU (CE) tH (CE) tV (WT-OE) tV (WT) tW (WT) IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH tGLWTV tQVWTH tWTLWTH Min. ns Max. ns 125 100 30 20 0 20 35 0 350 NOTE: The maximum load on WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. DOUT signifies data provided by the PC Card to the system. The WAIT# signal may be ignored if the OE# cycle-to-cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. COMMON MEMORY READ TIMING DIAGRAM An tSU (A) tH (A) REG# CE# tH (CE) tSU (CE) tDIS (CE) tA (OE) OE# tW (WT) WAIT# tV (WT-OE) tDIS (OE) tV (WT) DOUT White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs Common Memory Write Timing Parameter Data Setup before WE Data Hold following WE WE# Pulse Width Address Setup Time CE Setup before WE Write recovery Time Address Hold Time CE Hold following WE Wait Delay Falling from WE WE# High from Wait Release Wait Width Time Symbol tsu (D-WEH) th (D) tw (WE) tsu (A) tsu (CE) trec (WE) th (A) th (CE) tv (WT-WE) tv (WT) tw (WT) IEEE Symbol tDVWH tlWMDX tWLWH tAVWL tELWL tWMAX tGHAX tGHEH tWLWTV tWTHWH tWTLWTH Min. ns 80 30 150 30 0 30 20 20 Max. ns 35 0 350 NOTE: The maximum load on WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. DIN signifies data provided by the system to the PC Card. The WAIT# signal may be ignored if the WE# cycle-to-cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. COMMON MEMORY WRITE TIMING DIAGRAM An tSU (A) tH (A) REG# tH (CE) tSU (CE) CE# tREC (WE) tW (WE) OE# tW (WT) WAIT# tV (WT) tV (WT-WE) tH (D) tSU (D-WEH) DIN DIN Valid White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 17 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs I/O Input (Read) Timing Parameter Data Delay after IORD Data Hold following IORD IORD# Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG# Setup before IORD# (IORD) REG# Hold following IORD INPACK# Delay Falling from IORD INPACK# Delay Rising from IORD IOIS16# Delay Falling from Address IOIS16# Delay Rising from Address Wait Delay Falling from IORD Data Delay from Wait Rising Wait Width Time Symbol td (IORD) th (IORD) tw (IORD) tsuA (IORD) thA (IORD) tsuCE (IORD) thCE (IORD) tsuREG thREG (IORD) tdfINPACK (IORD) tdrINPACK (IORD) tdfIOIS16 (ADR) tdrIOIS16 (ADR) tdWT (IORD) td (WT) tw (WT) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH tlGLWTL tWTHQV tWTLWTH Min. ns 0 165 70 20 5 20 5 0 0 Max. ns 100 45 45 35 35 35 0 350 NOTE: The maximum load on WAIT#, INPACK# and IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is 0nsec, but minimum IORD# width must still be met. DOUT signifies data provided by the PC Card to the system. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. I/O READ TIMING DIAGRAM An tSU (IORD) tHA (IORD) tSUREG (IORD) REG# tHRE (IORD) tSUCE (IORD) CE# tHCE (IORD) tWIORD IORD# tDRINPACK (IORD) tDFINPACK (IORD) INPACK# tDRIOIS16 (ADR) tD (IORD) IOIS16# tDFIOIS16 (ADR) WAIT# tD (WT) tDWT (IORD) tW (WT) tH (IORD) DOUT White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 18 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series I/O INPUT (WRITE) TIMING Parameter Symbol IEEE Symbol Min. ns Data Setup before IOWR Data Hold following IOWR IOWR# Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR REG# Setup before IOWR REG# Hold following IOWR IOIS16# Delay Falling from Address IOIS16# Delay Rising from Address Wait Delay Falling from IOWR IOWR# high from Wait high Wait Width Time tsu (IOWR) th (IOWR) tw (IOWR) tsuA (IOWR) thA (IOWR) tsuCE (IOWR) thCE (IOWR) tsuREG (IOWR) thREG (IOWR) tdfIOIS16 (ADR) tdrIOIS16 (ADR) tdWT (IOWR) tdrIOWR (WT) tw (WT) tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tRGLIWL tlWHRGH tAVISL tAVISH tlWLWTL tWTJIWH tWTLWTH 60 30 165 70 20 5 20 5 0 Max. ns 35 35 35 0 350 NOTE: The maximum load on WAIT#, INPACK#, and IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is 0nsec, but minimum IOWR# width must still be met. DIN signifies data provided by the system to the PC Card. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. I/O WRITE TIMING DIAGRAM An tSU (IOWR) tHA (IOWR) tSUREG (IOWR) REG# tHRE (IOWR) tSUCE (IOWR) CE# tHCE (IOWR) tWIORD IOWR# tDRIOIS16 (ADR) IOIS16# tDFIOIS16 (ADR) tSU (IOWR) tW (WT) WAIT# tDWT (IOWR) tDRIOWR (WT) tH (IOWR) DIN White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 19 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs IDE MODE INTERFACE IDE Mode Read Timing Parameter Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Symbol td (IORD) th (IORD) tw (IORD) tsuA (IORD) thA (IORD) tsuCE (IORD) thCE (IORD) tdfIOIS16 (ADR) tdrIOIS16 (ADR) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tAVISL tAVISH Min. ns Max. ns 100 0 165 70 20 5 20 35 35 NOTE: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is 0nsec, but minimum IORD# width must still be met. DOUT signifies data provided by the PC Card to the system. IDE MODE READ TIMING DIAGRAM An tSU (IORD) tHA (IORD) tSUCE (IORD) CE# tHCE (IORD) tWIORD IORD# tDRIOIS16 (ADR) tD (IORD) IOIS16# tDFIOIS16 (ADR) tH (IORD) DOUT White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 20 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs IDE Mode Write Timing Parameter Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR IOIS16# Delay Falling from Address IOIS16# Delay Rising from Address Symbol tsu(IOWR) th(IOWR) twI(OWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tAVISL tAVISH Min. ns 60 30 165 70 20 5 20 Max. ns 35 35 NOTE: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT# high to IOWR# high is 0nsec, but minimum IOWR# width must still be met. DIN signifies data provided by the system to the PC Card. IDE MODE WRITE TIMING DIAGRAM An tSU (IOWR) tHA (IOWR) tSUCE (IOWR) CE# tHCE (IOWR) tWIOWR IOWR# tDRIOIS16 (ADR) IOIS16# tDFIOIS16 (ADR) tSU (IOWR) tH (IOWR) DIN White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 21 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Reset Timing Parameter Level Set before Power On Power on Reset Reset time Symbol tset tpor trst Min 1 Typ Max 10 10 Unit ms ms ms RESET TIMING DIAGRAM VCC POR (Internal) Reset Pin t RST t POR RDY/BSY# Pin tSET OE# Pin CSEL# Pin POWER ON RESET CHARACTERISTICS All card status are reset automatically when VCC voltage gOE#s over about 2.3 V. Parameter CE# setup time VCC rising up time Symbol tsu(VCC) tpr Min 100 0.1 POWER ON RESET TIMING Typ -- -- Max -- 100 Unit ms ms Test conditions t PR VCC tSU(VCC) CE1#, CE 2# Attention for Card Use Please notice that the card insertion/removal should be executed after card internal operations are completed (status register bit 7 turns from "1" to "0"). In the reset or power off, all register information is cleared. Before the card insertion VCC cannot be supplied to the card. After confirmation that CD1#, CD2# pins are inserted, supply VCC to the card. All card status are cleared automatically when VCC voltage turns below about 2.5V. Notice that the card insertion/removal should not be executed during host is active, if the card is used in true IDE mode. OE# must be kept at the VCC level during power on reset in memory card mode and I/O card mode. OE# must be kept constantly at the GND level in True IDE mode. After the card hard reset, soft reset, or power on reset, the card cannot access during +READY pin is "low" level. Unused pins of data bus (D0 to D15) signals should not be opened. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 22 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs CARD INFORMATION STRUCTURE (CIS) & IDENTIFY DRIVE (ID) INFORMATION Identify Drive Information Word 0 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62-127 128 129-159 160 161-255 8MB 848A 007A 0000 0004 0000 0200 0020 0000 3D00 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 007A 0004 0020 3D00 0000 0100 3D00 0000 All 0000 0000 All 0000 0000 All 0000 16MB 848A 00F6 0000 0004 0000 0200 0020 0000 7B00 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 00F6 0004 0020 7B00 0000 0100 7B00 0000 All 0000 0000 All 0000 0000 All 0000 32MB 848A 01EC 0000 0004 0000 0200 0020 0000 F600 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 01EC 0004 0020 F600 0000 0100 F600 0000 All 0000 0000 All 0000 0000 All 0000 48MB 848A 02E2 0000 0004 0000 0200 0020 0001 7100 0000 All 2020 0000 0002 0004 *1 2 0004 0000 0200 0000 0200 0000 0001 02E2 0004 0020 7100 0001 0100 7100 0001 All 0000 0000 All 0000 0000 All 0000 64MB 848A 00F6 0000 0010 0000 0200 0020 0001 EC00 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 00F6 0010 0020 EC00 0001 0100 EC00 0001 All 0000 0000 All 0000 0000 All 0000 96MB 848A 0171 0000 0010 0000 0200 0020 0002 E200 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 0171 0010 0020 E200 0002 0100 E200 0002 All 0000 0000 All 0000 0000 All 0000 128MB 848A 01EC 0000 0010 0000 0200 0020 0003 D800 0000 All 2020 0000 0002 0004 1 *2 0004 0000 0200 0000 0200 0000 0001 01EC 0010 0020 D800 0003 0100 D800 0003 All 0000 0000 All 0000 0000 All 0000 256MB 848A 03D8 0000 0010 0000 0200 0020 0007 B000 0000 All 2020 0000 0002 0004 *1 *2 0004 0000 0200 0000 0200 0000 0001 03D8 0010 0020 B000 0007 0100 B000 0007 All 0000 0000 All 0000 0000 All 0000 Note 1. Firmware Version: Rev 1.15 (52 65 76 20 31 2E 31 35) 2. Model Number: SAMSUNG CF/ATA (53 41 4d 53 55 4e 47 20 43 46 2f 41 54 41 20 20 20 20 20 20) White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 23 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Card Information Structure AttributeOffset 000h 002h 004h Data 01 04 DF 006h 4A 008h 00Ah 00Ch 00Eh 010h 012h 01 FF 1C 04 02 D9 014h 016h 018h 01Ah 01Ch 01Eh 01 FF 18 02 DF 01 020h 022h 024h 026h 028h 02Ah 02Ch 20 04 CE 00 00 00 15 02Eh 030h 032h 034h 036h 038h 03Ah 03Ch 03Eh 040h 042h 044h 046h 048h 04Ah 04Ch 04Eh 20 04 01 53 41 4D 53 55 4E 47 20 20 20 20 20 20 00 7 6 5 4 CISTPL_DEVICE 3 2 1 Device Type Code Dh=I/O X 9h W 1 Speed 7h 2h 0 Device Size List End Marker CISTPL_DEVICE_OC 0 Reserved, 0 Device Type Code Dh=I/O Device Size List End Marker CISTPL_JEDEC_C W 1 VccU Speed 1h PCMCIA Manufacture 's ID PCMCIA Code for PC Card-ATA No Vpp Required CISTPL_MANFID M Description of Contents Device Info Tuple Link is 4bytes I/O device, No Write Protects, Device Speed = 400ns CIS Function Tuple Code Link to next tuple Device ID WPS, Speed 2Kbyte of address Space End of Devices Other Condition Device Info Tuple Link is 4bytes 3.3V VCC Operation I/O device, No Write Protects,Device Speed=250ns Device Size End Marker Tuple Code Link to next tuple OC Info Device ID WPS, Speed 2Kbyte of address Space End of Devices JEDEC ID Common Mem Link is 2bytes First Byte of JEDEC ID Second Byte of JEDEC ID Device Size End Marker Tuple Code Link to next tuple JEDEC ID of Device 1 JEDEC ID Manufacture ID String Link is 4bytes Tuple Code Link to next tuple TPLMID_MANF TPLMID_MANF TPLMID_CARD TPLMID_CARD Tuple Code PC Card Manufacture's ID Code Manufacture Information CISTPL_VERS_1 Major Version Number Minor Version Number Manufacture Information End of Manufacture Information Level 1 Version/Product Information Link is 20bytes PCMCIA 2.1 JEIDA 4.2 S A M S U N G Name of Manufacture Null Terminator Link to next tuple TPLLV1_MAJOR TPLLV1_MINOR String 1 End String 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 24 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Card Information Structure cont. AttributeOffset 050h 052h 054h 056h 058h 05Ah 05Ch 05Eh 060h 062h 064h 066h 068h 06Ah 06Ch 06Eh 070h 072h 074h 076h 078h 07Ah 07Ch 07Eh 080h 082h 084h 086h 088h 08Ah 08Ch 08Eh 090h Data 52 65 76 20 31 2E 31 35 20 20 20 20 20 00 00 FF 21 02 04 01 22 02 01 01 22 03 02 0C 0F 1A 05 01 03 7 6 5 4 Product Information 3 2 092h 094h 096h 098h 09Ah 09Ch 00 02 0F 1B 08 C0 TPCC_RADR TPCC_RADR RFU S P CISTPL_CFTABLE_ENTRY I D 09Eh C0 M W R 1 0 End of Product Information End of CIS Revision Number List End Marker CISTPL_FUNCID IC Card Function Code RFU, 0 CISTPL_FUNCE R P Disk Function Extension Tuple Type Interface Type Code CISTPL_FUNCE Disk Function Extension Tuple Type RFU U S V R I E N P3 P2 P1 P0 CISTPL_CONFIG RFSZ TPCC_LAST RMSZ RASZ B V CIS Function String 2 Null Terminator Null Terminator End String 2 Function ID Tuple Link is 2bytes Fixed Disk Function System Initialization Bit Mask, Power-On-Self Test Function Extention Tuple Link is 2bytes Disk Device Interface PCCard-ATA Interface Function Extention Tuple Link is 3bytes Disk Device Interface Silicon/Rotating, ID/SN is unique Auto, Idle, Standby, Sleep Mode supported Configuration Tuple Link is 5bytes Size of Fields Byte Entry Index 03h Configuration Registers are located at 200h C I Configuration Entry Number W P Description of Contents R e v 1 . 1 Firmware Revision 5 Interface Type 4 Configuration Registers are present Configuration Entry Tuple Link is 8bytes Memory Mapped I/O, D: Default Configuration, I: Interface Byte Follows Memory Only Interface, Bvd & WP not used, RDY/ BSY# & Wait used for Memory Cycle End Marker Tuple Code Link to next tuple TPLFID_FUNCTION TPLFID_SYSINIT Tuple Code Link to next tuple TPLFE_TYPE TPLFE_DATA Tuple Code Link to next tuple TPLFE_TYPE TPLFE_DATA TPLFE_DATA Tuple Code Link to next tuple TPCC_SZ Last entry of Configuration table Location of Config Registers TPCC_RMSK Tuple Code Link to next tuple TPCE_INDX TPCE_IF White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 25 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Card Information Structure cont. AttributeOffset 0A0h Data A1 7 M 0A2h 01 R 0A4h 0A6h 0A8h 0AAh 0ACh 0AEh 0B0h 0B2h 55 08 00 20 1B 06 00 01 0B4h 21 0B6h 0B8h 0BAh 0BCh 0Beh 0C0h B5 1E 4D 1B 0A C1 0C2h 6 5 MS DI PI 4 I R Q AI 3 IO 2 1 T Power SI H L V V X Ah 5h Length in 256 bytes pages(LSB) Length in 256 bytes pages(MSB) X R P R A Twin CISTPL_CFTABLE_ENTRY 0 N V I M D Configuration Entry Number MS IR IO T Power Q R DI PI AI SI H L N V V V X 6h 5h X Eh(30d) X 9h 5h CISTPL_CFTABLE_ENTRY I D Configuration Entry Number 41 W R 0C4h 99 M 0C6h 01 R DI 0C8h 0CAh 55 64 X R Ah Bus 16/8 H V 5h I/O Addr Lines 0CCh F0 S P M 0CEh 0D0h 0D2h FF FF 20 0D4h 0D6h 0D8h 0DAh 1B 06 01 01 P PI L B Interface Type IR Q AI IO T Power SI V B L V I N V N A T R O CISTPL_CFTABLE_ENTRY X I M R P D MS Configuration Entry Number IR IO T Power Q Description of Contents VCC power-description structure only, MS: Single 2-byte length specified M: Misc field structure is present Nominal Operating Supply Voltage, No Extension CIS Function TPCE_FS VCC Nominal is 5V Length of Mem Space is 2KB Start at 0 on Card Power Down Configuration Entry Tuple Link is 6bytes VCC Nominal Value TPCE_MS Length LSB TPCE_MS Length MSB TPCE_MI Tuple Code Link to next tuple TPCE_INDX TPCE_FS VCC power-description structure only Power Parameters for Vcc Maximum Current required averaged over 10ms, Nominal Operating Supply Voltage, With Extension 1V x3 VCC Nominal is 3.3V Peak I is 45mA Configuration Entry Tuple Link is 10bytes I/O Mapped Contiguous 16, Registers Configuration, D: Default, Configuration, I: Interface Byte Follows I/O Interface, Bvd & WP not used, RDY/BSY# active, Wait not used for memory access Misc & IRQ field are present, VCC power-description structure only Nominal Operating supply Voltage TPCE_PD VCC Nominal is 5V Support 16/8 bit I/O access, I/O Address Lines are 16 IRQ Sharing S: Share Logic active P: Pulse IRQ supported L: Level IRQ supported M: Bit Mask of IRQ IRQ Levels to be routed 0-7 recommended IRQ Levels to be routed 8-15 recommended Power Down supported VCC Nominal Value TPCE_IO Configuration Entry Tuple Link is 6 bytes Tuple Code Link to next tuple TPCE_INDX TPCE_FS VCC power-description structure only VCC Nominal Value Peak I Value Tuple Code Link to next tuple TPCE_INDX TPCE_IF TPCE_FS TPCE_PD TPCE_IR TPCE_IR Mask Extension TPCE_IR Mask Extension TPCE_MI White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 26 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Card Information Structure cont. AttributeOffset 0DCh Data 21 7 R 6 DI 0DEh 0E0h 0E2h 0E4h 0E6h 0E8h 0EAh B5 1E 4D 1B 0F C2 41 X 6h 5h X 1Eh(30d) X 9h 5h CISTPL_CFTABLE_ENTRY I W D R 0ECh 99 M MS 0EEh 01 R DI 0F0h 0F2h 55 EA X R Ah Bus 16/8 0F4h 61 Size of length 0F6h 0F8h 0FAh 0FCh 0FEh 100h 102h F0 01 07 F6 03 01 EE Start of I/O Address Block First(LSB) Start of I/O Address Block First(MSB) First I/O Range Length Start of I/O Address Block Second(LSB) Start of I/O Address Block Second(MSB) Second I/O Range Length S P L M V B I N 104h 20 X 106h 108h 10Ah 10Ch 1B 06 02 01 4 AI 3 SI 2 H V 1 L V 0 N V 10Eh 21 110h 112h 114h 116h 118h B5 1E 4D 1B 0F Configuration Entry Number P B Interface Type PI IR Q AI IO T Power SI H V L V N V 5h I/O AddrLines Size of address Number of I/O Address Ranges R A T O CISTPL_CFTABLE_ENTRY I M R 5 PI P D Configuration Entry Number MS IR I T Power Q O R DI PI AI SI H L N V V V X 6h 5h X 1Eh(30d) X 9h 5h CISTPL_CFTABLE_ENTRY Description of Contents Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 1Vx3 VCC Nominal is 3.3V Peak I is 45mA Configuration Entry Tuple Link is 15bytes I/O Interface, Bvd & WP not used, RDY/BSY# active, Wait not used for memory access Misc & IRQ field are present, VCC power-description structure only Nominal Operating supply Voltage CIS Function TPCE_PD VCC Nominal Value Peak I Value Tuple Code Link to next tuple TPCE_INDX TPCE_IF TPCE_FS TPCE_PD VCC Nominal is 5V I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field VCC Nominal Value TPCE_IO IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported Power Down supported TPCE_IR Configuration Entry Tuple Link is 6bytes Tuple Code Link to next tuple TPCE_INDX TPCE_FS VCC power-description structure Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 1Vx3 VCC Nominal is 3.3V Peak I is 45mA Configuration Entry Tuple Link is 15bytes I/O Range Description Byte TPCE_MI TPCE_PD VCC Nominal Value Peak I Value Tuple Code Link to next tuple White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 27 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Card Information Structure cont. AttributeOffset 11Ah 11Ch Data C3 41 7 I W 6 D R 11Eh 99 M MS 120h 01 R DI 122h 124h 55 EA X R Ah Bus 16/8 126h 61 128h 12Ah 12Ch 12Eh 130h 132h 134h 70 01 07 76 03 01 EE Size of Size of Number of I/O length address Address Ranges Start of I/O Address Block First (LSB) Start of I/O Address Block First (MSB) First I/O Range Length Start of I/O Address Block Second(LSB) Start of I/O Address Block Second(MSB) Second I/O Range Length S P L M V B I N 136h 20 X 138h 13Ah 13Ch 13Eh 1B 06 03 01 140h 21 142h 144h 146h 148h 14Ah 14Ch B5 1E 4D 14 00 FF PI IR Q AI I O SI T H V 5h I/O AddrLines Power L V N V R A T O CISTPL_CFTABLE_ENTRY I M R 5 4 3 2 1 0 Configuration Entry Number P B Interface Type P D Configuration Entry Number MS IR I T Power Q O R DI PI AI SI H L N V V V X 6h 5h X Eh(30d) X 9h 5h CISTPL_NO_LINK No Bytes Following End of CIS Tuple Chain Description of Contents I/O Interface, Bvd & WP not used, RDY/BSY# active, Wait not used for memory access Misc & IRQ field are present, VCC CIS Function TPCE_INDX TPCE_IF TPCE_FS Nominal Operating supply Voltage TPCE_PD VCC Nominal is 5V I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field VCC Nominal Value TPCE_IO IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported Power Down supported TPCE_IR Configuration Entry Tuple Link is 6bytes Tuple Code Link to next tuple TPCE_INDX TPCE_FS VCC power-description structure only Nominal Operating supply Voltage, 1Vx3 VCC Nominal is 3.3V Peak I is 45mA No Link to Common Memory Link Length is 0 byte End of CIS I/O Range Description Byte TPCE_MI TPCE_PD VCC Nominal Value Peak I Value Tuple Code Link to next tuple Tuple Code White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 28 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs TRUE IDE to CompactFlashTM INTERFACE True IDE No(#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CompactFlashTM 40pin RESET# GND D7 D8 D6 D9 D5 D10 D4 D11 D3 D12 D2 D13 D1 D14 D0 D15 GND (keypin) DMACK# GND IOWR# GND IORD# GND IORDY CSEL DMACK# GND IREQ IOIS16# A1 PDIAG# A0 A2 CS0# CS1# DASP# GND No(#) 41 1,8,9,11,12,14,15,16,17,50,(39) 6 47 5 48 4 49 3 27 2 28 23 29 22 30 21 31 1,8,9,11,12,14,15,16,17,50,(39) 68pin RESET GND, A10-A3, OE#, CSEL# (39) D7 D8 D6 D9 D5 D10 D4 D11 D3 D12 D2 D13 D1 D14 D0 D15 GND, A10-A3, OE#, CSEL#(39) 44 1,8,9,11,12,14,15,16,17,50,(39) 35 1,8,9,11,12,14,15,16,17,50,(39) 34 1,8,9,11,12,14,15,16,17,50,(39) 42 39 44 1,8,9,11,12,14,15,16,17,50,(39) 37 24 19 46 20 18 7 32 45 1,8,9,11,12,14,15,16,17,50,(39) INPACK# GND, A10-A3, OE#, CSEL#(39) IOWR# GND, A10-A3, OE#, CSEL#(39) IORD# GND, A10-A3, OE#, CSEL#(39) WAIT# CSEL REG# GND, A10-A3, OE#, CSEL#(39) RDY/BSY# WP A1 BVD1 A0 A2 CS0# CS1# BVD2 GND, A10-A3, OE#, CSEL#(39) White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 29 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series PRODUCT MARKING WED 7P016CFA4500C25 C995 0322 COMPANY NAME PART NUMBER LOT CODE/TRACE NUMBER DATE CODE PART NUMBERING 7 P 256 CFA45 00 C 25 CARD TECHNOLOGY 7 8 FLASH SRAM PC CARD P R Standard Ruggedized CARD CAPACITY 256 256MB CARD FAMILY AND VERSION PACKAGING OPTION 00 Standard CF, WEDC logo TEMPERATURE RANGE C = Commercial 0C to +70C CARD ACCESS TIME 25 250ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 30 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs ORDERING INFORMATION 7P XXX CFA45 SS T ZZ XXX (unformatted capacity) 008 8MB 016 16MB 032 32MB 048 48MB 064 64MB 096 96MB 128 128MB 256 256MB 512 512MB CFA45 SS T ZZ Samsung based CompactFlashTM 00 01 CompactFlashTM Type I WEDC logo CompactFlashTM Type I Blank C Commercial Temperature Range 25 250ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2003 Rev. 0 31 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com