CCD Area Image Sensor
MN3711CFP
4.5mm (1/4 inch) 510H CCD Area Image Sensor
Overview
The MN3711CFP is a 4.5mm (1/4 inch) Interline Transfer CCD (IT-
CCD) solid state image sensor device.
This device uses photodiodes in the optoelectric conversion section
and CCDs for signal read out. The electronic shutter function has
made possible an exposure time of 1/10000 seconds. Further, this
device has the features of high sensitivity, low noise, broad dynamic
range, and low smear.
This device has a total of 270K pixels (542 horizontal × 494 vertical)
and provides stable and clear images with a resolution of 330
horizontal TV-lines and 350 vertical TV-lines.
Features
Total number of pixels: 542 (horizontal) × 494 (vertical)
High sensitivity
Low noise
Broad dynamic range
Low smear
Low image lag
Electronic shutter function present
No image distortion
Small size enables design of compact equipment
High reliability
14 Pin DIL ceramic package
Pin Assignments
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OD
ø
RD
VO
LG
ø
ø
PW
ø
ø
ø
ø
PT
Sub
R
H2
H1
V4
V3
V2
V1
MN3711CFP
(Top View)
C14 WDIP014-P-0400
Type No. Size System Color or B/W
MN3711CFP
4.5mm (1/4 inch)
NTSC Color
Applications
Compact lightweight camcoders
Cameras for surveillance, measurement, and
medical use
CCD Area Image Sensor
MN3711CFP
Block Diagram
13
12
11
10
14
14
5
4
1
3
8
9
267
PW
GND
VO
OD
RD
øRøH2 øH1
øV4
øV3
øV2
øV1
Sub
PT
(2 columns OB+512 columns valid area+28 columns OB)
(2 dummies+1 OB+492+1 OB+1 dummy)
(Internal connection)
(Internal bias) LG
Vertical shift register
Output section
Photodiode
Horizontal shift register
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
Symbol
OD
ø
RD
VO
LG
ø
ø
R
H2
H1
Output drain
Reset pulse
Reset drain
Video output
Output load transistor gate
Horizontal register clock pulse (2)
Horizontal register clock pulse (1)
Descriptions Pin No.
8
9
10
11
12
13
14
Symbol
Sub
PT
ø
ø
ø
ø
PW
Substrate
P-well for protection circuit
Vertical shift register clock pulse (1)
Vertical shift register clock pulse (2)
Vertical shift register clock pulse (3)
Vertical shift register clock pulse (4)
P-well
Descriptions
V1
V2
V3
V4
MN3711CFP
CCD Area Image Sensor
Absolute Maximum Ratings and Operating Conditions
Note 1) The initial setting of VSub shall be 8.0V and shall be adjusted to the minimum voltage at which no blooming is caused at a
light input of 100 times the standard value. The standard light input is the one when the exposure is done at an aperture of
F/8 using a light source of 2856K and 1050nt, and placing a color temperature conversion filter LB-40 (Hoya) and an IR
cutting filter CAW-500 (t=2.5mm) in the light path. (F/1.4 20.5nt)
If any FPN picture is present at the minimum operating condition of VSub, it should be adjusted to the minimum voltage at
which there is no FPN picture.
When any overflow charge is present, it should be adjusted to the minimum voltage at which the overflow charge is
eliminated in the range under 13.5V.
Note 2) Absolute maximum ratings: – 0.2 <VSub–VPT < + 55 (V)
– 0.2 <VøV–VPT < + 24.5 (V)
Note 3) The LG pins should each be grounded via a capacitor of 0.047µF or more.
14.5
14.5
ø
–1.2
4.7
0
4.7
0
4.7
0
14.5
– 0.2
–7.3
0.8
–7.3
14.5
– 0.2
–7.3
0.8
–7.3
3.0
24.5
Parameter Symbol Unit
Rating
min max
Operating condition
min typ max
Reset drain voltage
Output drain voltage
Output load transistor gate voltage
Protection P well voltage
P well voltage
Reset pulse voltage
Horizontal register clock pulse voltage 1
Horizontal register clock pulse voltage 2
Vertical shift register
clock pulse voltage 1
Vertical shift register
clock pulse voltage 2
Vertical shift register
clock pulse voltage 3
Vertical shift register
clock pulse voltage 4
Substrate voltage
Operating temperature
Storage temperature
VV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
˚C
˚C
– 0.2
– 0.2
–10.0
– 0.2
– 0.2
– 0.2
–9
–9
–9
–9
– 0.2
–10
–30
18
18
0.2
18
18
18
18
15
18
15
45
70
80
RD
OD
LG
PT
PW
ø R (H-L)
ø R (Bias)
ø H1 (H)
ø H1 (L)
ø H2 (H)
ø H2 (L)
ø V1 (H)
ø V1 (M)
ø V1 (L)
ø V2 (M)
ø V2 (L)
ø V3 (H)
ø V3 (M)
ø V3 (L)
ø V4 (M)
ø V4 (L)
Sub
opr
stg
V (L)
15.0
15.0
ø
–1.0
0
5.0
Adjust
5.0
0
5.0
0
15.0
0
–7.0
1.0
–7.0
15.0
0
–7.0
1.0
–7.0
Adjust
25.0
25.0
V (L)
15.5
15.5
ø
– 0.7
5.3
5.0
5.3
0
5.3
0
15.5
0.2
–6.7
1.2
–6.7
15.5
0.2
–6.7
1.2
–6.7
14.5
25.5
V (L)
(Supplied internally)
Reference voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T
T
V
H-L
Bias
Sub
ø V *2
Note 3)
*1
*1
*2
Note 2) Note 1)
Optical Characteristics
Color
or
B/W
MN3711CFP Color 512 492 58 650 200 0.01 0 330 350
Type No. Valid pixels
H V
S/N
typ.
(dB)
Saturation
output
typ.
(mV)
Sensitivity
F8
typ.
(mV)
Vertical
smear
Sm
typ. (%)
Vertical
resolution
typ.
(TV-lines)
Horizontal
resolution
typ.
(TV-lines)
Image lag
typ.
(%)
*2 VSub when using electronic shutter function
E
H-L
V
ø RL
V
ø RH
Bias (0 to 5.0V DC) E
ø V (V)
ø V L
Sub
ø V H
Sub
Sub
V (V)
Sub
*1
CCD Area Image Sensor
MN3711CFP
100
80
60
40
20
0400 500 600 700
Relative responsivity (%)
Wavelength (nm)
Without color filter
100
80
60
40
20
0
Transmittance (%)
400 500 600 700
Wavelength (nm)
Mg
CYYe
Gr
Color Filter Spectral Characteristics
Graphs of Characteristics
CCD Spectral Characteristics
MN3711CFP
CCD Area Image Sensor
Example of Recommended Driving Pulses
• V Rate timing
HD
VD
CBLK
øV1
øV2
øV3
øV4
øSub
øH1
øH2
ab
< Field A >
HD
VD
CBLK
øV1
øV2
øV3
øV4
øSub
øH1
øH2
ab
< Field B >
CCD Area Image Sensor
MN3711CFP
• H Rate timing
0T
ø
HD
CBLK
H1
øH2
0T
(232.2T)
206.5T
10.83µs (12.03µs)
6.36µs (6.58µs)
OB Dummy
OB (28 bits) 512 valid bits
Margin (2 bits) Dummy (1 bit) Blank feed (4 bits)
Dummies (6 bits) OB (2 bits)
Margin (7 bits)
1.21µs
154T(178T)45T
154T(178T)45T
70T 100T
90T 120T
60T 110T
80T 130T
94T 134T
Video output
CCD output
øV1
øV2
øV3
øV4
øSub
Margin
• High speed pulse timing
D
DS
CCD output
1
DS2
øH1
øH2
øR
DDDDDOB OB 123
D : Dummy C + G
or
C + M
Y
g
Y
Y + M
or
Y + G
e
g
eC + G
or
C + M
Y
g
Y