PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 4Mb ZBT(R) SRAM MT55L256L18F1, MT55L128L32F1, MT55L128L36F1; MT55L256V18F1, MT55L128V32F1, MT55L128V36F1 3.3V VDD, 3.3V or 2.5V I/O FEATURES * * * * * * * * * * * * * * * * * * * * * 100-Pin TQFP1 High frequency and 100 percent bus utilization Fast cycle times: 10ns, 11ns, and 12ns Single +3.3V 5% power supply (VDD) Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) Advanced control logic for minimum control signal interface Individual BYTE WRITE controls may be tied LOW Single R/W# (read/write) control pin CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs to eliminate the need to control OE# SNOOZE MODE for reduced-power standby Common data inputs and data outputs Linear or interleaved burst modes Burst feature (optional) Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBT SRAM family 165-pin FBGA package 100-pin TSOP package 119-pin BGA package Automatic power-down OPTIONS 165-Pin FBGA (Preliminary Package Data) MARKING* * Timing (Access/Cycle/MHz) 7.5ns/10ns/100 MHz 8.5ns/11ns/90 MHz 9ns/12ns/83 MHz * Configurations 3.3V I/O 256K x 18 128K x 32 128K x 36 2.5V I/O 256K x 18 128K x 32 128K x 36 * Package 100-pin TQFP 165-pin FBGA 119-pin, 14mm x 22mm BGA * Operating Temperature Range Commercial (0C to +70C) Industrial (-40C to +85C)** -10 -11 -12 119-Pin BGA2 MT55L256L18F1 MT55L128L32F1 MT55L128L36F1 MT55L256V18F1 MT55L128V32F1 MT55L128V36F1 T F B NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). 2. JEDEC-standard MS-028 BHA (PBGA). None IT * A Part Marking Guide for the FBGA devices can be found on Micron's web site--http://www.micron.com/support/index.html. ** Industrial temperature range offered in specific speed grades and confgurations. Contact factory for more information. Part Number Example: MT55L256L18F1T-12 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM FUNCTIONAL BLOCK DIAGRAM 256K x 18 18 SA0, SA1, SA ADDRESS REGISTER MODE CLK CKE# K CE 16 18 SA1 D1 SA0 D0 ADV/LD# K 18 Q1 SA1' SA0' BURST Q0 LOGIC WRITE ADDRESS REGISTER 18 18 ADV/LD# 256K x 9 x 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa# 18 WRITE DRIVERS BWb# MEMORY ARRAY R/W# OE# CE# CE2 CE2# S E N S E A M P S D A T A S T E E R I N G B U F F E R S DQs 18 E 18 INPUT E REGISTER READ LOGIC O U T P U T FUNCTIONAL BLOCK DIAGRAM 128K x 32/36 17 SA0, SA1, SA MODE CLK CKE# K CE ADDRESS REGISTER 17 SA1 D1 SA0 D0 ADV/LD# K 15 BURST LOGIC 17 Q1 SA1' SA0' Q0 17 WRITE ADDRESS REGISTER 17 128K x 8 x 4 (x32) ADV/LD# BWa# BWb# BWc# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC 36 WRITE DRIVERS 128K x 9 x 4 (x36) MEMORY ARRAY BWd# S E N S E A M P S R/W# OE# CE# CE2 CE2# INPUT E REGISTER D A T A S T E E R I N G O U T P U T B U F F E R S 36 DQs E 36 READ LOGIC NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams for detailed information. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM GENERAL DESCRIPTION The Micron(R) Zero Bus TurnaroundTM (ZBT(R)) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. Micron's 4Mb ZBT SRAMs integrate a 256K x 18, 128K x 32, or 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating any turnaround cycles when transitioning from READ to WRITE, or vice versa. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, and BWd#) and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The flow-through dataout (Q) is enabled by OE#. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by the burst 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 advance pin (ADV/LD#). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the flow-through ZBT SRAM uses a LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions. Micron's 4Mb ZBT SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTLcompatible. Users can choose either a 2.5V or 3.3V I/O version. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. Please refer to Micron's Web site (www.micron.com/ products/datasheets/zbtds.html) for the latest data sheet. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC NC NC DQb DQb DQb DQb DQb DQb DQb DQb DQb NC x32 NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd x36 DQc DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32 x36 VSS VDDQ NC DQd DQd NC DQd DQd NC NC DQd MODE (LBO#) SA SA SA SA SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA SA SA PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC NC NC DQa DQa DQa DQa DQa NC x32 NC DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD VSS VSS DQb DQb VDDQ VSS DQb DQb DQb DQb x36 DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 NC NC SA NC NC x32 x36 VSS VDDQ DQb DQb DQb DQb NC DQb SA SA NF* NF* ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWc# BWd# BWd# CE2 CE# SA SA * Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS VSS VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN ASSIGNMENT (Top View) 100-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VSS VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQa* NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x32/x36 SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQd* SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. **Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM TQFP PIN DESCRIPTIONS x18 37 36 32-35, 44-50, 80-82, 99, 100 x32/x36 37 36 32-35, 44-50, 81, 82, 99, 100 SYMBOL TYPE SA0 Input SA1 SA 93 94 - - 93 94 95 96 BWa# BWb# BWc# BWd# Input 89 89 CLK Input 98 98 CE# Input 92 92 CE2# Input 97 97 CE2 Input 86 86 OE# (G#) Input 85 85 87 87 CKE# Input 64 64 ZZ Input ADV/LD# Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for the higher-density 8Mb and 16Mb ZBT SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDECstandard term for OE#. Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. (continued on next page) 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM TQFP PIN DESCRIPTIONS (continued) x18 88 x32/x36 88 (a) 58, 59, 62, 63, 68, 69, 72-74 (b) 8, 9, 12, 13, 18, 19, 22-24 (a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 SYMBOL TYPE R/W# Input DQa DQb DESCRIPTION Read/Write: This input determines the cycle type when ADV/LD# is LOW and the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Input/ SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb Output pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge CLK. DQc DQd N/A 51 80 1 30 NC/DQa NC/DQb NC/DQc NC/DQd NC/ I/O No Connect/Data Bits: On the x32 version, these pins are no connect (NC) and can be left floating or connected to GND to minimize thermal impedance. On the x36 version, these bits are DQs. 31 31 MODE (LBO#) Input Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 95, 96 N/A NC NC No Connect: These pins can be left floating or connected to GND to minimize thermal impedance. 83, 84 83, 84 NF - 38, 39, 42, 43 38, 39, 42, 43 DNU - 15, 16, 41, 65, 91 15, 16, 41, 65, 91 VDD Supply 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 VDDQ Supply VSS Supply No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. Reserved for address expansion, pin 83 becomes an SA at 8Mb density and pin 84 becomes an SA at 16Mb density. Do Not Use: These signals may either be unconnected or wired to GND to minimize thermal impedance. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM PIN LAYOUT (TOP VIEW) 165-PIN FBGA x18 x32/x36 10 11 CKE# ADV/LD# NC SA SA R/W# OE# (G#) NC SA NC VSS VDDQ NC DQPa VSS VDD VDDQ NC DQa VSS VSS VDD VDDQ NC DQa VSS VSS VSS VDD VDDQ NC DQa VDD VSS VSS VSS VDD VDDQ NC DQa NC VDD VSS VSS VSS VDD NC NC ZZ NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC NC VSS VSS VDDQ NC NC NC NC SA SA DNU SA1 DNU SA SA SA NC MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA 1 2 3 4 5 6 NC SA CE# BWb# NC CE2# NC SA CE2 NC BWa# CLK NC NC VDDQ VSS VSS VSS VSS NC DQb VDDQ VDD VSS VSS NC DQb VDDQ VDD VSS NC DQb VDDQ VDD NC DQb VDDQ VSS VDD DQb 7 8 9 A A B VSS VDD VDDQ DQb DQb VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb NC VDD VSS VSS VSS VDD NC NC ZZ DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NC/DQPd NC VDDQ VSS NC NC VSS VSS VDDQ NC NC/DQPa NC NC SA SA DNU SA1 DNU SA SA SA NC MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA NC/DQPc NC VDDQ VSS VSS VSS VSS DQc DQc VDDQ VDD VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ VSS VDD DQd B C D E F G H J K L M N P R NC/DQPb CLK M N P NC BWd# BWa# L M N VDDQ CE2 K L M VSS SA A J K L NC NC 9 H J K SA CE2# 8 G H J NC BWc# BWb# 7 F G H R/W# OE# (G#) CE# 6 E F G NC SA 5 D E F SA NC 4 C D E CKE# ADV/LD# NC 3 B C D 11 2 A B C 10 1 N P R P R R TOP VIEW TOP VIEW *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. NOTE: Pins 9A, and 9B reserved for address pin expansion; 8Mb, and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM FBGA PIN DESCRIPTIONS x18 x32/x36 6R 6R 6P 6P 2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R, 4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R, 9P, 9R, 10A, 9P, 9R, 10A, 10B, 10P, 10B, 10P, 10R, 11A, 11R 10R, 11R SYMBOL TYPE SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. DESCRIPTION 5B 4A - - 5B 5A 4A 4B BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For the x32 and x36 versions, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. Parity is only available on the x18 and x36 versions. 6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device. CE# is sampled only when a new external address is loaded. (ADV/LD# LOW) 6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 7A 7A CKE# Input 11H 11H ZZ Input Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 7B 7B R/W# Input 3B 3B CE2 Input 8B 8B OE#(G#) Input Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. (continued on next page) 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE 8A 8A ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. 1R 1R MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, 10E, 1L, 1M, 2D, 10F, 10G, 11D, 2E, 2F, 2G 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M DQa DQb Input DESCRIPTION Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQas; Output Byte "b" is associated with DQbs. For the x32 and x36 versions, Byte "a" is associated with DQas; Byte "b" is associated with DQbs; Byte "c" is associated with DQcs; Byte "d" is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd 11C 1N - - 11N 11C 1C 1N NC/DQPa NC/DQPb NC/DQPc NC/DQPd 2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M 2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M VDD 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N VDDQ NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE DESCRIPTION 1H, 4C, 4N, 5C, 1H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 7N, 8C, 8N 7M, 7N, 8C, 8N VSS 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 1A, 1B, 1C, 1A, 1B, 1P, 1D, 1E, 1F, 2C, 2N, 2P, 1G, 1P, 2C, 2R, 3H, 5N, 2J, 2K, 2L, 6N, 9A, 9B, 2M, 2N, 2P, 9H, 10C, 10H, 2R, 3H, 4B, 10N, 11A, 5A, 5N, 6N, 11B, 11P 9A, 9B, 9H, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N, 11P NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. Pins 9A, and 9B reserved for address pin expansion; 8Mb, and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 Supply Ground: GND. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM PIN LAYOUT (TOP VIEW) 119-PIN BGA x18 x32/x36 1 2 3 4 5 6 7 VDDQ SA SA ADSP# SA SA VDDQ A 1 2 3 4 5 6 7 VDDQ SA SA ADSP# SA SA VDDQ NC CE2** SA ADSC# SA SA NC NC SA SA VDD SA SA NC DQc NF/DQPc* VSS NC VSS NF/DQPb* DQb A B B NC CE2** SA ADSC# SA SA NC C C NC SA SA VDD SA SA NC D D DQb NC VSS NC VSS DQPa NC E E NC DQb VSS VSS CE# NC DQa F DQc DQc VSS CE# VSS DQb DQb VDDQ DQc VSS OE# VSS DQb VDDQ DQc DQc BWc# DQb DQb DQc DQc VSS GW# VSS DQb DQb VDDQ VDD NC VDD NC VDD VDDQ DQd DQd VSS CLK VSS DQa DQa DQd DQd BWd# NC BWa# DQa DQa VDDQ DQd VSS BWE# VSS DQa VDDQ DQd DQd VSS SA1 VSS DQa DQa DQd NF/DQPd* VSS SA0 VSS NF/DQPa* DQa F VDDQ NC OE# VSS VSS DQa VDDQ G G NC DQb BWb# ADV# VSS NC DQa H DQb NC VSS GW# VSS DQa NC J J VDDQ VDD NC VDD NC VDD VDDQ K K NC DQb CLK VSS VSS NC DQa L L DQb NC NC VSS BWa# DQa NC M M VDDQ DQb BWE# VSS VSS NC VDDQ N N DQb NC VSS SA1 VSS DQa NC P P NC DQPb SA0 VSS VSS NC DQa R R NC SA MODE (LBO#) VDD VDD3 SA NC T NC SA MODE (LBO#) VDD NC NC SA VDDQ TMS TDI VDD 3 SA NC T NC SA SA NC SA SA ZZ U SA SA NC ZZ TCK TCO NC VDDQ U VDDQ TMS TDI TCK TDO NC VDDQ TOP VIEW NOTE: 1. 2. 3. 4. ADV# BWb# H TOP VIEW Pins 6B and 2B reserved for address pin expansion; 8Mb and 16Mb respectively. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. Pin 3J does not have to be connected directly to VDD if the input voltage is VIH. Pins 5J and 5R do not have to be connected directly to VSS if the input voltage is VIH. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM BGA PIN DESCRIPTIONS x18 x32/x36 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4P 4N 2A, 2C, 2R, 3A, 3B, 3C, 3T, 4T, 5A, 5B, 5C, 5T, 6A, 6C, 6R SYMBOL TYPE SA0 SA1 SA DESCRIPTION 5L 3G - - 5L 5G 3G 3L BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb. For the x32 and x36 versions, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb; BWc# controls DQc's and DQPc; BWd# controls DQd's and DQPd. Parity is only available on the x18 and x36 versions. 4M 4M CKE# Input Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CK input and effectively internally extends the previous CLK cycle. This input must meet the setup and hold times around the rising edge of CLK. 4H 4H R/W# Input Read/Write: This input determines the cycle type when ADV/ LD# is lOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. 4K 4K CLK Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 4E 4E CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 6B 6B CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 7T 7T ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 2B 2B CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. (continued on next page) 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM BGA PIN DESCRIPTIONS (continued) x18 x32/x36 4F 4F 4B 4B 3R 3R 4A, 4G 4A, 4G (a) 6F, 6H, 6L, (a) 6K, 6L, 6N, 7E, 7G, 6M, 6N, 7K, 7K, 7P 7L, 7N, 7P (b) 1D, 1H, (b) 6E, 6F, 1L, 1N, 2E, 6G, 6H, 7D, 2G, 2K, 2M 7E, 7G, 7H (c) 1D, 1E, 1G, 1H, 2E, 2F, 2G, 2H (d) 1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N SYMBOL TYPE DESCRIPTION OE# Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external addressis loaded. When ADV#/LD# is HIGH, R/W# is ignored. A LOW on ADV#/LD# clocks a new address at the CLK rising edge. MODE Input Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. NF Input No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. These pins are reserved for address expansion; 4G becomes an SA at 8Mb density and 4A becomes an SA at 16Mb density. DQa Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa's; Byte "b" Output is DQb's. For the x32 and x36 versions, Byte "a" is DQa's; Byte "b" is DQb's; Byte "c" is DQc's; Byte "d" is DQd's. Input data must meet setup and hold times around the rising edge of CLK. DQb DQc DQd 6D 2P - - 6P 6D 2D 2P NC/DQPa NC/DQPb NC/DQPc NC/DQPd 2J, 4C, 4J, 4R, 5R, 6J 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U 2J, 4C, 4J, 4R, 5R, 6J 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U VDD V DD Q NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM BGA PIN DESCRIPTIONS (continued) x18 x32/x36 3D, 3E, 3F, 3H, 3K, 3L, 3M, 3N, 3P, 5D, 5E, 5F, 5G, 5H, 5K, 5M, 5N, 5P 2U, 3U, 4U, 5U 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H, 5K, 5M, 5N, 5P 2U, 3U, 4U, 5U 1B, 1C, 1E, 1G, 1K, 1P, 1R, 1T, 2D, 2F, 2H, 2L, 2N, 3J, 4D, 4L, 4T, 5J, 6E, 6G, 6K, 6M, 6P, 6U, 7B, 7C, 7D, 7H, 7L, 7N, 7R 1B, 1C, 1R, 1T, 2T, 3J, 4D, 4L, 5J, 6T, 6U, 7B, 7C, 7R 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 SYMBOL TYPE V SS DESCRIPTION Supply Ground: GND. DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18) FUNCTION R/W# BWa# BWb# READ WRITE Byte "a" H L X L X H WRITE Byte "b" WRITE All Bytes WRITE ABORT/NOP L L L H L H L L H NOTE: Using R/W# and byte write(s), any one or more bytes may be written. PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36) FUNCTION READ WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE All Bytes WRITE ABORT/NOP R/W# H L BWa# X L BWb# X H BWc# X H BWd# X H L L L L L H H H L H L H H L H H L H L H H H L L H NOTE: Using R/W# and byte write(s), any one or more bytes may be written. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM State Diagram for ZBT SRAM DS BURST DS DS DESELECT W D E T RI A RE READ S WRITE BEGIN READ READ D DS READ BURST BURST AD RE E RIT W BURST KEY: BURST READ COMMAND DS READ WRITE BURST BEGIN WRITE WRITE WRITE BURST WRITE BURST OPERATION DESELECT New READ New WRITE BURST READ, BURST WRITE or CONTINUE DESELECT NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM TRUTH TABLE (Notes 5-10) OPERATION DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE ADDRESS CE# CE2# CE2 ZZ USED None H X X L None X H X L None X X L L None X X X L External L L H L ADV/ R/W# BWx OE# CKE# CLK LD# L X X X L LAE H L X X X L LAE H L X X X L LAE H H X X X L LAE H L H X L L LAE H DQ High-Z High-Z High-Z High-Z Q NOTES 1 Next X X X L H X X L L LAE H Q 1, 11 External L L H L L H X H L LAE H High-Z 2 Next X X X L H X X H L LAE H High-Z External L L H L L L L X L LAE H D 1, 2, 11 3 Next X X X L H X L X L LAE H D None L L H L L L H X L LAE H High-Z Next X X X L H X H X L LAE H High-Z Current X X X L X X X X H LAE H - None X X X H X X X X X X High-Z 1, 3, 11 2, 3 1, 2, 3, 11 4 NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not meet their requirements. 4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#, BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BWa# enables WRITEs to Byte "a" (DQas); BWb# enables WRITEs to Byte "b" (DQbs); BWc# enables WRITEs to Byte "c" (DQcs); BWd# enables WRITEs to Byte "d" (DQds). 7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 8. Wait states are inserted by setting CKE# HIGH. 9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. Voltage on VDD Supply Relative to VSS ............................... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS .......................................... -0.5V to VDD VIN ........................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** ................................... +150C Short Circuit Output Current ........................... 100mA 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage CONDITIONS SYMBOL MIN MAX UNITS NOTES DQ pins VIH VIH 2.0 2.0 VDD + 0.3 VDD + 0.3 V V 1, 2 1, 2 VIL ILI ILO -0.3 -1.0 -1.0 0.8 1.0 1.0 V A A 1, 2 3 VOH VOL 2.4 0.4 V V 1, 4 1, 4 VDD VDDQ 3.135 3.135 3.465 VDD V V 1 1, 5 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA Supply Voltage Isolated Output Buffer Supply NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply for 3.3V I/O operation. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD = +3.3V 0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current CONDITIONS Data bus (DQx) SYMBOL VIHQ MIN 1.7 Inputs VIH 1.7 VDD + 0.3 V 1, 2 VIL ILI ILO -0.3 -1.0 -1.0 0.7 1.0 1.0 V A A 1, 2 3 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) MAX UNITS VDDQ + 0.3 V NOTES 1, 2 Output High Voltage IOH = -2.0mA VOH 1.7 - V 1 Output Low Voltage IOH = -1.0mA IOL = 2.0mA VOH VOL 2.0 - - 0.7 V V 1 1 IOL = 1.0mA VOL VDD VDDQ - 3.135 0.4 3.6 V V 1 1 2.375 2.9 V 1 CONDITIONS TA = 25C; f = 1 MHz SYMBOL CI TYP 4 MAX 7 UNITS pF NOTES 4 VDD = 3.3V CO CA CCK 4.5 4 4.5 5.5 7 5.5 pF pF pF 4 4 4 SYMBOL TYP MAX UNITS NOTES Supply Voltage Isolated Output Buffer Supply TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance BGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance CONDITIONS TA = 25C; f = 1 MHz CI 4 7 pF 4 VDD = 3.3V CO 4.5 5.5 pF 4 Address Capacitance CA 4 7 pF 4 Clock Capacitance C CK 4.5 5.5 pF 4 Input/Output Capacitance (DQ) FBGA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES CI 2.5 3.5 pF 4, 5 TA = 25C; f = 1 MHz CO 4 5 pF 4, 5 CCK 2.5 3.5 pF 4, 5 Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. This parameter is sampled. 5. Preliminary package data. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Note 1) (0C TA +70C; VDD = +3.3V 0.165V unless otherwise noted) MAX DESCRIPTION CONDITIONS SYMBOL TYP -10 -11 -12 Power Supply Current: Operating Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open IDD 165 300 275 250 mA 2, 3, 4 Power Supply Current: Idle Device selected; VDD = MAX; CKE# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) IDD1 10 28 22 20 mA 2, 3, 4 CMOS Standby Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 ISB2 0.5 10 10 10 mA 3, 4 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 ISB3 6 25 25 25 mA 3, 4 Device deselected; VDD = MAX; ADV/LD# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) ISB4 37 65 65 60 mA 3, 4 ZZ VIH ISB2Z 0.5 10 10 10 mA 3, 4 TTL Standby Clock Running SNOOZE MODE UNITS NOTES NOTE: 1. VDDQ = +3.3V 0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device is active (not in deselected mode). 4. Typical values are measured at 3.3V, 25C and 12ns cycle time. 5. This parameter is sampled. 6. Preliminary package data. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYMBOL TYP UNITS NOTES Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 46 C/W 1 JC 2.8 C/W 1 CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 40 C/W 1 JC 9 C/W 1 JB 17 C/W 1 CONDITIONS SYMBOL TYP UNITS NOTES Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 40 C/W 1, 2 JC 9 C/W 1, 2 JB 17 C/W 1, 2 BGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Bumps (Bottom) UNITS NOTES FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) NOTE: 1. This parameter is sampled. 2. Preliminary package data. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM AC ELECTRICAL CHARACTERISTICS (Notes 6, 8, 9) (0C TA +70C; VDD = +3.3V 0.165V) -10 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in SYMBOL MIN tKHKH 10 fKF tKHKL tKLKH tKHQX1 7.5 0 tAVKH tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX 83 3.0 3.0 8.5 9.0 3.0 3.0 5.0 5.0 0 5.0 MAX 12 3.0 3.0 5.0 5.0 tGHQZ MIN 90 3.0 3.0 3.0 3.0 tGLQV -12 MAX 11 2.5 2.5 tKHQZ tGLQX MIN 100 tKHQV tKHQX -11 MAX 5.0 5.0 0 5.0 5.0 UNITS NOTES ns MHz ns ns 1 1 ns ns ns ns ns ns ns 2 2, 3, 4, 5 2, 3, 4, 5 6 2, 3, 4, 5 2, 3, 4, 5 2.0 2.0 2.0 2.0 2.2 2.2 2.2 2.2 2.5 2.5 2.5 2.5 ns ns ns ns 7 7 7 7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 7 7 7 7 NOTE: 1. 2. 3. 4. 5. 6. Measured as HIGH above VIH and LOW below VIL. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters. This parameter is sampled. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. Transition is measured 200mV from steady state voltage. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled. 8. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V 0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted. 9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 3.3V I/O AC TEST CONDITIONS 2.5V I/O AC TEST CONDITIONS Input pulse levels ................................... VSS to 3.3V Input pulse levels ................................... VSS to 2.5V Input rise and fall times ..................................... 1ns Input rise and fall times ..................................... 1ns Input timing reference levels .......................... 1.5V Input timing reference levels ........................ 1.25V Output reference levels ................................... 1.5V Output reference levels ................................. 1.25V Output load ............................. See Figures 1 and 2 Output load ............................. See Figures 3 and 4 3.3V I/O Output Load Equivalents 2.5V I/O Output Load Equivalents Q Q Z O= 50 Z O= 50 50 50 VT = 1.25V VT = 1.5V Figure 1 Figure 3 +3.3V +2.5V 225 317 Q Q 5pF 351 5pF 225 Figure 2 Figure 4 LOAD DERATING CURVES The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2z is guaranteed after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL Current during SNOOZE MODE ZZ VIH Current during SNOOZE MODE (P Version) ZZ VIH MIN MAX UNITS ISB2Z 10 mA ISB2ZP 1 mA NOTES tZZ 0 tKHKH ns 1 ZZ inactive to input sampled tRZZ 0 tKHKH ns 1 ZZ active to snooze current tZZI tKHKH ns 1 ns 1 ZZ active to input ignored tRZZI ZZ inactive to exit snooze current 0 NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM READ/WRITE TIMING 1 2 tKHKH 3 4 5 6 7 8 9 A5 A6 A7 10 CLK tEVKH tKHEX tCVKH tKHCX tKHKL tKLKH CKE# CE# ADV/LD# R/W# BWx# A1 ADDRESS A2 A3 A4 tKHQV tAVKH tKHAX tKHQX tKHQX1 DQ D(A1) D(A2) D(A2+1) tGLQV Q(A3) Q(A4+1) Q(A4) tGLQX OE# WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tGHQZ tDVKH tKHDX COMMAND tKHQZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) tKHQX WRITE D(A5) READ Q(A6) DON'T CARE UNDEFINED READ/WRITE TIMING PARAMETERS -10 SYM tKHKH fKF tKHKL MIN 10 tKLKH 2.5 tKHQX1 MIN 11 100 2.5 tKHQV tKHQX -11 MAX -12 MAX 90 3.0 -10 MAX MIN 2.0 2.0 2.2 2.2 2.5 2.5 UNITS ns ns ns ns ns tCVKH 9.0 2.0 2.0 2.2 2.2 2.5 2.5 ns ns ns ns ns tKHAX tKHCX 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns tKHDX 0.5 0.5 0.5 ns 3.0 3.0 3.0 3.0 3.0 tKHQZ 5.0 5.0 5.0 tGLQV 5.0 5.0 5.0 tGLQX NOTE: 1. 2. 3. 4. 0 0 0 -12 SYM tGHQZ tAVKH tEVKH 83 8.5 -11 UNITS ns MHz ns 3.0 3.0 7.5 3.0 3.0 MIN 12 tDVKH tKHEX MAX 5.0 MIN MAX 5.0 MIN MAX 5.0 For this waveform, ZZ is tied LOW. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM NOP, STALL, AND DESELECT CYCLES 1 2 3 A1 A2 4 5 A3 A4 6 7 8 9 10 CLK CKE# CE# ADV/LD# R/W# BWx# ADDRESS A5 tKHQZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) tKHQX COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DON'T CARE DESELECT CONTINUE DESELECT UNDEFINED NOP, STALL, AND DESELECT TIMING PARAMETERS -10 SYM tKHQX tKHQZ MIN 3.0 -11 MAX MIN 3.0 5.0 -12 MAX 5.0 MIN 3.0 MAX 5.0 UNITS ns ns NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE# are tied LOW. 3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 ID 22.10 +0.10 -0.15 0.15 +0.03 -0.02 0.32 +0.06 -0.10 0.65 20.10 0.10 DETAIL A 0.62 1.50 0.10 0.10 14.00 0.10 16.00 +0.20 -0.05 0.25 0.10 +0.10 -0.05 GAGE PLANE 1.00 (TYP) 0.60 0.15 1.40 0.05 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 165-PIN FBGA 0.85 0.075 0.12 C SEATING PLANE C BALL A11 165X O 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.40 10.00 BALL A1 PIN A1 ID 1.00 TYP 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 TYP MOLD COMPOUND: EPOXY NOVOLAC 6.50 0.05 SUBSTRATE: PLASTIC LAMINATE 5.00 0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .33mm 13.00 0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM 119-PIN BGA 22.00 0.20 19.94 0.10 Substrate material: BT resin laminate 0.60 0.10 14.00 0.10 0.90 0.10 0.15 11.94 0.10 SEATING PLANE 2.40 MAX A1 CORNER O 0.75 0.15 (dimension applies to a noncollapsed solder ball) A1 CORNER 1.27 (TYP) 7.62 1.27 (TYP) 20.32 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Solder ball land pad is 0.6mm. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark adn the Micron logo and M logo are trademarks of Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola, Inc. 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH ZBT SRAM REVISION HISTORY Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................ June 7/01 Added Industrial Temperature note and references, Rev. 3/01, FINAL ..................................................... March 6/01 Added 119-pin PBGA package, Rev. 1/01, FINAL ................................................................................. January 10/01 Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .................................................................... August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/00 CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF CO; TYP 4pF from 6pF; MAX. 5pF from 7pF CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF Added FBGA Part Marking Guide, Rev. 7/00, Preliminary .......................................................................... July 12/00 Added revision history Added 165-pin FBGA package, Rev. 6/00, Preliminary ............................................................................... May 23/00 Removed all "Smart ZBT" references 4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM MT55L256L18F1_C.p65 - Rev. 6/01 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.