NMC27C010 National Semiconductor PRELIMINARY NMC27C010 (Former NMC27C1023)* 1,048,576-Bit (128k x 8) UV Erasable CMOS PROM General Description The NMC27C010 is a high-speed 1024k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimenta- tion and low power consumption are important require- ments. The NMC27C010 is designed to operate with a single + 5V power supply with +5% or +10% tolerance. The CMOS design allows the part to operate over extended and military temperature ranges. The NMC27C010 is packaged in a 32-pin dual-in-line pack- age with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written electrically into the device by following the programming procedure. This EPROM is fabricated with Nationals proprietary, time proven CMOS double-poly silicon gate technology which combines high performance and high density with low pow- er consumption and excellent reliability. Features @ Clocked sense amps for fast access time down to 160 ns @ Low CMOS power consumption Active power: 110 mW max Standby power: 0.55 mW max m Extended temperature range (NMC27C0O10QE), 40C to +85C and military temperature range (NMC27C010QM), 55C to + 125C, available Pin compatible with NMOS bytewide 1024k EPROMs Fast and reliable programming100 us typical/byte Static operationno clocks required TTL, CMOS compatible inputs/outputs TRI-STATE output Optimum EPROM for total CMOS systems Manufacturer's identification code for automatic pro- gramming control High current CMOS level output drivers Block Diagram DATA OUTPUTS 09-0) Voc Omen GND O> mom Litttt tt GE ame] DUTPUT ENABLE, FGM p] CHIP ENABLE, AND iM OUTPUT Pin Names = >] PROGRAM LOGIC al BUFFERS - AO-A16 Addresses CE Chip Enable = DECODER . v GATING OE Output Enable - > Og-07 Outputs aoare | PGM Program ADDRESS 4 >) > NC No Connect INPUTS | p 1,048,576-B1T > x , CELL MATRIX >] DECODER > . > | *Some programmer manufacturers will call this device NMC27C1023. TL/D/91824 1-116Connection Diagram NMG27C010Q Dual-In-Line Package 4Mbit | 2Mbit 2Mbit | 4 Mbit Vpp Vpp Vep 1 32 Voce Voc Voc A16 A16 A162 31} PGM PGM A18 A15 A15 AIS43 30 Nc A17 A17 A12 A12 AlL24 29 fala Al4 Al4 A7 A7 AT15 28 RaAl3 A13 A13 AG AG AB16 27 as AB A8 AS AS AS-7 26 Ag Ag AQ Ad A4 Ada8 25 All Alt Alt A3 A3 As19 24; OE OE OE A2 A2 A2A10 23 ato A10 A10 Al Al Aymatt 22 fCE CE CE AO AD Ag=412 2107 O7 O7 Oo Oo Ogq13 20 f= 0 Os Os O71 01 0,414 18 0s Os Os Oo Os Oo 715 18-0, O4 O4 GND GND GND 116 170; Og Og TL/D/$162-2 Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMG27C010 pins. Order Number NMCG27C010Q See NS Package Number J32AQ OLODZZDAN Commercial Temperature Range (0C to + 70C) Commercial Temperature Range (0C to + 70C) Veco = 5V +5% Veco = 5V +10% Parameter/Order Number Access Time (ns) Parameter/Order Number Access Time (ns) NMG27C010015 150 NMC27C010Q150 150 NMC27C0010017 170 NMC27C0100170 170 NMC27C010Q20 200 NMG276010Q200 200 NMC27C010Q25 250 NMG27C010Q250 250 Extended Temperature Range ( 40C to + 85C) Military Temperature Range (55C to + 125C) Voc = 5V + 10% Veco = 5V + 10% Parameter/Order Number Access Time {ns) Parameter/Order Number Access Time (ns) NMC27C010QE170 170 NMG27C010QM170 170 NMC27C010QE200 200 NMC27C010QM200 200 NMC27C010QE250 250 NMC27C010QM250 250 NOTE: Surface mount PLCC package available for commercial and extended temperature ranges only. 1-117NMC27C010 COMMERCIAL TEMPERATURE RANGE Absolute Maximum Ratings (note 1) Temperature Under Bias Storage Temperature All Input Voltages except AQ with Respect to Ground (Note 10) All Output Voltages with Respect to Ground (Note 10} Vpp Supply Voltage and AQ with Respect to Ground Voc + 1.0V to GND-0.6V 10C to + 80C Power Dissipation 1.0W 65C to + 150C Lead Temperature (Soldering, 10 sec.) 300C ESD Rating +6,5V to -0.6V (Mil Spec 883C, Method 3015.2) 2000V Temperature Range Vcc Power Supply Operating Conditions (note 7) 0 to + 70C During Programming + 14,0V to 0.6V NMC27C010015, 17, 20, 25 +5V +5% Voc Supply Voltage with NMG27C0100150, 170, 200, 250 +5V 410% Respect to Ground +7.0V to 0.6V READ OPERATION DC Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units lu Input Load Current Vin = Voc or GND 1 pA Lo Output Leakage Current Vout = Vcc or GND, CE = Vin 1 pA loci Voc Current (Active) CE = Vi_,f = 5 MHz 15 30 mA (Note 9) TTL Inputs Inputs = Vjy or Vi_, 1/0 = OmA loce Voc Current (Active) CE = GND, f = 5 MHz 40 20 mA (Note 9) CMOS Inputs Inputs = Voc or GND, 1/0 = OmA locsB1 Voc Current (Standby) CE = Vin 04 { mA TTL Inputs locsp2 CoS Input (Standby) CE = Vcc 0.5 100 pA Ipp Vpp Load Current Vpp = Veco 10 BA VIL Input Low Voltage -0.2 0.8 Vv Vin Input High Voltage 2.0 Veco +1 Vv Vou Output Low Voltage lo = 2.1 mA 0.40 v Vor Output High Voltage lon = 2.5mA 3.5 V Voie Output Low Voltage lo. = 10 pA 0.1 Vv Voue Output High Voltage lon = ~10 A Vec 0.1 V AC Electrical Characteristics NMC27C010 Symbol Parameter Conditions Q15,Q150 | Q17,Q170 | Q20,Q200 | Q@25,Q250 | Units Min | Max | Min | Max | Min | Max | Min | Max tacc Address to Output Delay CE = OE = VIL 150 170 200 250 ns PGM = Vin tce CE to Output Delay OE = Vi, PGM = Vin 150 170 200 250 | ns toe OE to Output Delay CE = Vi_, PGM = Vin 60 75 75 100 | ns tor OE High to Cutput Float CE = Vi_, PGM = Vi, 50 0 55 55 60 ns tor CE High to Output Float OE = Vit, PGM = Vin 50 0 55 0 55 0 60 ns tou Output Hold from Addresses, | CE = OE = Vit CE or OE, Whichever PGM = Vin 0 0 0 0 ns Occurred First 4-118MILITARY AND EXTENDED TEMPERATURE RANGE Absolute Maximum Ratings (note 1) If Milltary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Under Bias Operating Temp. Range Storage Temperature 68C to + 150C All Input Voltages except AQ with Respect to Ground (Note 10) All Output Voltages with Respect to Ground (Note 10) Vep Supply Voltage and Ao with Respect to Ground During Programming Voc Supply Voltage with Respect to Ground Power Dissipation Lead Temperature (Soldering, 10 sec.) ESD Rating +6.5V to 0.6V (Mi! Spec 883C, Method 3015.2) Voct+ 1.0V to GND0.6V Temperature Range NMC27C010QE150, 170, 200, 250 +14,0V to 0.6V NMC27C010QM170, 200, 250 +7.0 to 0.6V Operating Conditions (Note 7) 1.0W 300C 2000V 40C to + 85C 55C to + 126C Voc Power Supply +5V 10% READ OPERATION DC Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units lot Input Load Current Vin = Voc or GND 10 pA lLo Output Leakage Current Vout = Voc or GND, CE = Vin 10 pA lec: Voc Current (Active) CE = Vi, f = 5 MHz 46 30 mA (Note 9) TTL Inputs Inputs = Viyor Vi, 1/0 = OMA loce Voc Current (Active) CE = GND, f = 5 MHz 10 20 mA (Note 9) CMOS Inputs Inputs = Voc or GND, I/O = OmA locsp1 voc pute. (Standby) CE = Vin 0.4 1 mA Iscsp2 Coe Inout (Standby) E = Voc 05 100 pA Ipp Vpp Load Current Vpp = Voc 10 pA Vit Input Low Voltage 0.2 0.8 Vv Vin Input High Voltage 2.0 Voc +1 Vv Vout Output Low Voltage lo. = 2.1mA 0.40 V Voui Output High Voltage lon = 1.6mA 3.5 V VoL2 Output Low Voltage fo. = 10 pA 0.1 Vv Vou2 Output High Voltage lon = 10 pA Voc 0.1 Vv AC Electrical Characteristics NMC27C010Q Symbol Parameter Conditions E150 E170,M170 | E200,M200 | E250,M250 | Units Min | Max| Min | Max | Min | Max | Min | Max tacc Address to Output Delay CE = OE = Vit 450 170 200 260 | ns PGM = Vin tce CE to Output Delay OE = Vi_, PGM = Vin 150 170 200 250 | ns toe OE to Output Delay CE = Vi, PGM = Vin 60 75 75 100 | ns tor GE High to Cutput Float CE = Vi, PGM = Vin} 0 | 50 0 55 55 0 60 ns tor CE High to Output Float OE = Vi, PGM = Vin| 0 | 50 55 55 0 60 ns tou Output Hold from Addresses, CE = OE = Vit CE or OE, Whichever PGM = Vin 0 0 0 0 ns Occurred First 4-119 OLOOZZDINNNMC27C010 Capacitance 1, = +25c, t = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units Cin Input Capacitance Vin = OV 9 15 pF Cout Output Capacitance | Vout = OV 12 15 pF AC Test Conditions Output Load 1 TTL Gate and Timing Measurement Reference Level CL = 100 pF (Note 8) Inputs 0.8V and 2V Input Rise and Fall Times <5ns Outputs 0.8V and 2V Input Pulse Levels 0.45V to 2.4V AC Waveforms (notes 6, 7, & 9) | 55 anoresses 2V ADDRESSES VALIO x as <= OV \ CE ov es / aJ tog ter ~ (NOTES 4, 5) 20V OE ogy cc / 3J toe a ae (NOTE 3) i (NOTES 4,5) H=Z 17 HieZ OUTPUT ay VALID OUTPUT Sy 5 at ra tacc o ton be (NOTE 3) TL/D/9182-3 Note 1: Strasses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at thease or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OF may be delayed up to tacc toe after the falling edge of CE without impacting tacc. Note 4: The tpr and tcf compare leval is determined as follows: High to TRI-STATE, the measured Voy, (DC) 0.10V; Low to TRI-STATE, the measured Vo.; (DC) + 0.10V. Note 5: TRLSTATE may be attained using OF or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at jeast a 0.1 4F ceramic capacitor be used on every device between Vcc and GND. Note 7: The outputs must be restricted to Voc + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: Io, = 1.6 mA, lon = 400 vA. C_: 100 pF includes fixture capacitance. Note 9: Vpp may be connected to Voc except during programming. Note 10: inputs and outputs can undershoot to 2.0V for 20 ns Max. 1-120Programming Characteristics (notes 1, 2,3 8 4) Symbol Parameter Conditions Min Typ Max Units tas Address Setup Time 1 pS toes OE Setup Time 1 ys tces CE Setup Time OE = Vin 1 ps tos Data Setup Time 1 ps tyes Vpp Setup Time 1 ps tvcs Voc Setup Time 1 ps taH Address Hold Time 0 ps toH Data Hold Time 1 pS tor Output Enable to Output Float Delay CE = Vit 0 60 ns tpw Program Pulse Width 95 100 405 ps toe Data Valid from OE CE = Vit 100 ns Ipp Vpp Supply Current During CE = Vit 30 mA Programming Pulse PGM = Vit lec Voc Supply Current 10 mA Ta Temperature Ambient 20 25 30 C Voc Power Supply Voltage 6.0 6.25 6.5 Vpp Programming Supply Voltage 12.5 12.75 13.0 ter Input Rise, Fail Time 5 ns Vit input Low Voltage 0.0 0.45 Vv Vin Input High Voltage 2.4 4.0 WV tin Input Timing Reference Voltage 0.8 1.5 2.0 Vv tout Output Timing Reference Voltage 0.8 15 2.0 v 4-121 OL0DZZ0INNNMC27C010 Programming Waveforms (note 3) PROGRAM PROGRAM ADDRESSES ADDRESS N DATA DATA IN STABLE PCM OE TL/D/9182-5 Note 1: National's standard product warranty applies only to devices programmed to specifications described herein. .* Note 2: Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a board with valtage applied to Vpp or Vcc. Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14. Care must be taken when switching the Vpp supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across Vpp, Vcc to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings. 1-122Fast Programming Algorithm Flow Chart START ADDR = FIRST LOCATION PROGRAM ONE 100 us PULSE INCREMENT X DEVICE FAILED INCREMENT ADDR LAST ADDR? Voc= Vpp=5.0V 5% DEVICE FAILED DEVICE PASSED TL/D/9182-6 FIGURE 1 OL0DZZ0IWN 1-123NMC27C010 Functional Description DEVICE OPERATION The six modes of operation of the NMC27C010 are listed in Table |. It shouid be noted that all inputs for the six modes are at TTL levels. The power supplies required are Vcc and Vpp. The Vpp power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The Vcc power supply must be at 6.25V dur- ing the three programming modes, and at 5V in the other three modes. Read Mode The NMC27C010 has two control functions, both of which must be logically active in order to obtain data at the out- puts. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the outputs toe after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacctoe. The sense amps are clocked for fast access time. Voc should therefore be maintained at operating voltage during read and verify. If Voc temporarily drops below the specified voltage (but not to ground) an address transition must be performed aftar the drop to insure proper output data. Standby Mode The NMC27C010 has a standby mode which reduces the active power dissipation by over 99%, from 110 mW to 0.55 mW. The NMC27C010 is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs ara in a high impedance state, independent of the OE input. Output OR-Tying Because the NMC27C010 is usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE be decoded and used as the primary de- vice selecting function, while OE be made a common con- nection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on the Vpp or AQ pin will damage the NMC27C010. Initially, and after each erasure, all bits of the NMC27C010 are in the 1 state, Data is introduced by selectively pro- gramming 0s into the desired bit locations. Although only O's will be programmed, both '1s and 0's can be pre- sented in the data word. The only way to change a 0 toa 1 is by ultraviolet light erasure. The NMC27C010 is in the programming mode when the Vpp power supply is at 12.75V and OE is at Vjy. It is required that at least a 0.1 uF capacitor be placed across Vpp, Voc to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active jow, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be pro- grammed. The NMC27C010 is programmed with the Fast Programming Algorithm shown in Figure 7. Each Address is programmed with a series of 100 us pulses until it verifies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 us pulse. The NMC27C010 must not be programmed with a DC signal applied to the PGM input. Programming multiple NC27C010 in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel NMC27C010 may be connected together when they are programmed with the same data. A low level TTL pulse ap- plied to the PGM input programs the paralleled NMC27C010. Program inhibit Programming multiple NMC27C010s in parallel with differ- ent data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel NUC27C010 may be common. A TTL low level program pulse applied to an NMC27C010s PGM input with CE at V\. and Vpp at 12.75V will program that NMC27C010. A TTL high level CE input inhibits the other NMC27C010s from being pro- grammed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with Vpp at 12.75V. Vpp must be at Voc, except during programming and program verify. Manufacturers Identification Code The NMC27C010 has a manufacturer's identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific program- ming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer's Identification code, shown in Table il, specifically identifies the manufacturer and the device type. The code for the NMC27C010 is 8F86, where "8F desig- nates that it is made by National Semiconductor, and 86 designates a 1Megabit byte-wide part. 1-124Functional Description (continues) TABLE I. Mode Selection Pins CE OE PGM Vpp Vec Outputs Mode (22) (24) (31) (1) (32) (13-15, 17-21) Read Vit Vit VIH Voc 5V Dout Standby VI Dont Care Dont Care Voc 5V Hi-Z Output Disable Dont Care Vin Vin Voc 5V Hi-Z Program VIL Vin ViL 12.75V 6.25V Din Program Verify Vit VIL Vie 12.75V 6.25V Dout Program Inhibit ViH Dont Care Don't Care 12.75V 6.25V Hi-Z TABLE II. Manufacturer's Identificatiion Code Pins Ap | O7 | Og | Os | Og | 03 | Op O, | Oo | Hex (12) | (21) | (20) | (19) | (18) | (17) | (15) | (14) | (13) | Data Manufacturer Code | Vi. 1 0 0 0 1 1 1 1 8F Device Code Vin 1 0 0 0 0 1 1 0 86 The code is accessed by applying 12V +0.5V to address Pin AQ. Addresses A1A8, A10-A16, and ail control pins are held at V),. Address pin AQ is held at Vj for the manu- facturers code, and held at Vix for the device code. The code is read on the eight data pins, OgO7. Proper code access is only guaranteed at 25C +5C. ERASURE CHARACTERISTICS The erasure characteristics of the NMC27C010 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range. AFTER PROGRAMMING Opaque jabels should be placed over the NUC27C010 win- dow to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the gen- eration of photo currents. The recommended erasure procedure for the NMG27C010 is exposure to short wave ultraviolet light which has a wave- length of 2537 Angstroms (A). The integrated dose (i.., UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The NMC27C010 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table III shows the minimum NMC27C010 erasure time for various light intensities. changed, the distance has changed, or the lamp has aged, the system should be chacked to make certain full erasure is occurring. incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when in- complete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Ice. has three segments that are of interest to the system de- sign)the standby current level, the active current level, and the transient current peaks that are produced by voit- age transitions on input pins. The magnitude of these tran- sient current peaks is dependent on the output capacitance loading the device. The associated Vcc transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 pF ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 .F bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. TABLE III. NMC27C010 Minimum Erasure Time An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (lf distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is Light intensity Erasure Time (uWatts/em?2) (Minutes) 15,000 20 10,000 25 5,000 50 1-125 OLODZZOWNNMC27C010 Package Information 6 SPACES AT 0.050 (1.270) 4 tH 0.551 +0.002 8 SPACES AT (14.00 0.051) 11270) 25 0.490 -0.530 0.590 + 0.005 (12.45 13.46) (14.99 0.127) (CONTACT DIMENSION) 0.390 0.430 {9.906 10.92) (CONTACT DIMENSION) 0.015 0.013 0.021 (0.3300.533) _0.100--0.140 0.0320.040 (0.381) 0,100--0.140 P (2.540 3.556) Tom 005 0.015 4 | (0.127 0.381) PIN NO. 1 0.026 0.032 4 0.060 - 0.095 ; . . IDENT (0.660 0.813) (1.524 2.413) 0.450 we (11.43) 0.485 0.495 (12.3212.57) 32-Lead PLCC Package Order Number NMC27C010V VIEW A-A 0.045 (1.143) 45 TL/D/9182-10 1-126