SY75572L 267MHz 1:2 3.3V HCSL/LVDS Fanout Buffer PrecisionEdgeTM General Description Features The SY75572L is a high-speed, fully differential 1:2 clock fanout buffer with a 2:1 input MUX optimized to provide two identical output copies with 137fs phase jitter and a maximum of 50ps output-to-output skew. Designed to be used with PCI Express applications, the SY75572L accepts and outputs HCSL or LVDS logic levels. * Two differential pairs of LVDS or HCSL outputs * Two pairs of differential inputs accept LVDS or HCSL logic levels * 267MHz maximum frequency * Ultra-low phase jitter: - 137fsRMS, 200MHz (12kHz-20MHz) - 153fsRMS, 156.25MHz (12kHz-20MHz) - 212fsRMS, 100MHz (12kHz-20MHz) * <2ps total jitter (peak-to-peak), 200MHz (BER = 10-12) * 50ps output-to-output skew * 3.3V 5% power supply operation * -40C to +85C operating temperature * Available in 16-pin (3mm x 3mm) QFN lead-free package The SY75572L operates from a 3.3V 5% power supply and is guaranteed over the full industrial temperature range (-40C to +85C). It is available in a 16-pin QFN lead-free package. The SY75572L is part of Micrel's high-speed, ultra-low jitter, PrecisionEdgeTM product line. The SY75572L supports PCIe Gen1-Gen3 requirements with sufficient performance margin for pending PCIe Gen4 applications. Datasheets and support documentation are available on Micrel's website at: www.micrel.com. Functional Block Diagram Applications * * * * * * * Blade servers Desktop servers Workstations Storage area networks IP routers and switches Telecom and datacom High performance computing PrecisionEdgeTM is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com December 5, 2014 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY75572LMG QFN-16 Industrial 572L with Pb-Free bar-line indicator NiPdAu QFN-16 Industrial 572L with Pb-Free bar-line indicator NiPdAu (2) SY75572LMG TR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and reel. Pin Configuration 16-Pin QFN December 5, 2014 2 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Pin Description Pin Number Pin Name 1 /IN1 HCSL/LVDS inverted input 1. 2 PDB PDB = 0 powers down the chip and tri-states outputs. The pin is attached to an internal pull-up resistor. 3 IN2 HCSL/LVDS input 2. 4 /IN2 HCSL/LVDS inverted input 2. 5 OE Tri-state outputs. High = enable outputs. Low = disable outputs. Internal pull-up resistor, outputs are enabled by default. 6 GND Ground. 7 IREF External resistor RREF between pin IREF and GND controls reference current. 8 /Q1 Inverted Output 1. 9 Q1 Non-inverted Output 1. 10 VDD 3.3V power supply. 11 GND Ground. 12 /Q0 Inverted Output 0. 13 Q0 Non-inverted Output 0. 14 SEL SEL = 0 propagates IN2, /IN2 to outputs. SEL = 1 propagates IN1, /IN1 to outputs. Internal pullup resistors, IN1, /IN1 is selected by default. 15 VDDIN 16 IN1 December 5, 2014 Pin Function 3.3V power supply. HCSL/LVDS input 1. 3 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Absolute Maximum Ratings(3) Operating Ratings(4) Supply Voltage (VDD, VDDIN) ........................................... 5.5V Input Voltage (VIN) .............................. -0.5V to VDDIN + 0.5V Lead Temperature (soldering, 20s) ............................ 260C Maximum Junction Temperature................................ 125C Storage Temperature (Ts) ......................... -65C to +150C ESD Protection (input) ....................................... 2000V min. Supply Voltage (VDD, VDDIN) ...................... 3.135V to 3.465V Ambient Op Temperature (TA) .................... -40C to +85C (5) Package Thermal Resistance QFN-16 Still-air (JA) ................................................. 59C/W Junction-to-board (JB) ............................... 38C/W DC Electrical Characteristics(6) VDD = VDDIN = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise stated. RREF = 475 Symbol Parameter Condition Min. Typ. Max. Units VDD, VDDIN Power Supply Voltage Range 3.135 3.3 3.465 V CIN Input Capacitance 6 pF COUT Output Capacitance 5 pF LPIN Pin Inductance 4 nH ROUT Output Resistance RPULL-UP Pull up Resistance SEL, PDB, OE VIH Input High Voltage SEL, PDB, OE 2 VDDIN + 0.3 V VIL Input Low Voltage SEL, PDB, OE -0.3 0.8 V VIH Input High Voltage HCSL, IN, /IN 660 750 850 V VIL Input Low Voltage HCSL, IN, /IN -150 0 VIN Differential Input Voltage Range LVDS, IN, /IN 250 350 550 VINPUT OFFSET Input Common Mode Voltage LVDS, IN, /IN, 1.125 1.25 1.375 V VOH Output High Voltage HSCL 660 750 850 mV VOL Output Low Voltage HSCL -150 0 27 mV (7, 8) VCROSS Crossing Point Voltage Absolute 250 350 550 mV (7, 8, 9) VCROSS_VARIATION Variation of Crossing Point Voltage 140 mV 60 mA No load, PDB = Low 0.4 mA OE = Logic Low 20 mA 5 A IDD IIL (10) Input Leakage Current k 110 Variation over all edges 50, 2pF Power Supply Current For VDD + VDDIN k 3 0 < VIN < VDDIN 42 -5 V mV Notes: 3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings. 5. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air unless otherwise stated. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 7. Test setup is RL = 50 with 2pF, RREF = 475 1%. 8. Measurement taken from Q and /Q. 9. Measured at the crossing point where instantaneous voltages of Q and /Q are equal. 10. Inputs with pull-up/pull-down resistances are not included. December 5, 2014 4 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L AC Electrical Characteristics(6) VDD = VDDIN = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise stated. Symbol Parameter fMAX Maximum Frequency tPD Propagation Delay Note 11 tSKEW Output-to-Output skew Notes 12, 13 tr , tf Output Rise/Fall Times 0.175V to 0.525V / 0.525V to 0.175V At full output swing. 50, 2pF Tr/f_VAR Rise/Fall Time Variation At full output swing. 50, 2pF TJITTER Phase Jitter Condition Min. Typ. Max. Units HCSL 267 LVDS 100 MHz 3 ns 50 ps 700 ps 125 ps 2 150 350 At 200MHz 137 fsrms At 156.25MHz 153 fsrms At 100MHz 212 fsrms -12 TTJ_JITTER Total Jitter BER = 10 , TDJ = 0, at 200MHz 2 ps TOE_ENABLE Output Enable Time All Outputs 2 s TOE_DISABLE Output Disable Time All Outputs 10 ns TDCY Duty Cycle 45 50 55 % Notes: 11. Measured from the differential input crossing point to the differential output crossing point. 12. Output-to-output skew is the difference in time between outputs, receiving data from the same input, for the same temperature, voltage, and transition. 13. This parameter is defined in accordance with JEDEC Standard 65. Where TJ is total jitter, RJ is random jitter, and DJ is deterministic jitter. If routing clock signals, the deterministic jitter is usually negligible and the TJ is dominated by the random jitter. Calculating TJ from RJ using Equation 1 gives the values in Table 1. Jitter Analysis Jitter is defined as the deviation of a signal from its ideal position. Phase noise is the presence of signal energy at frequencies other than the carrier. Random jitter has a Gaussian distribution and is specified as an RMS unit, which is one standard deviation of the distribution. Since Gaussian distribution is unbounded in an infinite sample, no communication system can be completely error free. Instead, communication links are rated with a maximum bit -12 error rate (BER), which is typically around 10 for highspeed communication equipment. Achieving a desired BER requires accounting for a number of standard deviations of random noise by using the appropriate value for N (see Table 1) in the formula in Equation 1. T J = N x RJ + D J December 5, 2014 Table 1. Standard Deviations of Random Noise BER N Rj at 200MHz Tj at 200MHz 10 -10 12.723 137fsRMS 1.743ps 10 -11 13.412 137fsRMS 1.837ps 10 -12 14.069 137fsRMS 1.927ps 10 -13 14.698 137fsRMS 2.013ps Eq. 1 5 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Phase Noise Plots Phase jitter = 137fsRMS, 200MHz carrier frequency; integration range: 12kHz-20MHz December 5, 2014 6 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Phase Noise Plots (Continued) Phase jitter = 153fsRMS, 156.25MHz carrier frequency; integration range: 12kHz-20MHz December 5, 2014 7 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Phase Noise Plots (Continued) Phase jitter = 212fsRMS, 100MHz carrier frequency; integration range: 12kHz-20MHz December 5, 2014 8 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Functional Characteristics HCSL Waveform Diagram HCSL Interface Application PCI Express Device Routing RS = 33, RT = 50 December 5, 2014 9 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L LVDS Waveform Diagram LVDS Interface Application December 5, 2014 10 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Package Information(14) 16-Pin QFN Note: 14. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. December 5, 2014 11 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L Recommended Land Pattern(14) December 5, 2014 12 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. SY75572L MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications markets. The Company's products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide. Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2014 Micrel, Incorporated. December 5, 2014 13 Revision 1.0 tcghelp@micrel.com or (408) 955-1690