SY75572L
267MHz 1:2 3.3V HCSL/LVDS Fanout Buffer
PrecisionEdge™
PrecisionEdge
TM
is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Dec
ember 5, 2014
Revision
1.0
tcghelp@micrel.com or (408) 955-1690
General Description
The SY75572L is a high-speed, fully differential 1:2 clock
fanout buffer with a 2:1 input MUX optimized to provide
two identical output copies with 137fs phase jitter and a
maximum of 50ps output-to-output skew. Designed to be
used with PCI Express applications, the SY75572L
accepts and outputs HCSL or LVDS logic levels.
The SY75572L operates from a 3.3V ±5% power supply
and is guaranteed over the full industrial temperature
range (−40°C to +85°C). It is available in a 16-pin QFN
lead-free package.
The SY75572L is part of Micrel’s high-speed, ultra-low
jitter, PrecisionEdge™ product line. The SY75572L
supports PCIe Gen1-Gen3 requirements with sufficient
performance margin for pending PCIe Gen4 applications.
Datasheets and support documentation are available on
Micrel’s webs ite at : www.micrel.com.
Functional Block Diagram
Features
• Two differential pairs of LVDS or HCSL outputs
• Two pairs of differential inputs accept LVDS or HCSL
logic levels
• 267MHz maximum frequency
• Ultra-low phase jitter:
− 137fsRMS, 200MHz (12kHz–20MHz)
− 153fsRMS, 156.25MHz (12kHz–20MHz)
− 212fsRMS, 100MHz (12kHz–20MHz)
• <2ps total jitter (peak-to-peak), 200MHz (BER = 10−12)
• 50ps output-to-output skew
• 3.3V ±5% power supply operation
• −40°C to +85°C operating temperature
• Available in 16-pin (3mm × 3mm) QFN lead-free
package
Applications
• Blade servers
• Desktop servers
• Workstations
• Storage area networks
• IP routers and switches
• Telecom and datacom
• High performance computing
Micrel, Inc.
SY75572L
D
ecember 5, 2014 2 Revision 1.0
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Ordering Information(1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY75572LMG QFN-16 Industrial 572L
with Pb-Free bar-line indicator NiPdAu
SY75572LMG TR(2) QFN-16 Industrial 572L
with Pb-Free bar-line indicator NiPdAu
Notes:
1. Contact f act ory for die availabi lity. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and reel.
Pin Configuration
16-Pin QFN
Micrel, Inc.
SY75572L
D
ecember 5, 2014 3 Revision 1.0
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Pin Description
Pin Number Pin Name Pin Function
1 /IN1 HCSL/LVDS inverted input 1.
2 PDB PDB = 0 powers down the chip and tri-states outputs. The pin is attached to an inter nal pul l-up
resistor.
3 IN2 HCSL/LVDS input 2.
4 /IN2 HCSL/LVDS inverted input 2.
5 OE Tri-state outputs. High = enable outputs. Low = disable outputs. Internal pull-up resistor, outputs
are enabled by default.
6 GND Ground.
7 IREF External resistor RREF between pin IREF and GND controls reference current.
8 /Q1 Inverted Output 1.
9 Q1 Non-inverted Output 1.
10 VDD 3.3V power supply.
11 GND Ground.
12 /Q0 Inverted Output 0.
13 Q0 Non-inverted Output 0.
14 SEL SEL = 0 propagates IN2, /IN2 to outputs. SEL = 1 propagates IN1, /IN1 to outputs. Internal pull-
up resistors , IN1, /IN1 is selected by default.
15 VDDIN 3.3V power supply.
16 IN1 HCSL/LVDS input 1.
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D
ecember 5, 2014 4 Revision 1.0
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Absolute Maximum Ratings(3)
Supply Voltage (VDD, VDDIN) ........................................... 5.5V
Input Voltage (VIN) .............................. –0.5V to VDDIN + 0. 5 V
Lead Temperature (soldering, 20s) ............................ 260°C
Maximum Junction Temperature................................ 125°C
Storage Temperature (Ts) ......................... –65°C to +150°C
ESD Protection (input) ....................................... 2000V min.
Operating Ratings(4)
Supply Voltage (VDD, VDDIN) ...................... 3.135V to 3.465V
Ambient Op Temperature (TA) .................... −40°C to +85°C
Package Thermal Resistance(5)
QFN-16
Still-air (θJA) ................................................. 59°C/W
Junction-to-board (ψJB) ............................... 38°C/W
DC Electrical Characteristics(6)
VDD = VDDIN = 3.135V to 3.465V, TA = −40°C to +85°C, unless otherwise stated. RREF = 475Ω
Symbol Parameter Condition Min. Typ. Max. Units
VDD, VDDIN Power Supply Voltage Range 3.135 3.3 3.465 V
CIN Input Capacitance 6 pF
COUT Output Capacitance 5 pF
LPIN Pin Inductance 4 nH
ROUT Output Resistance 3 kΩ
RPULL-UP Pull up Resistance SEL, PDB, OE 110 kΩ
VIH Input High Voltage SEL, PDB, OE 2 VDDIN + 0.3 V
VIL Input Low Voltage SEL, PDB, OE −0.3 0.8 V
VIH Input High Voltage HCSL, IN, /IN 660 750 850 V
VIL Input Low Voltage HCSL, IN, /IN −150 0 V
VIN Differential Input Voltage Range LVDS, IN, /IN 250 350 550 mV
VINPUT OFFSET Input Common Mode Voltage LVDS, IN, /IN, 1.125 1.25 1.375 V
VOH Output High Voltage HSCL 660 750 850 mV
VOL Output Low Voltage HSCL −150 0 27 mV
VCROSS(7, 8) Crossing Point Voltage Absolute 250 350 550 mV
VCROSS_VARIATION(7, 8, 9) Variation of Crossing Point Voltage Variation over all edges 140 mV
IDD Power Supply Current For
VDD + VDDIN
50Ω, 2pF 42 60 mA
No load, PDB = Low 0.4 mA
OE = Logic Low 20 mA
IIL(10) Input Lea kag e Current 0 < VIN < VDDIN −5 5 µA
Notes:
3. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not impli ed
at conditions other than thos e detailed in the operati onal sections of this datas heet. Exposure to absolute maximum ratings conditions for extended
periods may affect device reliabil i ty.
4. The datas heet limits are not guaranteed i f the device is operated beyond the operating ratings.
5. Package t hermal resist ance assumes that the exposed pad is soldered (or equivalent) t o the devic e's most negati ve potential on the PCB. ψJB and
θJA values are determined for a 4-layer board in still-air unless ot herwise st ated. The circuit is desi gned to meet the DC specifications s hown in the
above table after thermal equil i bri um has been established.
6. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equil i bri um has been established.
7. Test s etup is RL = 50Ω with 2pF, RREF = 475Ω ±1%.
8. Measurement taken from Q and /Q.
9. Measured at t he crossing point where instantaneous voltages of Q and /Q are equal.
10. Inputs with pull -up/pull-down resistances are not included.
Micrel, Inc.
SY75572L
D
ecember 5, 2014 5 Revision 1.0
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AC Electrical Characteristics(6)
VDD = VDDIN = 3.135V to 3.465V, TA = −40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min. Typ. Max. Units
fMAX Maximum Frequency HCSL 267
MHz
LVDS 100
tPD Propagation Delay Note 11 2 3 ns
tSKEW Output-to-Output sk ew Notes 12, 13 50 ps
tr, tf Output Rise/Fall Times
0.175V to 0.525V / 0.525V to 0.175V At full output swing.
50Ω, 2pF 150 350 700 ps
Tr/f_VAR Rise/Fall Time Variation At full output swi ng.
50Ω, 2pF 125 ps
TJITTER Phase Jitter
At 200MHz 137 fsrms
At 156.25MHz 153 fsrms
At 100MHz 212 fsrms
TTJ_JITTER Total Jitter BER = 10
-12
, TDJ = 0, at 200MHz 2 ps
TOE_ENABLE Output Enable Time All Outputs 2 µs
TOE_DISABLE Output Disable Time All Outputs 10 ns
TDCY Duty C ycle 45 50 55 %
Notes:
11. Measured from the diff erent i al input crossing poi nt t o the differenti al output crossi ng point.
12. Output-to-output skew is the difference in time between outputs, receiving data from the same input, for the same temperature, volt age, and
transition.
13. This paramet er is defined i n accordance with JEDEC Standard 65.
Jitter Analysis
Jitter is defined as the deviation of a signal from its ideal
position. Phase noise is the presence of signal energy at
frequencies other than the carrier. Random jitter has a
Gaussian distribution and is specified as an RMS unit,
which is one standard deviation of the distribution. Since
Gaussian distribution is unbounded in an infinite sample,
no communication system can be completely error free.
Instead, c omm unication li nk s are rated wit h a m aximum bit
error rate (BER), which is typically around 10-12 for high-
speed communication equipment. Achieving a desired
BER requires accounting for a number of standard
deviations of random noise by using the appropriate value
for N (see Table 1) in the formula in Equation 1.
TJ = N × RJ + DJ Eq. 1
Where TJ is total jitter, RJ is random jitter, and DJ is
determ inistic j itt er. If r outi ng c lock signals, t he deterministic
jitter is usually negligible and the TJ is dominated by the
random jitter. Calculating TJ from RJ using Equation 1
gives the values in Table 1.
Table 1. Standard Deviations of Random Noise
BER N Rj at 200MHz Tj at 200MHz
10-10 12.723 137fsRMS 1.743ps
10-11 13.412 137fsRMS 1.837ps
10-12 14.069 137fsRMS 1.927ps
10-13 14.698 137fsRMS 2.013ps
Micrel, Inc.
SY75572L
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ecember 5, 2014 13 Revision 1.0
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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