PurePathDigital
0,1
1
10
tal Harmonic Distortion - %
4Ohm (6kHz)
4Ohm (1kHz)
TOTAL HARMONIC DISTORTION+NOISE
VS
OUTPUT POWER
TC = 75 C
CONFIG = BTL
0,001
0,01
0,1
1
10
0,01 1 100
THD+N - Total Harmonic Distortion - %
PO- Output Power - W
4Ohm (6kHz)
4Ohm (1kHz)
TOTAL HARMONIC DISTORTION+NOISE
VS
OUTPUT POWER
TC = 75 C
CONFIG = BTL
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
150W STEREO / 300W MONO PurePath™HD ANALOG-INPUT POWER STAGE
Check for Samples: TAS5613A
1FEATURES •Thermally Enhanced Package Options:
–PHD (64-pin QFP)
23•Active Enabled Integrated Feedback Provides:
(PurePath™HD) –DKD (44-pin PSOP3)
–Signal Bandwidth up to 80kHz for High APPLICATIONS
Frequency Content From HD Sources
–Ultra Low 0.03% THD at 1W into 4Ω • Home Theater Systems
–Flat THD at all Frequencies for Natural •AV Receivers
Sound •DVD/ Blu-ray Disk™Receivers
–80dB PSRR (BTL, No Input Signal) •Mini Combo Systems
– >100dB (A Weighted) SNR •Active Speakers and Subwoofers
–Click and Pop Free Startup and Stop DESCRIPTION
•Pin compatible with TAS5630, TAS5615 and The TAS5613A is a high-performance analog input
TAS5611 Class D amplifier with integrated closed loop
•Multiple Configurations Possible on the Same feedback technology (known as PurePath™HD). It
PCB: has the ability to drive up to 150 W.(1) Stereo into 4Ω
–Mono Parallel Bridge Tied Load (PBTL) speakers from a single 36V supply.
–Stereo Bridge Tied Load (BTL) PurePath™HD technology enables traditional
–2.1 Single Ended (SE) Stereo Pair and AB-Amplifier performance (<0.03% THD) levels while
Bridge Tied Load Subwoofer providing the power efficiency of traditional class D
amplifiers.
•Total Output Power at 10%THD+N Unlike traditional Class-D amplifiers, the distortion
–300W in Mono PBTL Configuration curve only increases once the output levels move into
–150W per Channel in Stereo BTL clipping.
Configuration PurePath™HD technology enables lower idle losses
•Total Output Power in BTL Configuration at making the device even more efficient.
1%THD+N
–160W Stereo into 3Ω
–125W Stereo into 4Ω
–85W Stereo into 6Ω
–65W Stereo into 8Ω
• >90% Efficient Power Stage With 60-mΩ
Output MOSFETs
•Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short Circuit Protection) With Error Reporting
•EMI Compliant When Used With
Recommended System Design
(1) Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve high
output power levels
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Blu-ray Disk is a trademark of Blu-ray Disc Association.
3All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains Copyright ©2010–2011, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
26
16
15
OC_ADJ
14
RESET
13
C_STARTUP
12
INPUT_A
11
INPUT_B
10
VI_CM
9
GND
8
AGND 7
VREG
6
INPUT_C
5
INPUT_D
4
FREQ_ADJ
3
OSC_IO+
2
OSC_IO-
1
SD 64-pins QFP package
32
GND_D
31
PVDD_D
30
PVDD_D
29
OUT_D
28
OUT_D
27
BST_D
GVDD_D
25
GVDD_C
24
GND
23
GND
22 NC
21 NC
20 NC
19 NC
18 PSU_REF
17 VDD
33 GND_D
34 GND_C
35 GND_C
36 OUT_C
37 OUT_C
38 PVDD_C
39 PVDD_C
40 BST_C
41 BST_B
42 PVDD_B
43 OUT_B
44
GND_B
45
GND_A
46
47
48
55
49
50
51
READY
52
M1
53
M2
54
M3
GND
56
GND
57
GVDD_B
58
GVDD_A
59
BST_A
60
OUT_A
61
OUT_A
62
PVDD_A
63
PVDD_A
64
GND_A
OTW1
CLIP
PVDD_B
OUT_B
GND_B
OTW2
PHD PACKAGE
(TOP VIEW)
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
DKD PACKAGE
(TOP VIEW)
44 pins PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23M3
OC_ADJ
VDD
PSU_REF
M2
M1
READY
OTW
SD
OSC_IO-
OSC_IO+
FREQ_ADJ
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
RESET
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
GND_D
GVDD_AB
GVDD_CD
PVDD_A
PVDD_D
OUT_D
OUT_A
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Pin Assignment
The TAS5613A is available in two thermally enhanced packages:
•64-Pin QFP (PHD) Power Package
•44-Pin PSOP3 Package (DKD)
The package type contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
2Copyright ©2010–2011, Texas Instruments Incorporated
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
MODE SELECTION PINS
MODE PINS OUTPUT
ANALOG DESCRIPTION
INPUT CONFIGURATION
M3 M2 M1
0 0 0 Differential 2 ×BTL AD mode
0 0 1 — — Reserved
0 1 0 Differential 2 ×BTL BD mode
Differential
(BTL)
0 1 1 1 ×BTL + 2 ×SE BTL = BD mode, SE = AD mode
Single Ended
(SE)
1 0 0 Single Ended 4 ×SE AD mode
INPUT_C(1) INPUT_D(1)
1 0 1 Differential 1 ×PBTL 0 0 AD mode
1 0 BD mode
1 1 0 Reserved
1 1 1
(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=GND).
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER TAS5613APHD TAS5613ADKD
RθJC (°C/W) –2 BTL or 4 SE channels 3.2 2.1
RθJC (°C/W) –1 BTL or 2 SE channel(s) 5.4 3.5
RθJC (°C/W) –1 SE channel 7.9 5.1
Pad Area (2) 64 mm280 mm2
(1) JCis junction-to-case, CH is case-to-heat sink
(2) RθHis an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and both
channels active. The RθCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package.
Table 1. ORDERING INFORMATION (1)
TAPACKAGE DESCRIPTION
TAS5613APHD 64 pin HTQFP
0°C–70°CTAS5613ADKD 44 pin PSOP3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright ©2010–2011, Texas Instruments Incorporated 3
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TAS5613A UNIT
VDD to GND –0.3 to 13.2 V
GVDD to GND –0.3 to 13.2 V
PVDD_X to GND_X(2) –0.3 to 53 V
OUT_X to GND_X(2) –0.3 to 53 V
BST_X to GND_X(2) –0.3 to 66.2 V
BST_X to GVDD_X(2) –0.3 to 53 V
VREG to GND –0.3 to 4.2 V
GND_X to GND –0.3 to 0.3 V
GND to AGND –0.3 to 0.3 V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, –0.3 to 4.2 V
PSU_REF to GND
INPUT_X –0.3 to 7 V
RESET, SD, OTW, OTW1, OTW2, CLIP, READY to GND –0.3 to 7 V
Continuous sink current (SD, OTW, OTW1, OTW2, CLIP, READY) 9 mA
Operating junction temperature range, TJ0 to 150 °C
Storage temperature, Tstg –40 to 150 °C
Human-Body Model(3) (all pins) ±2 kV
Electrostatic discharge Charged-Device Model(3) (all pins) ±500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
4Copyright ©2010–2011, Texas Instruments Incorporated
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 18 36 38 V
Supply for logic regulators and
GVDD_x DC supply voltage 10.8 12 13.2 V
gate-drive circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4
Output filter according to Figure 12 and
RL(SE) Load impedance 2.8 3 Ω
Figure 13
RL(PBTL) 1.6 2
Output filter according to Figure 12 +
RL(BTL) Load impedance 2.8 3 Ω
Schottky, ROC = 22kΩ
LOUT(BTL) 7 10
LOUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 μH
LOUT(PBTL) 7 10
Nominal 385 400 415
PWM frame rate selectable for AM
FPWM interference avoidance; 1% AM1 315 333 350 kHz
Resistor tolerance AM2 260 300 335
Nominal; Master mode 9.9 10 10.1
PWM frame rate programming
RFREQ_ADJ AM1; Master mode 19.8 20 20.2 kΩ
resistor AM2; Master mode 29.7 30 30.3
CPVDD PVDD close decoupling capacitors 2.0 μF
ROC Over-current programming resistor Resistor tolerance = 5% 22 30 kΩ
ROC_LATCHED Over-current programming resistor Resistor tolerance = 5% 47 64 kΩ
Voltage on FREQ_ADJ pin for
VFREQ_ADJ Slave mode 3.3 V
slave mode operation
TJJunction temperature 0 125 °C
PIN FUNCTIONS
PIN FUNCTION(1) DESCRIPTION
NAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP 18 –O Clipping warning; open drain; active low
C_STARTUP 3 5 O Startup ramp requires a charging capacitor of 4.7nF to GND
FREQ_ADJ 12 14 I PWM frame rate programming pin requires resistor to GND
7, 23, 24,
GND 9 P Ground
57, 58
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 –P Gate drive voltage supply requires 0.1 μF capacitor to GND_A
GVDD_B 56 –P Gate drive voltage supply requires 0.1 μF capacitor to GND_B
GVDD_C 25 –P Gate drive voltage supply requires 0.1 μF capacitor to GND_C
GVDD_D 26 - P Gate drive voltage supply requires 0.1 uF capacitor to GND_D
GVDD_AB –44 P Gate drive voltage supply requires 0.22 μF capacitor to GND_A/GND_B
GVDD_CD –23 P Gate drive voltage supply requires 0.22 μF capacitor to GND_C/GND_D
(1) I = Input, O = Output, P = Power
Copyright ©2010–2011, Texas Instruments Incorporated 5
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
PIN FUNCTIONS (continued)
PIN FUNCTION(1) DESCRIPTION
NAME PHD NO. DKD NO.
INPUT_A 4 6 I Input signal for half bridge A
INPUT_B 5 7 I Input signal for half bridge B
INPUT_C 10 12 I Input signal for half bridge C
INPUT_D 11 13 I Input signal for half bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59-62 – – No connect, pins may be grounded.
OC_ADJ 1 3 O Analog over current programming pin requires 30kΩresistor to ground:
OSC_IO+ 13 15 I/O Oscillator master/slave output/input.
OSC_IO–14 16 I/O Oscillator master/slave output/input.
/OTW - 18 O Overtemperature warning signal, open drain, active low.
OTW1 16 –O Overtemperature warning signal, open drain, active low.
OTW2 17 –O Overtemperature warning signal, open drain, active low.
OUT_A 52, 53 39, 40 O Output, half bridge A
OUT_B 44, 45 36 O Output, half bridge B
OUT_C 36, 37 31 O Output, half bridge C
OUT_D 28, 29 27, 28 O Output, half bridge D
PSU_REF 63 1 P PSU Reference requires close decoupling of 330pF to GND
Power supply input for half bridges A requires close decoupling of 2μF capacitor to
PVDD_A 50, 51 41, 42 P GND_A.
Power supply input for half bridges B requires close decoupling of 2μF capacitor to
PVDD_B 42, 43 35 P GND_B.
Power supply input for half bridges C requires close decoupling of 2μF capacitor to
PVDD_C 38, 39 32 P GND_C.
Power supply input for half bridges D requires close decoupling of 2μF capacitor to
PVDD_D 30, 31 25, 26 P GND_D.
READY 19 19 O Normal operation; open drain; active high
RESET 2 4 I Device reset Input; active low, requires 47kΩpull up resistor to VREG
SD 15 17 O Shutdown signal, open drain, active low
Power supply for internal voltage regulator requires a 10-μF capacitor with a 0.1-μF
VDD 64 2 P capacitor to GND for decoupling.
VI_CM 6 8 O Analog comparator reference node requires close decoupling of 1nF to GND
VREG 9 11 P Internal regulator supply filter pin requires 0.1-μF capacitor to GND
6Copyright ©2010–2011, Texas Instruments Incorporated
2-CHANNEL
H-BRIDGE
BTL MODE
Output
H-Bridge 2
PVDD_A, B, C, D
GND_A, B, C, D
Hardwire
Over-
Current
Limit
8
GND
VDD
VREG
AGND
OC_ADJ
PVDD
PowerSupply
Decoupling
GVDD, VDD,
& VREG
PowerSupply
Decoupling
SYSTEM
Power
Supplies
PVDD
GVDD (12V)/VDD (12V)
GND
36V
12V
GND
VAC
Bootstrap
Caps
BST_C
BST_D
2nd Order
L-COutput
Filterfor
each
H-Bridge
OUT_C
OUT_D
GVDD_A, B, C, D
Bootstrap
Caps
BST_A
BST_B
INPUT_A 2nd Order
L-COutput
Filterfor
each
H-Bridge
OUT_A
OUT_B
8 4
Output
H-Bridge 1
Input
H-Bridge 1
INPUT_B
M2
M1
M3
Hardwire
Mode
Control
Input
H-Bridge 2
INPUT_C
INPUT_D
VI_CM
C_STARTUP
PSU_REF
Caps for
External
Filtering
&
Startup/Stop
InputDC
Blocking
Caps
InputDC
Blocking
Caps
System
microcontroller
or
Analogcircuitry
READY
ANALOG_IN_A
ANALOG_IN_B
ANALOG_IN_C
ANALOG_IN_D
FREQ_ADJ
Hardwire
PWMFrame
Rate Adjust
&
Master/Slave
Mode
OSC_IO+
OSC_IO-
Oscillator
Synchronization
2
2
2
2
(2)
SD
RESET
CLIP
OTW1OTW2OTW, ,
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
TYPICAL SYSTEM BLOCK DIAGRAM
Copyright ©2010–2011, Texas Instruments Incorporated 7
M1
M2
RESET
SD
OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD_C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_X
OUT_X
GND_ X
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
PWM
RECEIVER
ANALOGINPUTMUX
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
+
-
+
-
+
-
PROTECTION & I/O LOGIC
VI_CM
PSU_FF
POWER-UP
RESET
TEMP
SENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
OSCILLATOR
FREQ_ADJ
OSC_SYNC_IO-
PSU
GND
_REF
4
4
4
OSC_SYNC_IO+
OTW1
READY
CLIP
ANALOGCOMPARATORMUX
STARTUP
CONTROL
PVDD_X
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
8Copyright ©2010–2011, Texas Instruments Incorporated
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
AUDIO CHARACTERISTICS (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 36V,
GVDD_X = 12V, RL= 4Ω, fS= 400kHz, ROC = 30kΩ, TC= 75°C, Output Filter: LDEM = 7μH, CDEM = 680nF, mode = 010,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 3Ω, 10% THD+N (ROC = 22kΩ, add 200
Schottky diodes from OUT_X to GND_X)
RL= 4Ω, 10% THD+N 150
POPower output per channel W
RL= 3Ω, 1% THD+N (ROC = 22kΩ, add 160
Schottky diodes from OUT_X to GND_X)
RL= 4Ω, 1% THD+N 125
THD+N Total harmonic distortion + noise 1 W 0.03%
A-weighted, AES17 filter, Input Capacitor
VnOutput integrated noise 185 μV
Grounded
|VOS| Output offset voltage Inputs AC coupled to GND 8 25 mV
SNR Signal-to-noise ratio(1) 100 dB
DNR Dynamic range 100 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO= 0, 4 channels switching(2) 1.8 W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO CHARACTERISTICS (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 36V,
GVDD_X = 12V, RL= 2Ω, fS= 400 kHz, ROC = 30kΩ, TC= 75°C, Output Filter: LDEM = 7μH, CDEM = 680nF, MODE = 101-BD,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 2Ω, 10% THD+N 300
RL= 3Ω, 10% THD+N 200
RL= 4Ω, 10% THD+N 160
POPower output per channel W
RL= 2Ω, 1% THD+N 250
RL= 3Ω, 1% THD+N 160
RL= 4Ω, 1% THD+N 130
THD+N Total harmonic distortion + noise 1 W 0.05%
VnOutput integrated noise A-weighted 182 μV
SNR Signal to noise ratio(1) A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO= 0, 4 channels switching(2) 1.8 W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
Copyright ©2010–2011, Texas Instruments Incorporated 9
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC(Case temperature) = 75°C, fS= 400kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG Voltage regulator, only used as reference node VDD = 12V 3 3.3 3.6 V
Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 20
IVDD VDD supply current mA
Idle, reset mode 20
50% duty cycle 10
IGVDD_x Gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output filter 12.5 mA
IPVDD_x Half-bridge idle current Reset mode, No switching 620 μA
ANALOG INPUTS
RIN Input resistance READY = HIGH 33 kΩ
VIN Maximum input voltage swing 7 V
IIN Maximum input current 1 mA
G Inverting voltage Gain, (VOUT/VIN) 21 dB
OSCILLATOR
Nominal, Master Mode 3.85 4 4.15
fOSC_IO+ AM1, Master Mode FPWM ×10 3.15 3.33 3.5 MHz
AM2, Master Mode 2.6 3 3.35
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) 60 100 mΩ
TJ= 25°C, Includes metallization resistance,
RDS(on) GVDD = 12V
Drain-to-source resistance, high side (HS) 60 100 mΩ
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
Vuvp,G 9.5 V
VDD
Vuvp,hyst (1) 0.6 V
Overtemperature warning 1, OTW1(1) 95 100 105 °C
OTW Overtemperature warning 2, OTW, OTW2(1) 115 125 135 °C
Temperature drop needed below OTW
OTWHYST (1) temperature for OTW to be inactive after OTW 25 °C
event.
OTE(1) Overtemperature error 145 155 165 °C
OTE-OTWdifferential OTE-OTW differential 30 °C
(1)
A reset needs to occur for SD to be released
OTEHYST (1) 25 °C
following an OTE event
OLPC Overload protection counter fPWM = 400kHz 2.6 ms
Resistor –programmable, nominal peak current in 14
1Ωload, ROCP = 30kΩ
IOC Overcurrent limit protection A
Resistor –programmable, nominal peak current in
1Ωload, ROCP = 22kΩ(with Schottky diodes on 18
output nodes)
Resistor –programmable, peak current in 1Ωload, 14
ROCP = 64kΩ
IOC_LATCHED Overcurrent limit protection A
Resistor –programmable, nominal peak current in
1Ωload, ROCP = 47kΩ(with Schottky diodes on 18
output nodes)
Time from switching transition to flip-state induced
IOCT Overcurrent response time 150 ns
by overcurrent.
Connected when RESET is active to provide
IPD Output pulldown current of each half 3 mA
bootstrap charge. Not used in SE mode.
(1) Specified by design.
10 Copyright ©2010–2011, Texas Instruments Incorporated
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC(Case temperature) = 75°C, fS= 400kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
VIL Low level input voltage 0.8 V
Leakage Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to VREG,
RINT_PU 20 26 32 kΩ
OTW2 to VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6
VOH High level output voltage V
External pullup of 4.7kΩto 5V 4.5 5
VOL Low level output voltage IO= 4 mA 200 500 mV
Device fanout OTW1, OTW2, SD, CLIP,
FANOUT No external pullup 30 devices
READY
Copyright ©2010–2011, Texas Instruments Incorporated 11
0
50
100
150
200
250
18 20 22 24 26 28 30 32 34 36
PVDD-SupplyVoltage-V
6W
8W
P -OutputPower-W
O
T =75°C,
THD+N=10%
C
3W
4W
0.001
0.01
0.1
1
10
0.01 1 100
P -OutputPower-W
O
3W
4W
6W
8W
T =75°C
C
0.1 10 1000
THD+N-TotalHarmonicDistortion+Noise-%
100
90
80
70
60
50
40
30
20
10
0
0 50 100 150 200 250 300 350 400
2ChannelOutputPower-W
Efficiency-%
4W
6W
8W
T =25°C
THD+N=10%
C
18 20 22 24 26 28 30 32 34 36
PVDD-SupplyVoltage-V
3W
4W
6W
8W
T =75°C
C
0
50
100
150
200
P -OutputPower-W
O
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
Figure 1. Figure 2.
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY
vs vs
SUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
12 Copyright ©2010–2011, Texas Instruments Incorporated
30
20
10
0
0 50 100 150 200 250 300 350 400
2ChannelOutputPower-W
PowrLoss-W
4W
6W
8W
T =25°C
THD+N=10%
C
0
50
100
150
200
250
20 30 40 50 60 70 80 90 100
T -CaseTemperature-°C
C
3W
4W
6W
8W
THD+N=10%
P -OutputPower-W
O
-160
-140
-120
-100
-80
-60
-40
-20
0
0 5 10 15 20
f-Frequency-kHz
4W
T =75°C,
VREF=25.46V,
SampleRate=48kHz,
FFTsize=16384
C
Noise Amplitude-dB
0.001
0.01
0.1
1
10
THD+N-TotalHarmonicDistortion-%
10 100 1k 10k 100k
f-Frequency-Hz
R =4 ,
T =75°C,
ToroidalOutputInductors
L
C
W
1W
21 W (1/8 Power)
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS OUTPUT POWER
vs vs
OUTPUT POWER CASE TEMPERATURE
Figure 5. Figure 6.
NOISE AMPLITUDE TOTAL HARMONIC DISTORTION+NOISE
vs vs
FREQUENCY FREQUENCY
Figure 7. Figure 8.
Copyright ©2010–2011, Texas Instruments Incorporated 13
0.001
0.01
0.1
1
10
0.01 1 100
P -OutputPower-W
O
2W
3W
4W
6W
8W
T =75°C
C
0.1 10 1000
THD+N-TotalHarmonicDistortion+Noise-%
0
50
100
150
200
250
300
350
2W
3W
4W
6W
8W
T =75°C,
THD+N=10%
C
18 20 22 24 26 28 30 32 34 36
PVDD-SupplyVoltage-V
P -OutputPower-W
O
0
50
100
150
200
250
300
350
400
20 30 40 50 60 70 80 90 100
T -CaseTemperature-°C
C
P -OutputPower-W
O
4W
6W
8W
THD+N=10%
3W
2W
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
Figure 9. Figure 10.
OUTPUT POWER
vs
CASE TEMPERATURE
Figure 11.
14 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS5613A
TAS5613A
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SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2 oz. (70μm) is recommended for use with the TAS5613A. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
DECOUPLING CAPACITOR RECOMMENDATIONS
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2μF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50V is required for use with a 36V power
supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5613A.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TAS5613A
IN_LEFT_N
IN_LEFT_P
R_RIGHT_N
IN_RIGHT_P
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
OSC_IO+
OSC_IO-
GVDD/VDD (+12V)
PVDD
GVDD/VDD (+12V)
PVDD
PVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
GND
GND
GND
GND
GND
GND
VREG
VREG
GND
GND
GND
GND
GND
GND
GND
OUT_LEFT_P
OUT_LEFT_M
+
-
OUT_RIGHT_P
OUT_RIGHT_M
+
-
17
62
6318
19
64
20
21
24
23
22
25
27
26
29
28
30
31
32
1
33
34
35
37
2
3
36
4
38
39
5
6
7
40
41
8
9
42
10
43
11
44
45
12
46
47
13
48
14
15
49
16
50
51
52
54
53
56
55
57
58
59
60
61
R11
100R
R11
100R
R70
3.3R
R70
3.3R
C22
100nF
C22
100nF
L11L11
R32
3.3R
R32
3.3R
C70
1nF
C70
1nF
C31
100nF
C31
100nF
R30
3.3R
R30
3.3R
C52
680nF
C52
680nF
C77
10nF
C77
10nF
C78
10nF
C78
10nF
R73
3.3R
R73
3.3R
R31
3.3R
R31
3.3R
R74
3.3R
R74
3.3R
C72
1nF
C72
1nF
C18
100pF
C18
100pF
U10
TAS5613APHD
U10
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
L12L12
C53
680nF
C53
680nF
C68
47uF
63V
C68
47uF
63V
C65
1000uF
C65
1000uF
R71
3.3R
R71
3.3R
C75
10nF
C75
10nF
C63
2.0 uF
C63
R19
47k
R19
47k
R18
100R
R18
100R
C30
100nF
C30
100nF
C74
10nF
C74
10nF
C42
33nF
C42
33nF
R13
100R
R13
100R
C50
680nF
C50
680nF
C71
1nF
C71
1nF
R72
3.3R
R72
3.3R
C20
4.7nF
C20
4.7nF
C66
1000uF
C66
1000uF
C14
10uF
C14
10uF
L10L10
7 uH
C60C60
2.0 uF
C76
10nF
C76
10nF
R33
3.3R
R33
3.3R
C43
33nF
C43
33nF
C25
10uF
C25
10uF
C17
100pF
C17
100pF
C69
2.2uF
C69
2.2uF
C61
2.0 uF
C32
100nF
C32
100nF
C15
100pF
C15
100pF
C16
10uF
C16
10uF
C12
10uF
C12
10uF C13
100pF
C13
100pF
L13L13
C21
1nF
C21
1nF
R12
100R
R12
100R
C23
330pF
C23
330pF
C62
2.0 uF
C62
C26
100nF
C26
100nF
C73
1nF
C73
1nF
C51
680nF
C51
680nF
C64
1000uF
C64
1000uF
C10
10uF
C10
10uF
C67
1000uF
C67
1000uF
C33
100nF
C33
100nF
R20R20
30.0 kW
C41
33nF
C41
33nF
C11
100pF
C11
100pF
C40
33nF
C40
33nF
R21
10k
R21
10k
R10
100R
R10
100R 7 uH
7 uH
7 uH
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
Figure 12. Typical Differential Input BTL Application With BD Modulation Filters
16 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS5613A
IN_N
IN_P
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
GVDD (+12V)
PVDD
OSC_IO+
OSC_IO-
GVDD (+12V)
VDD (+12V)
PVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
GND
GND
GND GND
VREG
GND GND GND
GND
GND
GND
VREG
VREG
GND
GND
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+
-
OUT_LEFT_P
OUT_LEFT_M
3.3R3.3R
100nF100nF
4.7nF4.7nF
100nF100nF
100nF100nF
10uF10uF
330pF330pF
1000uF1000uF
3.3R3.3R
2.0 uF
47k47k
100nF100nF
1nF1nF
3.3R3.3R
33nF33nF
3.3R3.3R
1000uF1000uF
10uF10uF
10nF10nF
3.3R3.3R
100R100R
1nF1nF
100R100R
1000uF1000uF
680nF680nF
680nF680nF
47uF47uF
TAS5613APHD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
1nF1nF
10uF10uF
100pF100pF 10nF10nF
100nF100nF 33nF33nF 7 uH
2.0 uF
100R100R
3.3R3.3R
33nF33nF
3.3R3.3R
2.2uF2.2uF
10nF10nF
30.0 kW
100pF100pF
2.0 uF
10k10k
33nF33nF
100nF100nF
100pF100pF
2.0 uF
1000uF
63V
1000uF
63V
7 uH
7 uH
7 uH
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
Figure 13. Typical Differential (2N) PBTL Application With BD Modulation Filters
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TAS5613A
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5613A needs only a 12V supply in addition to the (typical) 36V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has
separate bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Gate drive supply (GVDD_X) is
separate for each half bridge for the PHD package and separate per full bridge for the DKD package.
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12V source, separating to GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board
(PCB) by RC filters (see application diagram for details) is recommended. These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5613A reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5613A is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5613A does not require a power-up sequence. The outputs of the H-bridges remain in a
high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
Powering Down
The TAS5613A does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
18 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS5613A
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Also, OTW and OTW2 go low when
the device junction temperature exceeds 125°C, and OTW1 goes low when the junction temperature exceeds
100°C (seeTable 2).
Table 2. Error Reporting
SD OTW1 OTW2, OTW DESCRIPTION
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction temperature higher than 125°C
(overtemperature warning)
0 0 1 Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0 1 1 Overload (OLP) or undervoltage (UVP). Junction temperature lower than 100°C
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW
outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5613A contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5613A responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in Table 3.
Table 3. Device Protection
BTL MODE PBTL MODE SE MODE
LOCAL LOCAL LOCAL
TURNS OFF TURNS OFF TURNS OFF
ERROR IN ERROR IN ERROR IN
AAA
A+B A+B
BBB
A+B+C+D
CCC
C+D C+D
DDD
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert SD).
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,
all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TAS5613A
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is <15ms/μF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
PHD Package
The TAS5613A PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5613A DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5613A fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low.
Asserting reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high.
A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
20 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS5613A
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs and needs to be slaved from an external differential clock.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 12.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 14. Printed Circuit Board - Top Layer
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TAS5613A
TAS5613A
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
www.ti.com
Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 15. Printed Circuit Board - Bottom Layer
22 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS5613A
TAS5613A
www.ti.com
SLAS711B –JUNE 2010–REVISED SEPTEMBER 2011
REVISION HISTORY
Changes from Original (June 2010) to Revision A Page
•Deleted the DKD 44-Pin package from the Features ........................................................................................................... 1
•Deleted the DKD Package drawing from the Pin Assignment section ................................................................................. 2
•Deleted the TAS5613ADKD from the PACKAGE HEAT DISSIPATON RATINGS table ..................................................... 3
•Deleted the TAS5613ADKD from the ORDERING INFORMATION table ............................................................................ 3
•Changed the FPWM and RFREQ_ADJ values in the RECOMMENDED OPERATING CONDITIONS table ............................... 5
•Changed the TJ max value From: 150 To: 125 in the ROC table ........................................................................................ 5
•Deleted the DKD package from the PIN FUNCTIONS table ................................................................................................ 5
•Changed the values of the ANALOG INPUTS and OSCILLATOR section of the ELECTRICAL CHARACTERISTICS
table .................................................................................................................................................................................... 10
•Deleted the DKD Package section from the OVERTEMPERATURE PROTECTION section ........................................... 20
Changes from Revision A (March 2011) to Revision B Page
•Added the DKD 44-Pin package to the Features ................................................................................................................. 1
•Added the DKD Package drawing to the Pin Assignment section ....................................................................................... 2
•Added the TAS5613ADKD to the PACKAGE HEAT DISSIPATON RATINGS table ........................................................... 3
•Added the TAS5613ADKD to the ORDERING INFORMATION table .................................................................................. 3
•Added the DKD package to the PIN FUNCTIONS table ...................................................................................................... 5
•Changed Inverting voltage Gain, (VOUT/VIN) From: 20 dB To: 21 dB .................................................................................. 10
•Added text to the Power Supplies section .......................................................................................................................... 18
•Added text following Table 3 "(non-latching, does not assert SD)"................................................................................... 19
•Added the DKD Package section ....................................................................................................................................... 20
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TAS5613A
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TAS5613ADKD ACTIVE HSSOP DKD 44 29 Green (RoHS
& no Sb/Br) NIPDAU Level-4-260C-72 HR
TAS5613ADKDR ACTIVE HSSOP DKD 44 500 Green (RoHS
& no Sb/Br) NIPDAU Level-4-260C-72 HR
TAS5613APHD ACTIVE HTQFP PHD 64 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5613APHDR ACTIVE HTQFP PHD 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5613PHD NRND HTQFP PHD 64 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5613PHDR NRND HTQFP PHD 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2011
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5613ADKDR HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
TAS5613APHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
TAS5613PHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5613ADKDR HSSOP DKD 44 500 367.0 367.0 45.0
TAS5613APHDR HTQFP PHD 64 1000 367.0 367.0 45.0
TAS5613PHDR HTQFP PHD 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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