LT3640
1
3640f
Typical applicaTion
DescripTion
Dual Monolithic Buck
Regulator with Power-On
Reset and Watchdog Timer
The LT
®
3640 is a dual channel, current mode monolithic
buck switching regulator with a power-on reset and a
watchdog timer. Both regulators are synchronized to a
single oscillator with an adjustable frequency (350kHz to
2.5MHz). At light loads, both regulators operate in low
ripple Burst Mode
®
to maintain high efficiency and low
output ripple.
The high voltage channel is a nonsynchronous buck with
an internal 2.4A top switch that operates from an input
of 4V to 35V; a 36.5V OVLO protects the device to 55V.
The low voltage channel operates from an input of 2.5V to
5.5V. Internal synchronous power switches provide high
efficiency without the need of external Schottky diode.
Both channels have cycle-by-cycle current limit, providing
protection against shorted outputs.
The power-on reset and watchdog timeout periods are
both adjustable using external capacitors. The window
mode watchdog timer flags when the µP pulses group
too close together or too far apart.
The LT3640 is available in a 28-pin 4mm × 5mm QFN
package and 28-pin TSSOP package. Both packages have
an exposed pad for low thermal resistance.
2MHz 3.3V/0.8A and 1.8V/0.8A Step Down Regulators
FeaTures
applicaTions
n High Voltage Buck Regulator:
4V to 35V Operating Range
1.3A Output Current
n OVLO Protects Input to 55V
n Low Voltage Synchronous Buck Regulator:
2.5V to 5.5V Input Voltage Range
1.1A Output Current
n Synchronizable, Adjustable 350kHz to 2.5MHz
Switching Frequency
n Programmable Power-On Reset Timer
n Programmable Window Mode Watchdog Timer
n Typical Quiescent Current: 290µA
n Short-Circuit Robust
n Programmable Soft-Start
n Low Shutdown Current: IQ < 1µA
n Available in Thermally Enhanced 28-Lead
(4mm × 5mm) QFN and 28-Lead TSSOP Packages
n Industrial Power Supplies
n Automotive Electronic Control Units
3640 TA01a
SYNC
PGOOD
WDE
1nF
1nF
1.5nF
1.5nF
32.4k
VOUT2
1.8V/0.8A
VOUT1
3.3V/0.8A
22µF
10µF
100k
RST2 EN2
WDO
WDI
FB2
CWDT
CPOR RT GND SS2 SS1
RST1
SW2
SW1EN/UVLO VIN
VIN
5V TO 35V
SW
LT3640
BST
VIN2
FB1
1µH
100k
VOUT1
µP
100k
49.9k
80.6k
49.9k
3.3µH
0.22µF
DA 22µF
HV Channel Efficiency,
2MHz, VOUT1 = 3.3V
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LV Channel Efficiency,
2MHz, VOUT2 = 1.8V
VOUT1 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1.0
90
75
85
1.2
3640 TA01b
VIN = 12V
VOUT2 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1
90
75
85
3640 TA01c
VIN2 = 3.3V
LT3640
2
3640f
absoluTe MaxiMuM raTings
VIN, EN/UVLO Voltage (Note 7) .................................55V
WDE Voltage .............................................................30V
BST Above SW, SW1 Voltage ....................... –0.3V to 6V
SW1 Above SW Voltage ............................... –0.3V to 6V
VIN2, SYNC, EN2, PGOOD, WDI,
WDO, RST1, RST2, Voltages ....................... –0.3V to 6V
SS1, SS2, FB1, FB2, RT, CWDT,
CPOR Voltages………... ........................... –0.3V to 2.5V
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FB2
PGOOD
EN/UVLO
SYNC
SS1
FB1
RT
RST2
RST1
WDO
CWDT
CPOR
WDE
WDI
SS2
EN2
GND
SW2
VIN2
GND
VIN
BST
SW
SW1
DA
NC
GND
GND
29
GND
θJA = 30°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
SYNC
SS1
FB1
RT
RST2
RST1
WDO
CWDT
SW2
VIN2
GND
VIN
BST
SW
SW1
DA
EN/UVLO
PGOOD
FB2
SS2
EN2
GND
CPOR
WDE
WDI
GND
GND
NC
7
17
18
19
20
21
22
16
815
29
GND
θJA = 34°C/W, θJC = 2.7°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3640EFE#PBF LT3640EFE#TRPBF LT3640FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3640IFE#PBF LT3640IFE#TRPBF LT3640FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3640EUFD#PBF LT3640EUFD#TRPBF 3640 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LT3640IUFD#PBF LT3640IUFD#TRPBF 3640 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SW2 Voltage ................................ –0.3V to (VIN2 + 0.3V)
Operating Junction Temperature Range (Note 2)
LT3640E ................................................. –40°C to 125°C
LT3640I .................................................. –40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C
LT3640
3
3640f
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
elecTrical characTerisTics
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Undervoltage Lockout Threshold l3.6 4 V
VIN Undervoltage Release Threshold l3.8 4.2 V
VIN Overvoltage Lockout Threshold l35 36.5 38 V
VIN Overvoltage Release Threshold l34 35.5 37 V
Quiescent Current from VIN EN/UVLO = 0.3V
Not Switching
0.1
275
1
375
µA
µA
EN/UVLO Threshold Voltage 1.2 1.26 1.3 V
EN/UVLO High Bias Current EN/UVLO = Threshold + 60mV 2 µA
EN/UVLO Low Bias Current EN/UVLO = Threshold – 60mV 0.1 µA
SYNC Input Frequency 0.35 2.5 MHz
SYNC Threshold Voltage 0.4 0.8 1 V
Switching Frequency RT = 32.4k
RT = 182k
l
l
1.75
450
2
500
2.35
550
MHz
kHz
FB1 Voltage l1.24 1.265 1.29 V
FB1 Bias Current FB1 = 1.265V 30 100 nA
FB1 Line Regulation 5V < VIN < 30V 0.001 %/V
SW1 Minimum Off-Time 70 100 ns
SW1 VCESAT ISW1 = 800mA 400 mV
SW1 Leakage Current 0.1 1 µA
SW1 Current Limit FB1 = 1V (Note 3)
FB1 = 0.1V
l2.2 2.8
1.8
3.4 A
A
DA Current limit FB1 = 1V (Note 4)
FB1 = 0.1V
l1.35 1.7
1
2.2 A
A
BST Pin Current ISW1 = 800mA 30 50 mA
Minimum BST-SW Voltage 2 2.7 V
ΔFB1 to Start LV Channel 80 100 130 mV
ΔFB1 Hysteresis to Stop LV Channel 30 50 90 mV
VIN2 Minimum Operating Voltage l2.3 2.5 V
VIN2 Maximum Operating Voltage l5.5 V
EN2 Threshold Voltage 0.3 1 1.5 V
FB2 Voltage l588 600 612 mV
FB2 Bias Current FB2 = 0.6V 0 100 nA
FB2 Line Regulation 2.5V < VIN2 < 5.5V 0.01 %/V
SW2 Minimum Off-Time 70 100 ns
SW2 PMOS Current Limit (Note 5) l1.5 1.9 2.2 A
SW2 NMOS Current Limit (Note 5) l1.2 1.6 2 A
SW2 PMOS RDS(ON) ISW2 = 0.5A (Note 6) 275 mΩ
SW2 NMOS RDS(ON) ISW2 = 0.5A (Note 6) 200 mΩ
ΔFB2 to Enable PGOOD 20 40 80 mV
ΔFB2 Hysteresis to Disable PGOOD 20 40 80 mV
PGOOD Voltage FB2 = 0.6V, IPGOOD = 1mA 200 320 mV
LT3640
4
3640f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3640E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3640I is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SS1, SS2 Charge Current SS1 = 0.5V, SS2 = 0.5V 1.4 1.9 2.5 µA
SS1 to FB1 Offset Voltage SS1 = 0.6V 5 30 mV
SS2 to FB2 Offset Voltage SS2 = 0.3V 5 30 mV
RST1 Threshold as Percentage of VFB l90 92 94 %
RST2 Threshold as Percentage of VFB l89 92 94 %
Undervoltage to RST Assert Time 20 µs
RST1, RST2, WDO Pull-Up Current RST1, RST2, WDO = 0V 5 15 30 µA
RST1, RST2, WDO Output Voltage IRST1, IRST2, IWDO = 2mA 150 250 mV
RST1, RST2 Timeout Period (tRST) CPOR = 220pF l8 9.5 11 ms
Watchdog Start Delay Time (tDLY) CWDT = 820pF 14 16 18 ms
Watchdog Upper Boundary (tWDU) CWDT = 820pF l27 32 35 ms
Watchdog Lower Boundary (tWDL) CWDT = 820pF l1.68 2 2.2 ms
WDI Pull-Up Current WDI = 1.2V 2 µA
WDI Voltage Threshold 0.55 0.85 1.15 V
WDI Low Minimum Pulse Width 300 ns
WDI High Minimum Pulse Width 300 ns
WDE Pull-Down Current WDE = 2V 1 µA
WDE Threshold l0.5 0.7 0.9 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation
to static test. Slope compensation reduces current limit at higher duty
cycle.
Note 4: The oscillator cycle is extended when DA current exceeds its limit.
DA current limit is flat over duty cycle.
Note 5: If the SW2 NMOS current exceeds its limit at the start of an
oscillator cycle, the PMOS will not be turned on in the cycle.
Note 6: The QFN switch RDS(ON) is guaranteed by correlation to wafer level
measurement.
Note 7: Absolute maximum voltage at VIN and RUN/SS pin is 55V for
nonrepetitive one second transients, and 36V for continuous operation.
elecTrical characTerisTics
LT3640
5
3640f
Typical perForMance characTerisTics
LV Channel Efficiency
(2MHz, VOUT2 = 1.8V) Quiescent Current vs VIN Quiescent Current vs Temperature
HV Channel Efficiency
(2MHz, VOUT1 = 3.3V)
HV Channel Efficiency
(2MHz, VOUT1 = 5V)
LV Channel Efficiency
(2MHz, VOUT2 = 1.2V)
TA = 25°C, unless otherwise noted.
FB1 Voltage vs Temperature FB1 Voltage vs SS1 FB2 Voltage vs Temperature
VOUT1 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1.0
90
75
85
1.2
3640 G01
VIN = 12V
VIN = 24V
VIN = 16V
VOUT1 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1.0
90
75
85
1.2
3640 G02
VIN = 12V
VIN = 24V VIN = 16V
VOUT2 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1.0
90
75
85
3640 G04
VIN2 = 3.3V
VIN2 = 5V
VIN VOLTAGE (V)
0
VIN QUIESCENT CURRENT (mA)
0.20
0.25
0.30
0.15
0.10
20
10 30 40
0.05
0.00
0.35
3640 G05
TEMPERATURE (°C)
–50
FB1 VOLTAGE (V)
50
0100 150
3640 G07
1.00
1.10
1.20
1.30
1.40
1.05
1.15
1.25
1.35
REGULATION
RST1 THRESHOLD
SS1 VOLTAGE (V)
FB1 VOLTAGE (V)
1.00 0.5 1.5 2.0
3640 G08
0.0
0.4
0.8
1.2
1.4
0.2
0.6
1.0
TEMPERATURE (°C)
–50
FB2 VOLTAGE (V)
50
0100 150
3640 G09
0.45
0.55
0.65
0.70
0.50
0.60 REGULATION
RST2 THRESHOLD
VOUT2 CURRENT (A)
0
70
EFFICIENCY (%)
80
0.2 0.4 0.80.6 1.0
90
75
85
3640 G03
VIN2 = 3.3V
VIN2 = 5V
LT3640
6
3640f
Typical perForMance characTerisTics
FB2 Voltage vs SS2
Switching Frequency
vs Temperature
HV Channel Current Limit
vs Duty Cycle
VOUT1 Minimum Load to Run at
Full Frequency (VOUT1 = 3.3V)
HV Channel Switching Frequency
(VOUT1 = 3.3V)
LV Channel Switching Frequency
(VOUT2 = 1.8V)
LV Channel Peak Current Limit
vs Duty Cycle
LV Channel Switch Voltage
Drop vs Current (VIN2 = 3.3V)
TA = 25°C, unless otherwise noted.
SS2 VOLTAGE (mV)
FB2 VOLTAGE (mV)
3640 G10
0
200
400
600
700
100
300
500
0200 400 6000 800 1000
TEMPERATURE (°C)
–50
SWITCHING FREQUENCY (MHz)
50
0100 150
3640 G11
0.48
0.50
0.52
0.49
0.51
RT = 182k
DUTY CYCLE (%)
SW1 PEAK CURRENT LIMIT (A)
3640 G12
020 40 60 80 100
0.0
1.0
2.0
2.5
0.5
1.5
DUTY CYCLE (%)
SW2 PEAK CURRENT LIMIT (A)
3640 G13
020 40 60 80 100
0.0
1.0
2.0
0.5
1.5
SW2 CURRENT (A)
0
SW2 VOLTAGE DROP (mV)
300
350
400
250
200
0.5 1 1.5
50
0
150
450
100
3640 G14
PMOS
NMOS
VIN VOLTAGE (V)
0
VOUT1 CURRENT (A)
0.30
0.35
0.40
0.25
0.20
5 1510 20 25 30
0.05
0
0.15
0.45
0.10
3640 G15
2MHz
2.5MHz
VOUT1 CURRENT (A)
SWITCHING FREQUENCY (MHz)
3640 G16
0
1.0
2.0
2.5
0.5
1.5
00.2 0.4 0.6 0.8 1.0 1.2
VIN = 12V
VIN = 24V
VIN = 16V
RT = 32.4k
VOUT2 CURRENT (A)
SWITCHING FREQUENCY (MHz)
3640 G17
0
1.0
2.0
2.5
0.5
1.5
00.2 0.4 0.6 0.8 1.0
VIN2 = 3.3V
VIN2 = 5V
LT3640
7
3640f
Typical perForMance characTerisTics
Full Frequency Waveforms Light Load Operation Waveforms
TA = 25°C, unless otherwise noted.
Watchdog Upper Boundary
Period vs CWDT
Watchdog Upper Boundary
Period vs Temperature RST/WDO Pull-Up Current
200ns/DIV
SW1
10V/DIV
IL1
0.5A/DIV
SW2
5V/DIV
IL2
0.5A/DIV
3640 G18
VIN1 = 12V
VOUT1 = 3.3V/0.5A
VIN2 = VOUT1
VOUT2 = 1.8V/0.5A
500ns/DIV
SW1
10V/DIV
IL1
0.5A/DIV
SW2
5V/DIV
IL2
0.5A/DIV
3640 G19
VIN1 = 12V
VOUT1 = 3.3V/25mA
VIN2 = VOUT1
VOUT2 = 1.8V/30mA
CWDT CAPACITANCE (pF)
0
WATCHDOG UPPER BOUNDARY PERIOD (ms)
120
140
160
100
80
20001000 3000 4000 5000
20
0
60
180
40
3640 G20
TEMPERATURE (°C)
–50
WATCHDOG UPPER BOUNDARY PERIOD (ms)
20
25
30
15
10
50
0100 150
5
0
35
3640 G21
RST/WDO VOLTAGE (V)
0
RST/WDO PULL-UP CURRENT (µA)
1
0.5 1.5 2
3640 G22
0
10
20
5
15
LT3640
8
3640f
pin FuncTions
FB2 (Pin 1/Pin 26): The low voltage converter regulates the
FB2 pin to 600mV. Connect the feedback resistor divider
tap to this pin to set output voltage.
PGOOD (Pin 2/Pin 27): Open-drain logic output that starts
to sink current when FB2 is in regulation.
EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut
down the LT3640. The 1.26V threshold can function as an
accurate undervoltage lockout, preventing the LT3640 from
operating until VIN voltage has reached the programmed
level.
SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external
clock signal synchronizes both converters to the applied
frequency. The lowest external clock frequency should be
20% higher than the internal oscillator frequency.
SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage ex-
ternally between 0V and 1.265V, providing soft-start and
tracking. Tie this pin 1.5V or higher to use the internal
1.265V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the high voltage
converter. Use a resistor divider to track another supply.
FB1 (Pin 6/Pin 3): The high voltage converter regulates the
FB1 pin to 1.265V. Connect the feedback resistor divider
tap to this pin to set output voltage.
RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the internal oscillator
frequency.
RST2 (Pin 8/Pin 5): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB2 goes above 550mV.
RST1 (Pin 9/Pin 6): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB1 goes above 1.165V.
WDO (Pin 10/Pin 7): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor if
WDE is enabled and WDI pin is not driven by an appropri-
ate signal.
CWDT (Pin 11/Pin 8): Connect a capacitor to ground at
this pin to set watchdog timer.
CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this
pin to set the power-on reset timer and WDO output timer.
WDE (Pin 13/Pin 10): Watchdog Enable Pin.
WDI (Pin 14/Pin 11): The WDI pin receives watchdog
signals from a microprocessor.
GND (Pins 15, 16, 23, 26, Exposed Pad Pin 29/Pins 12,
13, 20, 23, Exposed Pad Pin 29): Ground. These pins
must be soldered to PCB ground.
NC (Pin 17/Pin 14): Not Connected. This pin can be con-
nected to ground.
DA (Pin 18/Pin 15): The DA pin is used to sense the catch
diode current for current limit and protection. Connect this
pin to catch diode anode.
SW1 (Pin 19/Pin 16): Output of the High Voltage Internal
Power Switch. Connect this pin to the inductor and catch
diode cathode.
SW (Pin 20/Pin 17): The SW pin is used to charge the
boost capacitor. Connect this pin to the boost capacitor.
BST (Pin 21/Pin 18): The BST pin is used to provide a drive
voltage, higher than VIN pin voltage, to the high voltage
channel internal power switch. Connect an external boost
diode to this pin.
VIN (Pin 22/Pin 19): The VIN pin supplies current to
the LT3640’s internal circuitry and to the high voltage
channel internal power switch. This pin must be locally
bypassed.
VIN2 (Pin 24/Pin 21): The VIN2 pin supplies current to the
internal power MOSFET of the low voltage converter and
to the LT3640’s internal circuitry when VIN2 is above 3V.
SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage
Converter. Connect this pin to an inductor.
EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin.
Pull this pin below 0.3V to shut down the low voltage
converter. Pull this pin above 1.5V to enable the low volt-
age converter.
SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage
externally between 0V and 0.6V, providing soft-start and
tracking. Tie this pin 0.8V or higher to use the internal
0.6V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the low voltage
converter. Use a resistor divider to track another supply.
(FE/QFN)
LT3640
9
3640f
block DiagraM
3640 BD
+
+
–
gm2
VREF
600mV
VOUT2
VOUT1
VC2
VC1
100k
5.5V
2µA
R2 FB1
SS1
EN/
UVLO ENABLE
BST
SW
SW1
DRIVER
L1
L2
DA
RT
SYNC
SW2
R1
+
–
2µA 2µA
+
+
–
gm1
2µA
+
–
2µA
+
–
A4
A8
+
–
A3
+
–
A2
+
–
A1
+
–
A7
A9
R4 FB2
50mV
PGOOD
R3
SS2
CPOR
3
3
VREF
1.265V
RAMP
GENERATOR
POR TIMER WATCHDOG
TIMER
OSCILLATOR
SLOGIC
CIRCUIT
R Q
S
R Q
+
–
A6
+
–
A5
VIN
CIN
VOUT1
VOUT2
VIN2
CIN2
CBST
COUT1
COUT2
DBST
Q1
D1
EN2
CWDT
RST1 RST2 WDE WDI WDO
+
–
+
–
LT3640
10
3640f
TiMing DiagraMs
The LT3640 is a dual channel, constant-frequency, current
mode monolithic buck switching regulator with power-on
reset and watchdog timer. Both channels are synchronized
to a single oscillator with frequency set by RT. Operation can
be best understood by referring to the Block Diagram.
Buck Regulators
The high voltage channel is a nonsynchronous buck
regulator that operates from the VIN pin. The start of each
oscillator cycle sets an SR latch and turns on the internal
NPN power switch. An amplifier and comparator monitor
the current flowing between the VIN and SW1 pins, turning
the switch off when this current reaches a level determined
by the voltage at VC1 node. An error amplifier measures
the output voltage through an external resistor divider tied
to the FB1 pin and servos the VC1 node. The reference
of the error amplifier is determined by the lower of the
internal reference and the voltage at the SS1 pin. If the error
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
operaTion
An active clamp (not shown) on the VC1 node provides
peak current limit. A DA pin current comparator extends
the oscillator cycle until the catch diode current is below
the valley current limit. Both the peak and valley current
limits help to control the inductor current in fault condi-
tions such as shorted output with high VIN. Both current
limits are reduced when the voltage at the FB1 pin is below
0.2V. This current foldback helps to control the inductor
current during start-up and overload.
The NPN power switch driver operates from either the VIN
pin or the BST pin. An external capacitor and diode are
used to generate a voltage between the BST and SW pins.
During the power-up of the LT3640, an internal 5mA current
source charges the external BST capacitor. The regulator
starts switching when the (BST-SW) voltage reaches the
2V threshold. The internal NPN power switch can be fully
saturated for efficient operation when the (BST-SW) volt-
age is between 2.3V and 5.5V.
The low voltage channel is a synchronous buck regulator
that operates from the VIN2 pin. It starts switching only
FB
RST
WDI
WDO
3640 TD
tRST
tUV
t < tWDL tRST
tDLY
t < tWDU
tWDL < t < tWDU
tWDU
tRST
Power-On Reset Timing
Watchdog Timing
LT3640
11
3640f
when the VIN2 pin voltage is above 2.3V, the EN2 pin is
pulled high and the FB1 pin voltage is above 1.165V. The
internal top power MOSFET is turned on each cycle at the
beginning of each oscillator cycle, and turned off when
the current flowing through the top MOSFET reaches a
level determined by the voltage at the VC2 node. An error
amplifier measures the output voltage through an external
resistor divider tied to the FB2 pin and servos the VC2
node. The reference of the error amplifier is determined by
the lower of the internal 600mV reference and the voltage
at the SS2 pin.
While the top MOSFET is off, the bottom MOSFET is turned
on in an oscillator cycle until the inductor current starts
to reverse. If the inductor current is higher than the valley
current limit at the beginning of an oscillator cycle, the top
MOSFET will not turn on in this cycle, limiting inductor
current in shorted output fault.
An internal regulator provides power to the control circuitry.
The regulator draws most power from the VIN2 pin and a
small portion of power from the VIN pin when the VIN2 pin
voltage is higher than 3V. If the voltage at VIN2 pin is lower
than 3V, the regulator draws all power from the VIN pin.
The EN/UVLO pin is used to put the LT3640 in shutdown,
reducing the input current to less than 1µA. The accurate
1.26V threshold of the EN/UVLO pin provides a program-
mable VIN undervoltage lockout through an external resistor
divider tied to the EN/UVLO pin. A 2µA hysteresis current
on the EN/UVLO pin prevents switching noise from shut-
ting down the LT3640.
The LT3640 has an overvoltage protection feature which
disables switching action in both channels when the VIN
pin voltage goes above 36V. When switching is disabled,
the LT3640 can sustain VIN voltages up to 55V for one
second.
Internal 2µA current sources charge the SS1 pin and
the SS2 pin up to about 2V. Soft-start or output voltage
tracking of the two channels can be independently imple-
mented with capacitors from the SS1 pin and the SS2 pin
to ground. Any overvoltage or undervoltage condition on
the VIN pin triggers an internal latch that discharges the
SS1 pin to below 100mV before it is released. If the EN2
pin goes low, the VIN2 voltage falls below 2.2V or the FB1
pin goes below 1.165V, the SS2 pin will be discharged to
below 100mV before it is released.
To optimize efficiency, the LT3640 switches to low ripple
Burst Mode operation in light load situations. Between
switching pulses, control-circuitry current is minimized.
A power good comparator with 40mV of hysteresis trips
when the low voltage channel is enabled and the FB2 pin is
above 550mV. The PGOOD pin is an open-drain output that
is pulled low when both the outputs are in regulation.
Power-On Reset and Watchdog Timer
The LT3640 includes one power-on reset timer for each
buck regulator and one common watchdog timer. Power-
on reset and watchdog timers are both adjustable using
external capacitors. Operation can be best understood by
referring to the Timing Diagram.
The RST1, RST2 and WDO pins are all open-drain outputs
with weak internal pull-ups to about 2V. The RST1 and RST2
pins are pulled low when the LT3640 is enabled and VIN is
above 3.6V. Once the FB1 pin rises above 1.165V, the high
voltage channel reset timer is started and RST1 is released
after the reset timeout period. The low voltage channel reset
timer is started once the FB2 pin rises above 550mV, and
releases RST2 after the reset timeout period.
The watchdog circuit monitors a µP’s activity. As soon
as both RST1 and RST2 are released, a delay timer is
started. The watchdog timer is started after the delay timer
times out. The LT3640 implements windowed watchdog
function for higher system reliability. The watchdog timer
detects falling edges on the WDI pin. If the falling edges
are grouped too close together or too far apart, the WDO
pin is pulled down and the reset timer is started. When the
reset timer times out, WDO is released and the watchdog
timer is again started after the delay period.
operaTion
LT3640
12
3640f
Setting the Output Voltages
The internal reference voltage is 1.265V for the high volt-
age channel, and 600mV for the low voltage channel. The
output voltages are set by resistor dividers according to
the following formulas:
R R V
V
R R V
V
OUT
OUT
2 1 1 265 1
4 3 0 6 1
1
2
= −
= −
•.
•.
Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
Switching Frequency
The LT3640 uses a constant-frequency PWM architecture
that can be programmed to switch from 350kHz to 2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary RT value for a desired switching
frequency.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz) RT (k)
0.35 267
0.5 182
1 82.5
2 32.4
2.2 27.4
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
efficiency.
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3640 switches have
finite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
applicaTions inForMaTion
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
DCMIN = fS • tON(MIN)
DCMAX = 1 – fS • tOFF(MIN)
where fS is the switching frequency, tON(MIN) is the mini-
mum switch on-time, and tOFF(MIN) is the minimum switch
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
The internal oscillator of the LT3640 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
the SYNC pin. The RT value should be chosen such that
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3640 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3640’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
VIN Voltage Range
The LT3640’s minimum operating voltage is 3.6V typical.
A higher minimum operating voltage can be accurately
programmed with a resistor divider between the VIN pin
and the EN/UVLO pin. The EN/UVLO threshold is 1.26V.
When the LT3640 is enabled, a 2µA current flows out of the
EN/UVLO pin generating hysteresis to prevent the switch-
ing action from falsely disabling the LT3640. Choose the
divider resistances for appropriate hysteresis voltage.
The high voltage nonsynchronous channel operates from
the VIN pin. The minimum VIN voltage to regulate output
voltage is:
VV V
DC V V
IN MIN OUT D
MAX D CE( ) =+
− +
1
Where VD is the forward voltage drop of the catch diode, VCE
is the voltage drop of the internal NPN power switch, and
DCMAX is the maximum duty cycle (refer to the Switching
Frequency section). If VIN is below the calculated minimum
voltage, output will lose regulation.
LT3640
13
3640f
Figure 1. Lower Switching Frequency Occurs in High
Voltage Channel When Required On-Time Is Below 50ns
The maximum VIN should not exceed the absolute maxi-
mum rating. For fixed frequency operation, the maximum
VIN is:
VV V
DC V V
IN MAX OUT D
MIN D CE( ) =+
− +
1
Note that the high voltage buck will still regulate at an input
voltage that exceeds VIN(MAX) (up to 35V). However, the
switching frequency will be lowered to satisfy the equa-
tion (Figure 1).
Once the input voltage reaches 36.5V, an internal overvoltage
lockout (OVLO) circuit is triggered to disable switching ac-
tion (Figure 2). Without switching, the LT3640 can sustain
VIN voltage transients up to 55V for one second.
VIN2 Voltage Range
The low voltage synchronous channel operates from
the VIN2 pin. The VIN2 pin can be connected to either an
independent voltage supply or the high voltage channel
output for a two-stage power regulator.
In either configuration, if the high voltage channel is over-
loaded and pulled out of regulation, the low voltage channel
will be disabled. The SS2 pin will be discharged as well.
The minimum VIN2 voltage to regulate output voltage is:
VV
DC
IN MIN OUT
MAX
22
( ) ≈
Where DCMAX is the maximum duty cycle (refer to
the Switching Frequency section). If VIN2 is below the
calculated minimum voltage, the output will fall out of
regulation.
The maximum VIN2 for fixed frequency operation is:
VV
DC
IN MAX OUT
MIN
22
( ) ≈
Where DCMIN is the minimum duty cycle (refer to the Switch-
ing Frequency section). For voltage that exceeds VIN2(MAX)
(up to 5.5V), the low voltage channel exhi-bits pulse-skip-
ping behavior, and the output ripple will increase.
Inductor Selection
Inductor selection involves inductance, saturation current,
series resistance (DCR) and magnetic loss.
The inductance for the high voltage channel is:
LV V
f
OUT D
S
1 1 7 1
=+
. •
where VOUT1 is high voltage channel output voltage, VD
is the forward voltage drop of the catch diode, and fS is
the switching frequency. For example, 3.3µH is a reason-
able inductance for a 3.3V output with 2MHz switching
frequency.
Once the inductance is selected, the inductor current ripple
and peak current can be calculated:
∆IV V
I f
V V
V
LOUT D
L S
OUT D
IN
11
1
1
1=+ +
( )
•• –
I I I
L PEAK OUT MAX L
( ) ( )
= + ∆
2
Figure 2. VIN Overvoltage Lockout
applicaTions inForMaTion
200ns/DIV
SW1
10V/DIV
IL1
0.5A/DIV
3640 F01
VIN = 30V
VOUT1 = 3.3V/0.2A
RT SET = 2MHz
10µs/DIV
VIN
20V/DIV
55VPK, 40V, 15V
IL1
2A/DIV
3640 F02
LT3640
14
3640f
applicaTions inForMaTion
To guarantee sufficient output current, peak inductor cur-
rent must be lower than the switch current limit (ILIM).
The largest inductor current ripple occurs at the highest
VIN. To guarantee current capacity, use VIN(MAX) in the
above formula.
The inductance for the low voltage channel is:
LV
f
OUT
S
2 1 5 2
=.
For a selected inductance, the inductor current ripple can
be calculated:
∆IV
L f
V
V
LOUT
S
OUT
IN
22 2
2
21=
•• –
For robust operation in fault conditions, the inductor
saturation current should be higher than the upper limit
of the corresponding top switch current limit.
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be < 0.1Ω),
and the core material should be intended for the chosen
operation frequency. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores; instead use ferrite, molypermalloy or Kool Mµ
cores. Table 2 lists several vendors and suitable inductor
series.
Table 2. Inductor Vendors
PART SERIES VENDOR
LQH55D Murata
www.murata.com
SLF7045
SLF10145
TDK
www.componenttdk.com
D62CB, D63CB
D75C, D75F
TOKO
www.toko.com
CR54, CDRH74
CDRH6D38, CR75
Sumida
www.sumida.com
Of course, such a simple design guide will not always
result in the optimum inductors for the applications. A
larger value inductor provides a slightly higher maximum
load current and will reduce the output voltage ripple. A
larger value inductor also results in higher efficiency in the
condition of same DCR and same magnetic loss. However,
for a same series of inductors, a larger value inductor has
higher DCR. The trade-off between inductance and DCR
is not always obvious. Use experiments to find optimum
inductors.
Low inductance may result in discontinuous mode opera-
tion, which is okay, but reduces maximum load current.
For details of maximum output current and discontinuous
mode operation, see the Linear Technology Application Note
44. For duty cycles greater than 50%, there is a minimum
inductance required to avoid subharmonic oscillations.
See the Linear Technology Application Note 19.
Input Capacitor
Bypass the VIN pin of the LT3640 with a ceramic capacitor
of X7R (–55°C to 125°C) or X5R (–55°C to 85°C) type.
Buck converters draw pulse current from the input sup-
ply. The input capacitor is required to reduce the resulting
voltage ripple. Use a ceramic capacitor with:
CµF
f
IN S
≥10
where fS in the switching frequency in MHz.
A second precaution regarding the ceramic input capacitor
concerns the maximum input voltage rating of the LT3640.
A ceramic input capacitor combined with trace or cable
inductance forms a under damped tank circuit. If the LT3640
circuit is plugged into a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
LT3640’s voltage rating. This situation can be easily avoided
(see the Linear Technology Application Note 80).
LT3640
15
3640f
Output Capacitors and Output Ripple
The output capacitor has two essential functions. In steady
state, it determines the output voltage ripple. In transient,
it stores energy in order to satisfy transient loads and
stabilize the control loop. Ceramic capacitors have low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
CV f
OUT OUT S
1
150
=•
where fS is in MHz, and COUT is the recommended output
capacitance in µF. Use X5R or X7R types. This choice will
provide low output ripple and good transient response.
A good starting value for the low voltage channel output
capacitor is:
CV f
OUT OUT S
22
100
=•
In the case where VIN2 is connected to the high voltage
channel output, the high voltage channel output capacitor
can be used as the low voltage channel input capacitor.
The required VIN2 input capacitor value is usually smaller
than the high voltage output capacitor.
Low ESR ceramic capacitors for VIN2 input and high volt-
age channel output could form resonant tank and cause
jitter in certain operating area. Avoid VIN2 input capacitor
if possible.
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. High performance tantalum or
electrolytic capacitors can be used for the output capacitor.
Low ESR is important, so choose one that is intended for
use in switching regulators. Table 3 lists several capacitor
vendors.
Table 3. Capacitor Vendors
PART SERIES VENDOR
Ceramic, Polymer, Tantalum Panasonic
www.panasonic.com
Ceramic, Tantalum Kemet
www.kemet.com
Ceramic, Polymer, Tantalum Sanyo
www.sanyovideo.com
Ceramic Murata
www.murata.com
Ceramic, Tantalum AVX
www.avxcorp.com
Ceramic Taiyo Yuden
www.taiyo-yuden.com
Catch Diode
The high voltage channel requires an external catch diode
to conduct current during switch off-time. Average forward
current in normal operation can be calculated from:
II V V
V
D AVG OUT IN OUT
IN
( )
( )
=−
where IOUT is the output load current. Use a 1A or 2A
rated Schottky diode. Peak reverse voltage is equal to the
regulator input voltage. Use a diode with a reverse voltage
rating greater than the input voltage. Table 4 lists several
Schottky diodes and their manufacturers.
Table 4. Diode Vendors
PART NUMBER
VR
(V)
IAVE
(A)
VF AT 1A
(MV)
VF AT 2A
(MV)
On Semiconductor
MBRM120E
MBRM140
20
40
1
1
530 595
Diodes Inc.
B120
B130
B220
B230
DFLS240L
20
30
20
30
40
1
1
2
2
2
500
500
500
500
500
International Rectifier
10BQ030
20BQ030
30
30
1
2
420 470
470
applicaTions inForMaTion
LT3640
16
3640f
BST and SW Pin Considerations
The high voltage channel requires an external capacitor
between the BST and SW pins and an external boost diode
from a voltage source to the BST pin. In most cases, a
0.22µF capacitor will work well. The (BST-SW) voltage
cannot exceed 5.5V, and must be more than 2.3V for best
efficiency. Connect the boost diode to any voltage between
2.7V and 5.5V. The VIN2 pin is the best choice if the low
voltage channel is used.
The high voltage channel will not start until the (BST-SW)
voltage is 2V or above. When the LT3640 is enabled, an
internal ~5mA current source from VIN flows out of the BST
pin. The SW pin is disconnected from the SW1 pin, and is
pulled down by an internal current source to ground. The
external boost capacitor can be charged up regardless of
the output. When the (BST-SW) voltage reaches 2V, the SW
pin is connected to the SW1 pin, and the high voltage chan-
nel starts switching. However, the internal bipolar power
switch cannot be fully saturated until the (BST-SW) voltage
is further charged to above 2.3V. To start up a traditional
nonsynchronous buck regulator with very light load, the
input voltage needs to be a couple of volts higher than
the minimum running input voltage if the input voltage is
ramping up slowly. The LT3640’s unique boost capacitor
charging scheme solves this start-up issue. Figure 3 shows
that the minimum input voltage to start the high voltage
channel nonsynchronous buck regulator of the LT3640 is
very close to the minimum input voltage to regulate the
output voltage for most of the load range.
Soft-Start
The LT3640 has a soft-start pin for each channel. The
feedback pin voltage is regulated to the lower of the cor-
responding SS pin and the internal references, which is
1.265V for the high voltage channel, and 600mV for the low
voltage channel. A capacitor from the SS pin to ground is
charged by an internal 2µA current source resulting in an
output ramping linearly from 0V to the regulated voltage.
The duration of the ramp is:
t C V
µA
t C mV
µA
SS SS
SS SS
1 1
2 2
1 265
2
600
2
=
=
•.
•
where tSS1 is the ramping time for the SS1 pin, tSS2 is
the ramping time for the SS2 pin, CSS1 is the capacitance
from the SS1 pin to ground, and CSS2 is the capacitance
from the SS2 pin to ground.
At power-up, a latch is set to discharge the SS1 pin.
After the SS1 pin is discharged to below 100mV, the latch
is reset. The internal 2µA current source starts to charge
the SS1 pin when the (BST-SW) voltage is charged to
above 2V.
Figure 3. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V
applicaTions inForMaTion
(3a) FS = 2MHz (3b) FS = 500kHz
VOUT CURRENT (A)
0.001
4
VIN VOLTAGE (V)
0.01 0.1 1
3
2
1
0
5
3640 F03a
START
RUN
VOUT CURRENT (A)
0.001
4
VIN VOLTAGE (V)
0.01 0.1 1
3
2
1
0
5
3640 F03b
START
RUN
LT3640
17
3640f
In the event of VIN undervoltage lockout, VIN overvoltage
lockout or the EN/UVLO pin being driven below 1.26V, the
soft-start latch is set, triggering a start-up sequence.
A latch is set to discharge the SS2 pin at power-up. After
the FB1 pin reaches 1.165V, the VIN2 voltage is above 2.3V,
the EN2 pin is enabled, and the SS2 pin is below 100mV,
the latch is reset. The internal 2µA current source starts
to charge the SS2 pin.
In the event of VFB1 out of regulation, the VIN2 pin falling
below 2.2V, or the EN pin going low, the SS2 discharging
latch is set, triggering a start-up sequence.
The SS pins can also be pulled up by external current
sources or resistors for output tracking. The external pull-
up current should not exceed 100µA for either SS pin.
Figure 4 shows the soft-start for a 3.3V and 1.8V
application.
Shorted-Output Protection
If an inductor is chosen that will not saturate excessively,
the LT3640 will tolerate a shorted output. For the high
voltage channel, the DA current comparator extends the
internal oscillator period until the catch diode current is
below its limit. Both the top switch and the DA comparator
have current foldback to help limit load current when the
output is shorted to ground. The DA current limit is 1.7A
when the FB1 voltage is above 0.2V, and is 1A when the
FB1 voltage is below 0.2V. Figure 5 shows the high voltage
channel operation under shorted output.
Because of the low VIN2 voltage, the low voltage channel
does not have current foldback. The low voltage channel
does not extend the internal oscillator in shorted output
condition allowing the high voltage channel to operate
in constant frequency. If the bottom MOSFET current
exceeds the NMOS current limit at the start of a clock
cycle, the top MOSFET is kept off in this cycle (similar to
pulse-skipping operation). The inductor valley current is
kept below the NMOS current limit to ensure robustness
in shorted output condition (Figure 6).
Figure 4. Soft-Start of LT3640
Figure 5. The High Voltage Channel Reduces Frequency
to Protect Against Shorted Output With 30V Input
Figure 6. The Low Voltage Channel Operates in
Pulse-Skipping Mode to Protect Against Shorted Output
applicaTions inForMaTion
500µs/DIV
VOUT2
1V/DIV
PGOOD
2V/DIV
VOUT1
2V/DIV
EN
2V/DIV
3640 F04
VIN = 12V
RTSET = 2MHz
1µs/DIV
SW1
10V/DIV
IL1
0.5A/DIV
3640 F05
VIN = 30V
VOUT1 = SHORT
1µs/DIV
SW2
2V/DIV
IL2
1A/DIV
3640 F06
VIN2 = 5V
VOUT2 = SHORT
LT3640
18
3640f
The threshold of power-on comparator is 1.15V for the high
voltage channel, and 550mV for the low voltage channel.
Both RST1 and RST2 are open-drain outputs with weak
internal pull-ups (100k to ~2V). The DC characteristics of
the RST1 and RST2 pull-down strength are shown in the
Typical Performance Characteristics section. The weak
Reverse Protection
In battery charging applications or in battery back-up
systems, the output will be held high when the input to the
LT3640 is absent. If the VIN pin is floated and the LT3640 is
enabled, the LT3640’s internal circuitry will pull its quiescent
current through the SW1 pin or the SW2 pin. This is fine if
the system can tolerate a few mA in this state. If the LT3640
is disabled, the SW1 pin and the SW2 pin current will drop
to essentially zero. However, if the VIN pin is grounded while
the high voltage channel output is held high, an external
diode is required at the VIN pin to prevent current being
pulled out of the VIN pin. If the VIN2 pin is grounded while
the low voltage channel output is held high, an external
diode is required at the VIN2 pin to prevent current being
pulled out of the VIN2 pin (Figure 7).
Figure 8. PFM Operation
PFM Operation
To improve efficiency at light loads, the LT3640 auto-
matically switches to pulse frequency modulation (PFM)
operation which minimizes the switching loss and keeps
the output voltage ripples small.
Because the two channels of the LT3640 may have differ-
ent loads, the two channels can have different switching
frequency (Figure 8).
Power-On Reset Timer
Each channel of the LT3640 has a power-on comparator. Both
comparators are enabled when the LT3640 is powered up
and starts monitoring their corresponding feedback voltages.
Figure 7. Diodes Prevent Shorted Inputs from
Discharging a Battery Tied to the Outputs
applicaTions inForMaTion
3640 F07
OUT2
OUT1
GND
FB2
SW2
SW1
EN/UVLO
VIN
IN SW
LT3640
BST
VIN2
FB1
DA
+
–
+
–
IN2
500ns/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3640 F08a
VIN = 12V
VOUT1 = 3.3V/25mA
VIN2 = VOUT1
VOUT2 = 1.8V/30mA
2µs/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3640 F08b
VIN = 12V
VOUT1 = 3.3V/25mA
VIN2 = VOUT1
VOUT2 = 1.8V/20mA
2µs/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3640 F08c
VIN = 12V
VOUT1 = 3.3V/0mA
VIN2 = VOUT1
VOUT2 = 1.8V/30mA
(8a)
(8b)
(8c)
LT3640
19
3640f
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, tRST (64 cycles on the
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, CPOR, between
the CPOR pin and ground:
t C s
F
RST POR
=
• •37 106
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of tRST will be
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
pin, such as probe capacitance, can affect tRST
.
Watchdog
The WDE pin is the enable pin for the watchdog. As soon
as both RST1 and RST2 are released, the watchdog starts
a delay period, tDLY, during which the input signal at the
WDI pin is ignored for higher reliability. After the delay
period, the watchdog starts detecting falling edges on the
WDI pin. If the time between any two WDI falling edges is
shorter than the watchdog lower boundary, tWDL, or longer
than the watchdog upper boundary, tWDU, the WDO pin
is pulled down for a period of tRST
, which is the same as
the power-on reset timeout period. When the WDO pin is
released, the watchdog again starts the delay period.
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
related and set by a capacitor, CWDT, between the CWDT
pin and ground:
t t
tt
t C
DLY WDU
WDL WDU
WDU WDT
=
=
=
•
•
33
64
16
37 •• 106s
F
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
CWDT. Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
Figure 9. Power-On Reset and Watchdog Timing
applicaTions inForMaTion
(9a)
(9b)
(9c)
20ms/DIV
CPOR
CWDT
FB1
FB2
RST2
RST1
3640 F09a
64 CYCLES 64 CYCLES
WD STARTS
1ms/DIV
CPOR
CWDT
WDI
WDO
3640 F09b
50ms/DIV
CPOR
CWDT
WDI
WDO
3640 F09c
LT3640
20
3640f
3640 F10
L2
L1
CIN2
CIN
CBST
COUT1
COUT2
Figure 9a shows the power-on reset timing. Having FB1
or FB2 high starts the CPOR oscillator. After tRST
, the cor-
responding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 9b shows
the watchdog waveform with the WDI period between tWDL
and tWDU. The WDI falling edge resets the CWDT oscillator.
The CPOR oscillator is disabled and WDO remains high.
Figure 9c shows the watchdog waveform with the WDI
period longer than tWDU. WDO is asserted for a period of
tRST when the watchdog upper boundary, tWDU, expires.
PCB Layout
For proper operation and minimum EMI, care must be
taken during the printed circuit board (PCB) layout. Figure
10 shows the recommended component placement with
trace, ground plane and via locations. The input loop of
the high voltage channel, which is formed by the VIN
and SW1 pins, the external catch diode (D1), the input
capacitor (CIN) and the ground, should be as small as
possible. These external components should be placed
on the same side of the circuit board as the LT3640, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
The boost capacitor (CBST) should be as close to the BST
and SW pins as possible.
The input loop of the low voltage channel is formed by
the VIN2 pin, the input capacitor (CIN2) and the ground.
Place CIN2 close to the VIN2 and the GND pin to minimize
this loop. Place a local, unbroken ground plane below
this input loop.
Keep the FB1 and FB2 nodes small so that the ground
traces will shield them from the switching nodes. The
Exposed Pad on the bottom of the package must be sol-
dered to the ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3640 to additional ground planes within the circuit
board and on the bottom side.
Figure 10. Recommended PCB Layout, FE28 Package
applicaTions inForMaTion
LT3640
21
3640f
3640 TA03
SYNC
D1
WDIWDI
WDE
PGOOD
1nF
1nF
1.5nF
1.5nF 32.4k
VOUT2
1.2V/1A
VOUT1
5V/0.8A
22µF
4.7µF
RST1
RST2
EN2
WDO
FB2
CWDT CPOR RT GND SS2 SS1
SW2
SW1EN/UVLO VIN
VIN
7V TO 35V
SW
LT3640
BST
VIN2
FB1
L2
0.47µH
453k
100k
100k
OUT1
49.9k
49.9k
301k
100k
L1
4.7µH
0.22µF D2
DA
22µF
100k
100k
100k
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
D2: CENTRAL SEMI CMDSH-4E
Typical applicaTions
2MHz 3.3V/1.3A and 1.8V/1A Buck Regulators
2MHz 5V/0.8A and 1.2V/1A Buck Regulators
3640 TA02
SYNC
D1
WDE
PGOOD
1nF
1nF
1.5nF
1.5nF 32.4k
VOUT2
1.8V/1.1A
VOUT1
3.3V/1.3A
VIN2
2.5V TO 5.5V
22µF
4.7µF
RST1
RST2
EN2
WDO
WDI
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
D2: CENTRAL SEMI CMDSH-4E
FB2
CWDT CPOR RT GND SS2 SS1
SW2
SW1EN/UVLO VIN
VIN
5V TO 35V
SW
LT3640
BST
VIN2
FB1
L2
1µH
301k
100k
49.9k
100k
80.6k
49.9k
L1
3.3µH
D2
0.22µF
DA
4.7µF
22µF
3640 TA04
SYNC
WDE
PGOOD
1nF
1nF
1.5nF
1.5nF
22µF
4.7µF
RST1
RST2
WDO
WDI
FB2
CWDT CPOR RT GND SS2 SS1
SW2
SW1EN/UVLO VIN SW
LT3640
BST
VIN2
FB1
68.1k
49.9k
0.22µF
DA
22µF
EN2
D1
32.4k
VOUT2
0.6V/1A
VOUT1
3V/0.8A
VIN
4V TO 30V
L2
0.47µH
L1
3.3µH
D2
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: ON SEMI MBRS230
D2: CENTRAL SEMI CMDSH2-3
2MHz 2.5V/0.8A and 0.6V/1A Buck Regulators
LT3640
22
3640f
package DescripTion
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
FE28 (EB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 2726 25 24 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LT3640
23
3640f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4.00 ± 0.10
(2 SIDES)
2.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
package DescripTion
LT3640
24
3640f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0510 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators
3640 TA05
SYNC
WDE
PGOOD
1nF
1nF
1.5nF
1.5nF 32.4k
VOUT2
0.8V/1.2A
VOUT1
3.3V/0.8A
22µF
RST1
RST2
WDO
WDI FB2
CWDT CPOR RT GND SS2 SS1
SW2
SW1EN/UVLO VIN SW
LT3640
BST
VIN2
FB1
0.47µH
49.9k
16.5k
80.6k
49.9k
3.3µH
0.22µF
DA
22µF
4.7µF
VIN
4V TO 35V
EN2
PART NUMBER DESCRIPTION COMMENTS
LT3689 36V, 60V Transient Protection, 800mA, 2.2MHz High Efficiency
MicroPower Step-Down DC/DC Converter with POR Reset and
Watchdog Timer
VIN: 3.6V to 36V, Transient to 60V, VOUT(MIN) = 0.8V, IQ = 75µA,
ISD < 1µA, 3mm × 3mm QFN-16 Package
LT3686 37V, 55VMAX, 1.2A, 2.5MHz High Efficiency Step-Down DC/DC
Converter
VIN: 3.6V to 37V, Transient to 55V, VOUT(MIN) = 1.21V, IQ = 1.1mA,
ISD < 1µA, 3mm × 3mm DFN-10 Package
LT3682 36V, 60VMAX, 1A, 2.2MHz High Efficiency Micropower
Step-Down DC/DC Converter
VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75µA, ISD < 1µA, 3mm × 3mm
DFN-12 Package
LT3971 38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8µA of Quiescent Current
VIN: 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, 3mm × 3mm
DFN-10, MSOP-10E Packages
LT3991 55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8µA of Quiescent Current
VIN: 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, 3mm × 3mm
DFN-10, MSOP-10E Packages