Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: 719-528-2300 Fax: 719-528-2370 W eb Site: http://www .spt.com e-mail: sales@spt.com
SPT9689
DUAL ULTRAFAST VOLTAGE COMPARATOR
TECHNICAL DATA
FEBRUARY 20, 2001
FEATURES
• 650 ps propagation delay
• 100 ps propagation delay v ariation
• 70 dB CMRR
• Low feedthrough and crosstalk
• Differential latch control
• ECL compatible
APPLICATIONS
• Automated test equipment
• High-speed instrumentation
• Window comparators
• High-speed timing
• Line receivers
• High-speed triggers
• Threshold detection
• Peak detection
GENERAL DESCRIPTION
The SPT9689 is a
Sub
nanosecond monolithic dual com-
parator. The propagation delay variation is less than
100 ps from 5 to 50 mV input overdrive voltage. The input
slew rate is 10 V/ns. The device utilizes a high precision
differential input stage with a common-mode range of
–2.5 V to +4.0 V.
ECL-compatible complementary digital outputs are ca-
pable of driving 50 Ω terminated transmission lines and
providing 30 mA output drive. The SPT9689 is pin compat-
ible with the SPT9687. It is a v ailable in 20-lead PLCC and
20-contact LCC packages o ver the industrial temperature
range. The SPT9689 is also available in die form.
BLOCK DIAGRAM
A
+
INVERTING
INPUT
GNDA
LATCH ENABLE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
INVERTING
INPUT
NONINVERTING
INPUT
GNDB
LATCH ENABLE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
NONINVERTING
INPUT
+
B
VEE
VCC
SPT
22/20/01
SPT9689
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE =–5.20 V, RL = 50 Ohm to –2 V, unless otherwise specified.
TEST TEST SPT9689A SPT9689B
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
DC CHARACTERISTICS
Input Offset Voltage VIN, CM=0, RS=0 Ohms1I–10 ±3.0 10 –25 ±12 25 mV
Input Offset Voltage VIN, CM=0, RS=0 Ohms1
TMIN<TA<TMAX IV –15 ±4.5 15 –30 ±15 30 mV
Offset Voltage Tempco V 10 40 µV/°C
Input Bias Current I ±8 ±25 ±8 ±25 µA
Input Bias Current TMIN<TA<TMAX IV ±12 ±38 ±12 ±38 µA
Input Offset Current I ±1.0 ±3.0 ±2.0 ±5.0 µA
Input Offset Current TMIN<TA<TMAX IV ±2.0 ±5.0 ±4.0 ±7.0 µA
Positive Supply Current Dual I 1 8 30 1 8 35 m A
Negative Supply Current Dual I 40 55 40 60 mA
Positive Supply Voltage, VCC IV 4.75 5.0 5.25 4.75 5.0 5.25 V
Negative Supply Voltage, VEE IV –4.95 –5.2 –5.45 –4.95 –5.2 –5.45 V
Input Common Mode Range V –2.5 +4.0 –2.5 +4.0 V
Latch Enable
Common Mode Range IV –2.0 0 –2.0 0 V
Open Loop Gain V 66 66 dB
Differential Input Resistance V 500 500 kΩ
Input Capacitance V 0.6 0.6 pF
Power Supply Sensitivity V 70 70 dB
Common Mode Rejection Ratio VCM=–2.5 to +4.0 V 70 70 dB
Power Dissipation Dual, Without Load I 350 425 350 475 m W
Power Dissipation Dual, With Load I 400 550 400 550 m W
Output High Level ECL 50 Ohms to –2 V I –1.00 –.81 –1.00 –.81 V
Output Low Level ECL 50 Ohms to –2 V I –1.95 –1.54 –1.95 –1.54 V
AC CHARACTERISTICS
Propagation Delay 20 mV O.D. IV 650 850 750 950 p s
Latch Set-up Time V 150 300 150 300 ps
Latch to Output Delay 250 mV O.D. V 500 600 500 600 ps
Latch Pulse Width V 500 500 p s
Latch Hold Time V 0 0 ps
Rise Time 20% to 80% V 180 18 0 ps
Fall Time 20% to 80% V 80 80 ps
Slew Rate V 10 10 V/ns
Bandwidth –3 dB V 900 900 MHz
1RS = Source impedance
Supply Voltages
Positive Supply Voltage (VCC to GND)....–0.5 to +6.0 V
Negative Supply Voltage (VEE to GND) . .–6.0 to +0.5 V
Ground Voltage Differential ....................–0.5 to +0.5 V
Input Voltages
Input Common Mode Voltage .................–4.0 to +5.0 V
Differential Input Voltage ........................–3.0 to +3.0 V
Input Voltage, Latch Controls ....................VEE to 0.5 V
Output
Output Current ...................................................30 mA
Temperature
Operating Temperature, ambient............ –40 to +85 °C
junction ..................... +150 °C
Lead Temperature, (soldering 60 seconds) ..... +300 °C
Storage Temperature............................ –65 to +150 °C
SPT
32/20/01
SPT9689
VIN+=100 mV (p-p), VOD=20 mV
VREF ± VOS
50%
50%
50%
t
t
tpL
t
t
Differential
Input Voltage
Output Q
Output Q
tS
t
H
pdL
pdH pLOL
pLOH
Latch Enable
Latch Enable
VOD
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL TEST PROCEDURE
I 100% production tested at the specified temperature.
I I 100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
II I QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V Parameter is a typical value for info rmation pur poses only.
VI 100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
TIMING INFORMATION
The timing diagram for the comparator is shown in figure
1. If LE is high and LE low in the SPT9689, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
e xisting logic states.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q). The input signal must
be maintained f or a time tS (set-up time) before the LE f all-
ing edge and LE rising edge and held for time tH after the
falling edge f or the comparator to accept data. After tH, the
output ignores the input status until the latch is strobed
again. A minimum latch pulse width of tpL is needed for
strobe operation, and the output transitions occur after a
time of tpLOH or tpLOL.
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before tS will be detected and held;
those occurring after tH will not be detected. Changes
between tS and tH may not be detected.
Figure 1 – Timing Diagram
SPT
42/20/01
SPT9689
SWITCHING TERMS (Refer to figure 1)
tpdH INPUT TO OUTPUT HIGH DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition
tpdL INPUT TO OUTPUT LOW DELAY – the propagation
delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition
tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition
VOD VOLTAGE OVERDRIVE – the difference between
the differential input and reference input voltages
tpLOL LATCH ENABLE TO OUTPUT LOW DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
tHMINIMUM HOLD TIME – the minimum time after the
negative transition of the Latch Enable signal that
the input signal must remain unchanged in order to
be acquired and held at the outputs
tpL MINIMUM LATCH ENABLE PULSE WIDTH – the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
tSMINIMUM SET-UP TIME – the minimum time bef ore
the negative transition of the Latch Enable signal
that an input signal change must be present in order
to be acquired and held at the outputs
GENERAL INFORMATION
The SPT9689 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.
The SPT9689 has a complementar y latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
The negative common mode voltage is –2.5 V. The posi-
tive common mode voltage is +4.0 V.
The dual comparators share the same VCC and VEE con-
nections but have separate grounds for each comparator
to achiev e high crosstalk rejection.
ECL
OUT
Q
Q
REF
1
REF
2
PRE
AMP
+
V
IN
CLK
BUF
LATCH
V
IN
V
EE
GND
LE LE
V
CC
Figure 2 – Internal Function Diagram
SPT
52/20/01
SPT9689
TYPICAL PERFORMANCE CHARACTERISTICS
020406080 100
OVERDRIVE (mV)
500
PROPAGATION DELAY TIME (ps)
PROPAGATION DELAY VS OVERDRIVE VOLTAGE
550
600
650
700
750
800
-50 0 +50 +100
120
160
200
240
RISE TIME VS TEMPERATURE
TEMPERATURE (°C)
80
RISE TIME (ps)
280
+150
HYSTERESIS VS
D
LATCH
1
HYSTERESIS (mV)
0
DLATCH = VLE VLE (mV)
3
5
7
9
11
10 20 30 40 50
400 500 600 700 800
1.50
1.30
1.10
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
TIME (ps)
1.90
OUTPUT RISE AND FALL (V)
1.70
.90
900
100
140
180
220
60
260
50 0 +50 +100 +150
FALL TIME VS TEMPERATURE
TEMPERATURE (°C)
FALL TME (ps)
3.0
8
12
16
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
COMMON MODE VOLTAGE (V)
0
INPUT BIAS CURRENT (µA)
4
20
2.0 1.0 0.0 +2.0 +3.0 +4.0 +5.0+1.0
T=-55 °C
T=+25 °C
T=+125 °C
SPT
62/20/01
SPT9689
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the compar ator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be noted to achiev e optimal perf ormance. The very
high operating speeds of the comparator require careful
la yout, decoupling of supplies, and proper design of tr ans-
mission lines.
Since the SPT9689 comparator is a ver y high-frequency
and high-gain device, certain layout rules must be fol-
lowed to avoid oscillations. The comparator should be
soldered to the board with component lead lengths kept
as short as possib le. A ground plane should be used while
the input impedance to the part is k ept as lo w as possible
to decrease parasitic feedback. If the output board traces
are longer than approximately half an inch, microstripline
techniques must be employed to prevent ringing on the
output waveform . Also, the microstriplines must be ter mi-
nated at the far end with the characteristic impedance of
the line to prevent reflections. Both supply voltage pins
should be decoupled with high-frequency capacitors as
close to the device as possible. All ground pins and no
connects should be soldered to a common ground plane
to further improve noise immunity. If using the SPT9689
as a single comparator, the outputs of the inactive com-
parator can be grounded, left open, or terminated with
50 ohms to –2 V. All outputs on the active comparator,
whether used or unused, should have identical termina-
tions to minimize ground current switching transients.
Figure 3 – SPT9689 Typical Interface Circuit Figure 4 – SPT9689 Typical Interface Circuit
with Hysteresis
V
IN
+5.0 V
10 µF
0.1 µF
100 pF
10 µF
0.1 µF
100 pF
5.2 V 2 V
R
L
R
L
10 F
+V
CC
LE
LE
V
EE
GND
+
Q Output
Q Output
V
REF
100 pF
10 µF
0.1 µF 50
W
50
W
ECL
NOTES:
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
0.1 µF and 100 pF capacitors are chip type mounted as close
to the pins as possible.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
100 pF
V
IN
+5.0 V
10 µF
0.1 µF
100 pF
10 µF0.1 µF
10 µF
0.1 µF
100 pF
5.2 V 2 V
10 µF
2 V
1.3 V
+V
CC
LE
LE
V
EE
GND
+
100 W
0 to 200 W
V
REF
50 W
NOTES:
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
0.1 µF and 100 pF capacitors are chip type mounted
as close to the pins as possible.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
Q Output
Q Output
R
L
50 W
R
L
SPT
72/20/01
SPT9689
PACKA GE OUTLINES
20-Contact Leadless Chip Carrier (LCC)
C
D
F
A
BPin 1
Bottom
View
G
H
E
A
B
E
Pin 1
G
L
M
N
H
IJK
O
C
D
F
TOP
VIEW
Pin 1
BOTTOM
VIEW
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A .040 typ 1.02 typ
B .050 typ 1.27 typ
C 0.045 0.055 1.14 1.40
D 0.345 0.360 8.76 9.14
E 0.054 0.066 1.37 1.68
F .020 typ 0.51 typ
G 0.022 0.028 0.56 0.71
H 0.075 1.91
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A .045 typ 1.14 typ
B .045 typ 1.14 typ
C 0.350 0.356 8.89 9.04
D 0.385 0.395 9.78 10.03
E 0.350 0.356 8.89 9.04
F 0.385 0.395 9.78 10.03
G 0.042 0.056 1.07 1.42
H 0.165 0.180 4.19 4.57
I 0.085 0.110 2.16 2.79
J 0.025 0.040 0.64 1.02
K 0.015 0.025 0.38 0.64
L 0.026 0.032 0.66 0.81
M 0.013 0.021 0.33 0.53
N 0.050 1.27
O 0.290 0.330 7.37 8.38
20-Lead Plastic Leadless Chip Carrier (PLCC)
SPT
82/20/01
SPT9689
ORDERING INFORMATION
PART INPUT TEMPERATURE PACKAGE
NUMBER OFFSET RANGE TYPE
SPT9689AIC 10 mV –40 to +85 °C 20C LCC
SPT9689BIC 25 mV –40 to +85 °C 20C LCC
SPT9689AIP 10 mV –40 to +85 °C 20L PLCC
SPT9689BIP 25 mV –40 to +85 °C 20L PLCC
SPT9689ACU +25 °CDie*
SPT9689BCU +25 °CDie*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without
the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails,
can be reasonably expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
PIN ASSIGNMENTS PIN FUNCTIONS
NAME FUNCTION
QAOutput A
QAInverted Output A
GNDAGround A
LEALatch Enable A
LEAInverted Latch Enable A
VEE Negative Supply Voltage
–INAInverting Input A
+INANoninverting Input A
+INBNoninverting Input B
–INBInverting Input B
VCC Positive Supply Voltage
LEBLatch Enabled B
LEBInverted Latch Enable B
GNDBGround B
QBOutput B
QBInverted Output B
QA
INA+INA
QB
GNDB
LEB
VCC
INB
+INB
4
5
6
7
8
18
17
16
15
14
9 10111213
3 2 1 20 19
N/C
GNDA
LEA
LEA
VEE
N/C N/C
N/C
QAQB
LEB
TOP VIEW
LCC/PLCC
