VBAT
RESET
MR
PFO
8
7
6
5
1
2
3
4
VOUT
VDD
GND
PFI
DGK PACKAGE
(TOP VIEW)
ACTUAL SIZE
3,05 mm x 4,98 mm
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION
Check for Samples: TPS3619-33-EP,TPS3619-50-EP,TPS3620-33-EP,TPS3620-50-EP
1FEATURES APPLICATIONS
• Fax Machines
• Supply Current of 40 mA (Max) • Set-Top Boxes
• Battery-Supply Current of 100 nA (Max) • Advanced Voice-Mail Systems
• Precision Supply-Voltage Monitor 3.3 V, 5 V, • Portable Battery-Powered Equipment
and Other Options on Request • Computer Equipment
• Backup-Battery Voltage Can Exceed VDD • Advanced Modems
• Power-On Reset Generator with Fixed 100-ms • Automotive Systems
Reset Delay Time • Portable Long-Time Monitoring Equipment
• Voltage Monitor for Power-Fail or Low-Battery • Point-of-Sale Equipment
Monitoring
• Battery Freshness Seal (TPS3619) DESCRIPTION
• Pin-to-Pin Compatible With MAX819, MAX703, The TPS3619 and TPS3620 families of supervisory
and MAX704 circuits monitor and control processor activity by
• 8-Pin Mini Small-Outline Package (MSOP) providing backup-battery switchover for data retention
Package of CMOS RAM.
During power on, RESET is asserted when the
SUPPORTS DEFENSE, AEROSPACE, supply voltage (VDD or VBAT) becomes higher than 1.1
AND MEDICAL APPLICATIONS V. Thereafter, the supply voltage supervisor monitors
• Controlled Baseline VDD and keeps RESET output active as long as VDD
• One Assembly/Test Site remains below the threshold voltage (VIT). An internal
• One Fabrication Site timer delays the return of the output to the inactive
state (high) to ensure proper system reset. The delay
• Available in Military (–55°C/125°C) time starts after VDD has risen above VIT. When the
Temperature Range(1) supply voltage drops below VIT, the output becomes
• Extended Product Life Cycle active (low) again.
• Extended Product-Change Notification The product spectrum is designed for supply voltages
• Product Traceability of 3.3 V and 5 V. The TPS3619 and TPS3620 are
available in an 8-pin MSOP package and are
characterized for operation over a temperature range
(1) Additional temperature ranges available - contact factory of –55°C to 125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VDD VBAT
PFI
Backup
Battery
RESET
PFO
VOUT
GND
Rx
Ry
External
Source
0.1 µF
Power
Supply
GND
RESET
I/O
VCC
Switchover
Capacitor
0.1 µF
TPS3619
TPS3620 Microcontroller
or
Microprocessor
Manual
Reset
MR
Reel
Nominal Supply Voltage
Package
Functionality
Family
DGK EP
R
Temperature Range
Designator
TPS361 9 33 M
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL OPERATING CIRCUIT
PACKAGE INFORMATION(1)
PACKAGE TRANSPORT MEDIA,
TAPRODUCT ORDERABLE PART NUMBER
MARKING QUANTITY
TPS3619-33MDGKEP(2) Tube, 80
TPS3619-33 BZP TPS3619-33MDGKREP Tape and reel, 2500
TPS3619-50MDGK(2) Tube, 80
TPS3619-50 TBD TPS3619-50MDGKREP(2) Tape and reel, 2500
–55°C to 125°C TPS3620-33MDGKTEP Tape and reel, 250
TPS3620-33 BTY TPS3620-33MDGKREP Tape and reel, 2500
TPS3620-50MDGKTEP(2) Tape and reel, 250
TPS3620-50 TBD TPS3620-50MDGKREP(2) Tape and reel, 2500
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
see the TI web site at www.ti.com.
(2) Product Preview. Parameters in electrical characteristics are subject to change.
Standard and Application-Specific Versions
DEVICE NAME NOMINAL VOLTAGE(1), VNOM
TPS3619-33 DGK 3.3 V
TPS3619-50 DGK 5 V
TPS3620-33 DGK 3.3 V
TPS3620-50 DGK 5 V
(1) For other threshold voltage versions, contact the local TI sales
office for availability and lead time.
2Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
UNIT
VDD (2) 7 V
Supply voltage MR and PFI pins(2) –0.3 V to (VDD + 0.3 V)
VOUT 400 mA
Continuous output current, IOAll other pins(2) ±10 mA
Continuous total power dissipation See Dissipation Ratings Table
Operating free-air temperature range, TA–55°C to 125°C
Storage temperature range, Tstg –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 in) from case for 10 s 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than
t = 1000 h.
Dissipation Ratings TA< 25°C DERATING FACTOR TA= 70°C TA= 85°C TA= 125°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
DGK 470 mW 3.76 mW/°C 301 mW 241 mW 93.98 mW
Recommended Operating Conditions
at specified temperature range MIN MAX UNIT
VDD Supply voltage 1.65 5.5 V
VBAT Battery supply voltage 1.5 5.5 V
VIInput voltage 0 VDD + 0.3 V
VIH High-level input voltage 0.7 × VDD V
VIL Low-level input voltage 0.3 × VDD V
IOContinuous output current at VOUT 300 mA
Input transition rise and fall rate at MR 100 ns/V
Δt/ΔV Slew rate at VDD or VBAT 1 V/ms
TAOperating free-air temperature –55 125 °C
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 3.3 V, IOH = –2 mA VDD – 0.4
RESET VDD = 5 V, IOH = –3 mA VDD – 0.4
VOH High-level output voltage VDD = 1.8 V, IOH = –20 mA VDD – 0.3 V
PFO VDD = 3.3 V, IOH = –80 mA VDD – 0.4
VDD = 5 V, IOH = –120 mA VDD – 0.4
VDD = 1.8 V, IOL = –400 mA 0.2
VOL Low-level output voltage RESET, PFO VDD = 3.3 V, IOL = 2 mA 0.4 V
VDD = 5 V, IOL = 3 mA 0.4
IOL = 20 mA, VBAT > 1.1 V or
Vres Power-up reset voltage(1) 0.4 V
VDD > 1.1 V
IOUT = 8.5 mA, VBAT = 0 V, VDD – 50
VDD = 1.8 V
IOUT = 125 mA, VBAT = 0 V,
Normal mode VDD – 150
VDD = 3.3 V
VOUT IOUT = 190 mA, VBAT = 0 V, mV
VDD – 200
VDD = 5 V
IOUT = 0.5 mA, VBAT = 1.5 V, VBAT – 50
VDD = 0 V
Battery-backup mode IOUT = 7.5 mA, VBAT = 3.3 V VBAT – 150
VDD to VOUT on resistance VDD = 5 V 0.6 1
rDS(on) Ω
VBAT to VOUT on resistance VDD = 3.3 V 8 20
TPS36XX-33 2.88 2.93 3.05
VIT– TA= –55°C to 125°C V
Negative-going input threshold TPS36XX-50 4.46 4.55 4.64
voltage(2)
VPFI TA= –55°C to 125°C 1.13 1.15 1.185 V
1.65 V < VIT < 2.5 V 20
VIT 2.5 V < VIT < 3.5 V 40
Vhys Hysteresis 3.5 V < VIT < 5.5 V 60 mV
PFI 12
VBSW(3) VDD = 1.8 V 55
IIH High-level input current MR MR = 0.7 × VDD, VDD = 5 V –30 –76 mA
IIL Low-level input current MR MR = 0 V, VDD = 5 V –110 –255 mA
IIInput current PFI –25 25 nA
VDD = 1.8 V –0.3
IOS Short-circuit current PFO PFO = 0 V VDD = 3.3 V –1.1 mA
VDD = 5 V –2.4
VOUT = VDD 40
IDD VDD supply current mA
VOUT = VBAT 40
VOUT = VDD –0.1 0.1
I(BAT) VBAT supply current mA
VOUT = VBAT 0.5
CIInput capacitance VI= 0 V to 5 V 5 pF
(1) The lowest supply voltage at which RESET becomes active. tr,VDD ≥15 ms/V.
(2) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 mF) should be placed near the supply terminals.
(3) For VDD < 1.6 V, VOUT switches to VBAT, regardless of VBAT.
4Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
VIT
VBAT
VDD
VOUT
RESET
td
t
t
t
td
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
Timing Requirements
at RL= 1 MΩ, CL= 50 pF, TA= 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
at VDD VIH = VIT + 0.2 V, VIL = VIT – 0.2 V 6 ms
twPulse width at MR VDD = VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 × VDD 100 ns
Switching Characteristics
at RL= 1 MΩ, CL= 50 pF, TA= –55°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD ≥VIT + 0.2 V, MR ≥0.7 × VDD,
tdDelay time 60 100 140 ms
See timing diagram
VDD to RESET VIL = VIT – 0.4 V, VIH = VIT + 0.4 V 2 5
Propagation (delay) time, PFI to PFO delay VIL = VPFI – 0.35 V, VIH = VPFI + 0.35 V 3 5
tPHL ms
high-to-low-level output VDD ≥VIT + 0.2 V, VIL = 0.3 × VDD,
MR to RESET 0.1 1
VIH = 0.7 × VDD
Timing Diagram
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
Table 1. FUNCTION TABLE
VDD > VIT VDD > VBAT MR VOUT RESET
0 0 L VBAT L
0 0 H VBAT L
0 1 L VDD L
0 1 H VDD L
1 0 L VDD L
1 0 H VDD H
1 1 L VDD L
1 1 H VDD H
PFI > VPFI PFO
0 L
1 H
CONDITION: VDD > VDD(MIN)
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
GND 3 I Ground
MR 6 I Manual reset
PFI 4 I Power-fail comparator input
PFO 5 O Power-fail comparator output
RESET 7 O Active-low reset
VBAT 8 I Backup battery
VDD 2 I Supply input voltage
VOUT 1 O Supply output voltage
6Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
_
+Switch
Control
Reference
Voltage
of 1.15 V
_
+
RESET
Logic
+
Timer
VBAT
VDD
PFI
VOUT
RESET
PFO
MR
_
+
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
500
600
700
800
900
1000
50 75 100 125 150 175 200
TA = 85°C
TA = 25°C
TA = 0°C
TA = −40°C
− Static Drain-Source On-State Resistance − m
VDD = 3.3 V
VBAT = GND
IO − Output Current − mA
rDS(on) Ω
5
10
15
20
2.5 4.5 6.5 8.5 10.5 12.5 14.5
TA = 85°C
TA = 25°C
TA = 0°C
TA = −40°C
− Static Drain-Source On-State Resistance −
IO − Output Current − mA
rDS(on) Ω
VBAT = 3.3 V
7.5
12.5
17.5
0.995
0.996
0.997
0.998
0.999
1
1.001
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
− Normalized Threshold Voltage at RESET − V
VIT
TA − Free-Air Temperature − °C
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT) (VBAT to VOUT)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
SUPPLY CURRENT NORMALIZED THRESHOLD AT RESET
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 3. Figure 4.
8Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
0
1
2
3
4
5
6
−35−30−25−20−15−10−−50
TA = −40°C
TA = 85°C
TA = 0°C
TA = 25°C
IOH − High-Level Output Current − mA
VDD = 5 V
VBAT = GND
VOH – High-Level Output Voltage at RESET – V
4.5
4.6
4.7
4.8
4.9
5
5.1
−5−4.5−4−3.5−3−2.5−2−1.5−1−0.50
TA = −40°C
TA = 25°C
TA = 85°C
TA = 0°C
IOH − High-Level Output Current − mA
VDD = 5 V
VBAT = GND
Expanded View
VOH – High-Level Output Voltage at RESET – V
0
1
2
3
4
5
6
−2.5−2−1.5−1−0.50
TA = −40°C
TA = 25°C
TA = 85°C
TA = 0°C
IOH − High-Level Output Current − mA
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
VOH – High-Level Output Voltage at PFO – V
5.10
5.15
5.20
5.25
5.30
5.35
5.40
5.45
5.50
5.55
−200−180−160−140−120−100−80−60−40−200
TA = −40°C
TA = 25°C
TA = 85°C
TA = 0°C
IOH − High-Level Output Current − µA
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
Expanded View
VOH – High-Level Output Voltage at PFO – V
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE AT RESET HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 5. Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE AT PFO HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25
TA = 25°C
TA = 85°C
TA = 0°C
TA = −40°C
IOL − Low-Level Output Current − mA
VDD = 3.3 V
VBAT = GND
VOL – Low-Level Output Voltage at RESET – V
0
1
2
3
4
5
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Minimum Pulse Duration at − VDD
Threshold Overdrive at VDD − V 1
sµ
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Minimum Pulse Duration at PFI −
Threshold Overdrive at PFI − V
VDD = 1.65 V
sµ
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE AT RESET LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs vs
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 9. Figure 10.
MINIMUM PULSE DURATION AT VDD MINIMUM PULSE DURATION AT PFI
vs vs
THRESHOLD OVERDRIVE AT VDD THRESHOLD OVERDRIVE AT PFI
Figure 11. Figure 12.
10 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
www.ti.com
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
DETAILED DESCRIPTION
Battery Freshness Seal (TPS3619)
The battery freshness seal of the TPS3619 family disconnects the backup battery from internal circuitry until it is
needed. This function prevents the backup battery from being discharged until the final product is put to use. The
following steps explain how to enable the freshness seal mode.
1. Connect VBAT (VBAT > VBAT min)
2. Ground PFO
3. Connect PFI to VDD (PFI = VDD)
4. Connect VDD to power supply (VDD > VIT) and retain for 5 ms < t < 35 ms
The battery freshness seal mode is removed automatically by the positive-going edge of RESET when VDD is
applied.
Power-Fail Input/Output Comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The PFI is
compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold
(VIT(PFI)) of 1.15 V (typ), the PFO goes low. If VIT(PFI) goes above V(PFI) plus about 12-mV hysteresis, the output
returns to high. By connecting two external resistors, it is possible to supervise any voltages above V(PFI). The
sum of both resistors should be about 1 MΩ, to minimize power consumption and also to ensure that the current
in the PFI pin can be ignored, compared with the current through the resistor network. The tolerance of the
external resistors should be not more than 1%, to ensure minimal variation of sensed voltage. If the power-fail
comparator is unused, PFI should be connected to ground and PFO left unconnected.
Backup-Battery Switchover
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In
order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors
do not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ωswitch)
when VDD falls below the VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred, either
until VDD crosses VBAT or until VDD rises above VIT. VOUT connects to VDD through a 1-Ω(max) PMOS switch
when VDD crosses the reset threshold.
Table 2. FUNCTION TABLE
VDD > VBAT VDD > VIT VOUT
1 1 VDD
1 0 VDD
0 1 VDD
0 0 VBAT
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
Undefined
VBSW Hysteresis
VBAT Mode
VDD Mode VIT Hysteresis
– Normal Supply Voltage – VVDD
VBAT – Backup-Battery Supply Voltage – V
TPS3619-33-EP, TPS3619-50-EP
TPS3620-33-EP, TPS3620-50-EP
SGLS350C –JULY 2006–REVISED SEPTEMBER 2010
www.ti.com
Figure 13. Normal Supply Voltage vs Backup-Battery Supply Voltage
12 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3619-33-EP TPS3619-50-EP TPS3620-33-EP TPS3620-50-EP
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS3619-33MDGKREP ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3620-33MDGKREP ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3620-33MDGKTEP ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06670-01XE ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06670-03XE ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF TPS3619-33-EP, TPS3620-33-EP :
•Catalog: TPS3619-33, TPS3620-33
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS3619-33MDGKREP VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS3620-33MDGKREP VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS3620-33MDGKTEP VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS3619-33MDGKREP VSSOP DGK 8 2500 358.0 335.0 35.0
TPS3620-33MDGKREP VSSOP DGK 8 2500 358.0 335.0 35.0
TPS3620-33MDGKTEP VSSOP DGK 8 250 202.0 201.0 28.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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