10-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT
1
FEATURES APPLICATIONS
NominalSize=1inx0.62in
(25,4mmx15,75mm)
DESCRIPTION
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
ADJUST POWER MODULE
•Complex Digital Systems2
•Up to 10-A Output Current•12-V Input Voltage•Wide-Output Voltage Adjust(1.2 V to 5.5 V/(0.8 V to 1.8 V)•Efficiencies up to 95%•225 W/in
3
Power Density•Output Voltage Sense•Margin Up/Down Controls•Undervoltage Lockout•Auto-Track™ Sequencing•Pre-Bias Start-up Capabilityusing On/Off Inhibit•Output Overcurrent Protection(Non-latching, Auto-Reset)•Operating Temperature: – 40 ° C to 85 ° C•Safety Agency Approvals:UL/IEC/CSA C22.2 60950-1•Point-of-Load Alliance ( POLA™) Compatible
The PTH12060 series is a non-isolated power module, and part of a new class of complete dc/dc convertersfrom Texas Instruments. These modules are small in size, and are an alternative for applications requiring up to10 A of load current.
The small footprint, (1 inch × 0.62 inch) and industry leading features makes this module suitable for spaceconscious digital systems that incorporate multiple processors.
This series of modules operate from a 12-V input bus voltage to provide step-down power conversion to a widerange of output voltages. The output voltage of the W-suffix device may be set to any voltage over the adjustrange, 1.2 V to 5.5 V. The L-suffix device has an adjustment range of 0.8 V to 1.8 V. The output voltage is setwithin the adjust range using a single external resistor.
This product includes Auto-Track™ Sequencing. Auto-Track simplifies the task of supply voltage sequencing in apower system, by enabling modules to track each other, or any other external voltage, during power up andpower down.
Other features include an on/off inhibit and margin up/down controls. An output voltage sense ensures tight loadregulation. Non-latching overcurrent trip protects against load faults.
For start-up into a non-prebiased output, review page 14 in the Application Information section.
For start-up into a prebiased output, review page 18 in the Application Information section.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Auto-Track, POLA, TMS320 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
MarginDown
MarginUp
VI
C
560 F
(Required)
I
m
C 1
330 F
(Optional)
O
m
C 2
Ceramic
(Optional)
O
+
+
Inhibit
GND GND
VO
V Sense
O
Track
1
2
10 7
6
54
3
9 8
R ,1%
(Required)
SET
L
O
A
D
ABSOLUTE MAXIMUM RATINGS
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
STANDARD APPLICATION
A. R
SET
= Required to set the output voltage to a value higher than the minimum value. See the Application Informationsection for values.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or seethe TI website at www.ti.com.
voltages are with respect to GND
UNIT
V
I
Input voltage Track – 0.3 V to V
I
+0.3 VOperating temperature – 40 ° C to 85 ° C
(1)T
A
Over V
I
rangerange
PTH12060WAH 260 ° C
(2)Wave solderT
wave
Surface temperature of module body or pins (5 seconds)temperature
PTH12060WAD
PTH12060WAS 235 ° C
(2)Solder reflowT
reflow
Surface temperature of module body or pinstemperature
PTH12060WAZ 260 ° C
(2)
T
stg
Storage temperature – 55 ° C to 125 ° C
(3)
Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 msec, Sine, mounted 500 GMechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20 GWeight 5 gramsFlammability Meets UL 94V-O
(1) For operation below 0 ° C, the external capacitors must have stable characteristics. Use either a low ESR tantalum, Os-Con, or ceramiccapacitor.
(2) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the statedmaximum.
(3) The shipping tray or tape & reel cannot be used to bake parts at temperatures higher than 65 ° C.
2Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
ELECTRICAL CHARACTERISTICS
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
T
A
= 25C; V
I
= 12 V; V
O
= 3.3 V; C
I
= 560 µ F, C
O
= 0 µ F, and I
O
= I
O
max (unless otherwise stated)
PTH12060W UNITPARAMETER TEST CONDITIONS
MIN TYP MAX
T
A
= 60 ° C, 200 LFM airflow 0 10
(1)
AI
O
Output current Over ΔV
adj
range
T
A
= 25 ° C, natural convection 10
(1)
A
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
O tol
Set-point voltage tolerance ± 2
(2)
%V
O
ΔReg
temp
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.5 %V
O
ΔReg
line
Line regulation Over V
in
range ± 10 mV
ΔReg
load
Load regulation Over I
o
range ± 12 mV
ΔReg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤T
A
≤85 ° C ± 3 %V
O
ΔV
adj
Output voltage adjust range Over V
in
range 1.2 5.5 V
R
SET
= 280 Ω, V
O
= 5.0 V 94%
R
SET
= 2.0 k Ω, V
O
= 3.3 V 92%
R
SET
= 4.32 k Ω, V
O
= 2.5 V 90%ηEfficiency I
O
= 8 A
R
SET
= 11.5 k Ω, V
O
= 1.8 V 87%
R
SET
= 24.3 k Ω, V
O
= 1.5 V 85%
R
SET
= open circuit, V
O
= 1.2 V 83%
V
O
≤2.5 V 25
(3)
mV
PP20-MHz bandwidth,V
O
ripple (peak-to-peak)
with C
O
2 = 10 µ F ceramic
V
O
> 2.5 V 1
(3)
%V
O
I
O
trip Overcurrent threshold Reset, followed by auto-recovery 20 A
t
tr
1 A/ µ s load step, 50 to Recovery time 70 µ STransient response 100% I
o
max,
V
o
over/undershoot 100 mVΔV
tr
C
O
1 = 330 µ F
V
O
adj Margin up/down adjust ± 5%
I
IL
margin Margin input current (pins 9/10) Pin to GND – 8
(4)
µA
I
IL
track Track input current (pin 8) Pin to GND – 0.11
(5)
mA
dV
track
/dt Track slew rate capability C
O
≤C
O
(max) 1 V/ms
V
I
increasing 9.5 10.4UVLO Undervoltage lockout VV
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(5)
VV
IL
Inhibit Control (pin 3) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 3 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 300 350 400 kHz
C
I
External input capacitance 560
(6)
µ F
Nonceramic 0 330
(7)
5500
(8)
Capacitance value µ FC
O
External output capacitance Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(9)
mΩ
6.4MTBF Reliability Per Bellcore TR-332, 50% stress, T
A
= 40 ° C, ground benign
10
6
Hr
(1) See SOA curves or consult factory for appropriate derating.(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has atolerance of 1% with 100 ppm/ ° C or better temperature stability.(3) The peak-to-peak output ripple voltage is measured with an external 10- µ F ceramic capacitor. See the standard application schematic.(4) A small, low leakage ( < 100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.(5) This control pin has an internal pull-up to the input voltage V
I
. If it is left open-circuit, the module operates when input power is applied.A small, low-leakage ( < 100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place anexternal pull-up on this pin. For further information, see the related application information section.(6) A 560 µ F input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms ofripple current.(7) An external output capacitor is not required for basic operation. Adding 330 µ F of distributed capacitance at the load improves thetransient response.(8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using avoltage supervisor, C
O
(max) is reduced to 2200 µF. See the application notes for further guidance.(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ωas the minimum when using max-ESR valuesto calculate.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): PTH12060W/L
ELECTRICAL CHARACTERISTICS
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
T
A
= 25C; V
I
= 12 V; V
O
= 1.8 V; C
I
= 560 µ F, C
O
= 0 µ F, and I
O
= I
O
max (unless otherwise stated)
PTH12060L UNITPARAMETER TEST CONDITIONS
MIN TYP MAX
Over ΔV
adj
range 85 ° C, 200 LFM airflow 0 10
(1)
I
O
Output current A25 ° C, natural convention 0 10
(1)
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
O tol
Set-point voltage tolerance ± 2
(2)
%V
O
ΔReg
temp
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.5 %V
O
ΔReg
line
Line regulation Over V
I
range ± 10 mV
ΔReg
load
Load regulation Over I
O
range ± 12 mV
ΔReg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤T
A
≤85 ° C ± 3 %V
O
ΔV
adj
Output voltage adjust range Over V
I
range 0.8 1.8 V
R
SET
= 130 Ω, V
O
= 1.8 V 88%
R
SET
= 3.57 k Ω, V
O
= 1.5 V 87%
ηEfficiency I
O
= 8 A R
SET
= 12.1 k Ω, V
O
= 1.2 V 84%
R
SET
= 32.4 k Ω, V
O
= 1 V 82%
R
SET
= open circuit, V
O
= 0.8 V 81%
V
O
> 1 V 20
(3)20-MHz bandwidth,V
O
ripple (peak-to-peak) mV
PPwith C
O
2 = 10 µ F ceramic
V
O
≤1 V 30
(3)
I
O
trip Overcurrent threshold Reset, followed by auto-recovery 20 A
t
tr
1 A/ µ s load step, 50 to 100% Recovery time 70 µ STransient response I
O
max,
V
O
over/undershoot 100 mVΔV
tr
C
O
1 = 330 µ F
V
O
adj Margin up/dow adjust ± 5%
I
IL
margin Margin input current (pins 9/10) Pin to GND – 8
(4)
µA
I
IL
track Track input current (pin 8) Pin to GND – 0.11
(5)
mA
dV
track
/dt Track slew rate capability C
O
≤C
O
(max) 1 V/ms
V
I
increasing 9.5 10.4UVLO Under-voltage lockout VV
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(5)
VV
IL
Inhibit Control (pin 3) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 3 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 200 250 300 kHz
C
I
External input capacitance 560
(6)
µ F
Nonceramic 0 330
(7)
5500
(8)
Capacitance value µ FC
O
External output capacitance Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(9)
mΩ
Per Bellcore TR-332 6.4MTBF Reliability
10
6
Hr50% stress, T
A
= 40 ° C, ground benign
(1) See SOA curves or consult factory for appropriate derating.(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has atolerance of 1% with 100 ppm/ ° C or better temperature stability.(3) The peak-to-peak output ripple voltage is measured with an external 10- µ F ceramic capacitor. See the standard application schematic.(4) A small, low-leakage ( < 100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.(5) This control pin has an internal pull-up to the input voltage V
I
. If it is left open-circuit, the module operates when input power is applied.A small, low-leakage ( < 100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place anexternal pull-up on this pin. For further information, see the application information section.(6) A 560- µ F input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms ofripple current.(7) An external output capacitor is not required for basic operation. Adding 330 µ F of distributed capacitance at the load improves thetransient response.(8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using avoltage supervisor, C
O
(max) is reduced to 2200 µF. See the application notes for further guidance.(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ωas the minimum when using max-ESR valuesto calculate.
4Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
DEVICE INFORMATION
PTHXX060
(Top View)
1
2
10 9 8 7
6
543
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Terminal Functions
TERMINAL
DESCRIPTIONNAME NO.
V
I
2 The positive input voltage power node to the module, which is referenced to common GND.V
O
6 The regulated positive power output with respect to the GND node.This is the common ground connection for the V
I
and V
O
power connections. It is also the 0 Vdc reference for theGND 1, 7
control inputs.The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low level groundsignal to this input disables the module ’ s output and turns off the output voltage. When the Inhibit control is active,the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open-circuit, the moduleInhibit 3
produces an output whenever a valid input source is applied. Do not place an external pull-up on this pin. Forpower-up into a non-prebiased output, it is recommended that AutoTrack be utilized for On/Off control. See theApplication Information for additional details.A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of the moduleto a value higher than its lowest value. The temperature stability of the resistor should be 100 ppm/ ° C (or better).The set-point range is 1.2 V to 5.5 V for W-suffix devices, and 0.8 V to 1.8 V for L-suffix devices. The resistor valueV
O
Adjust 4
required for a given output voltage may be calculated using a formula. If left open circuit, the output voltage defaultsto its lowest value. For further information on output voltage adjustment, see the application information section.Table 2 gives the preferred resistor values for a number of standard output voltages.The sense input allows the regulation circuit to compensate for voltage drop between the module and the load. ForV
O
Sense 5
optimal voltage accuracy, V
O
Sense should be connected to V
O
. It can also be left disconnected.This is an analog control input that enables the output voltage to follow an external voltage. This pin becomesactive typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage fromzero volts, up to the nominal set-point voltage. Within this range, the output follows the voltage at the Track pin on aTrack 8
volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage.The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus.If unused, this input should be connected to V
I
.Note: Due to the undervoltage lockout feature, the output of the module cannot follow its own input voltage duringpower up. For more information, see the application information section.When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The input requires anMargin Down 9 open-collector (open-drain) interface. It is not TTL compatible. A lower percent change can be accommodated witha series resistor. For further information, see the application information section.When this input is asserted to GND, the output voltage is increased by 5%. The input requires an open-collectorMargin Up 10 (open-drain) interface. It is not TTL compatible. The percent change can be reduced with a series resistor. Forfurther information, see the application information section.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): PTH12060W/L
PTH12060W TYPICAL CHARACTERISTICS (V
I
= 12 V)
(1) (2) (3)
0 2 4 6 8 10
Efficiency − %
IO − Output Current − A
50
60
70
80
90
100 VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
VO = 5 V
Output Ripple − mV
0
20
40
60
80
100
0 2 4 6 8 10
IO − Output Current − A
VO = 5 V VO = 2.5 V
VO = 1.8 V
VO = 1.5 V VO = 1.2 V
VO = 3.3 V
20
30
40
50
60
70
80
90 400LFM
200 LFM
100 LFM
Nat Conv
TA− Ambient Temperature −
5C
IO − Output Current − A
0 2 4 6 8 10
0
1
2
3
4
5
IO − Output Current − A
VO = 3.3 V
VO = 2.5 V
VO = 1.2 V
VO = 5 V
− Power Dissipation − W
PD
0 2 4 6 8 10
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
OUTPUT RIPPLEEFFICIENCY vsvs OUTPUT CURRENTOUTPUT CURRENT (see Note 3 below)
Figure 1. Figure 2.
POWER DISSIPATION TEMPERATURE DERATINGvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 3. Figure 4.(1) Characteristic data has been developed from actual products tested at 25 ° C. This data is considered typical data for the Converter.Applies to Figure 1 ,Figure 2 , and Figure 3 .(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer ' s maximum operatingtemperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in., double-sided PCB with 1 oz copper. For surface mountproducts (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please referto the mechanical specification for more information. Applies to Figure 4 .(3) The peak-to-peak output ripple voltage is measure with an external 10 µ F ceramic capacitor on the output.
6Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
PTH12060L TYPICAL CHARACTERISTICS (V
I
= 12 V)
(1) (2) (3)
50
60
70
80
90
100
Efficiency − %
VO = 0.8 V
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
VO = 1 V
IO − Output Current − A
0 2 4 6 8 10
0
20
40
60
80
100
Output Ripple − mV
VO = 1.8 V
VO = 1.5 V
VO = 1.2
V
VO = 1 V
VO = 0.8 V
IO − Output Current − A
0 2 4 6 8 10
− Power Dissipation − W
PD
0
0.5
1
1.5
2
2.5
3
IO − Output Current − A
0 2 4 6 8 10
VO = 1.8 V
VO = 1.5 V
VO = 1 V
VO = 0.8
V
VO = 1.2 V
20
30
40
50
60
70
80
90
IO − Output Current − A
0 2 4 6 8 10
100 LFM
Nat Conv
TA− Ambient Temperature −
5C
VO = ≤1.8 V
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
OUTPUT RIPPLEEFFICIENCY vsvs OUTPUT CURRENTOUTPUT CURRENT (see Note 3 below)
Figure 5. Figure 6.
POWER DISSIPATION TEMPERATURE DERATINGvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 7. Figure 8.(1) Characteristic data has been developed from actual products tested at 25 ° C. This data is considered typical data for the Converter.Applies to Figure 5 ,Figure 6 , and Figure 7 .(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer ' s maximum operatingtemperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in., double-sided PCB with 1 oz copper. For surface mountproducts (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please referto the mechanical specification for more information. Applies to Figure 8 .(3) The peak-to-peak output ripple voltage is measure with an external 10 µ F ceramic capacitor on the output.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): PTH12060W/L
APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
VI
++
GND
VO
V Sense
O
R
1%
SET
PTH12060
1
10
4
5
62
3
9
7
8
C
330 F
(Optional)
O
m
C
560 F
(Required)
I
m
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
The V
O
Adjust control (pin 4) sets the output voltage of the PTH12060W/L. The adjustment range is from 1.2V to5.5V for the W-suffix modules, and 0.8V to 1.8V for L-suffix modules. The adjustment method requires theaddition of a single external resistor, R
SET
, that must be connected directly between the V
O
Adjust and GNDpins
(1)
.Table 1 gives the standard value of the external resistor for a number of standard voltages, along with theactual output voltage that the resistance value provides. For other output voltages the value of the requiredresistor can either be calculated using Equation 1 , or simply selected from the range of values given in Table 3 .Figure 9 shows the placement of the required resistor.
Table 1. Standard Values of R
SET
for Standard Output Voltages
PTH12060W PTH12060L
V
O
(V) V
O
(V) V
O
(V)R
SET
(k Ω) R
SET
(k Ω)(Required) (Actual) (Actual)
5 0.280 5.009 N/A N/A3.3 2 3.294 N/A N/A2.5 4.32 2.503 N/A N/A2 8.06 2.01 N/A N/A1.8 11.5 1.801 0.130 1.81.5 24.3 1.506 3.57 1.4991.2 Open 1.2 12.1 1.2011.1 N/A N/A 18.7 1.1011.0 N/A N/A 32.4 0.9990.9 N/A N/A 71.5 0.9010.8 N/A N/A Open 0.8
(1) R
SET
:Use a 0.05-W rated resistor with a 1% tolerance and temperature stability of 100 ppm/ ° C or better. Place theresistor directly between pins 4 and 7, as close to the regulator as possible, using dedicated PCB traces.(2) Never connect capacitors from V
O
Adjust to either GND or V
O
. Any capacitance added to the V
O
Adjust pin affects thestability of the regulator.
Figure 9. V
O
Adjust Resistor Placement
8Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
Equation 1. Output Voltage Adjust
R =10k x
SET W0.8V -R k
SW
V -V
O min
(1)
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Use Equation 1 to calculate the adjust resistor value. See Table 2 for parameters, R
S
and V
min
.
Table 2. Adjust Equation Parameters
Parameter PTH12060W PTH12060L
V
min
(V) 1.2 0.8V
max
(V) 5.5 1.8R
S
(k Ω) 1.82 7.87
Table 3. Output Voltage Set-Point Resistor Values
PTH12060W PTH12060L
V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω)
1.20 Open 2.70 3.51 0.80 Open1.225 318 2.75 3.34 0.825 3121.25 158 2.80 3.18 0.85 1521.275 105 2.85 3.03 0.875 98.81.30 78.2 2.90 2.89 0.90 72.11.325 62.2 2.95 2.75 0.925 56.11.35 51.5 3.0 2.62 0.95 45.51.375 43.9 3.05 2.5 0.975 37.81.40 38.2 3.10 2.39 1.0 32.11.425 33.7 3.15 2.28 1.025 27.71.45 30.2 3.20 2.18 1.05 24.11.475 27.3 3.25 2.08 1.075 21.21.50 24.8 3.30 1.99 1.10 18.81.55 21 3.35 1.9 1.125 16.71.60 18.2 3.40 1.82 1.15 151.65 16 3.50 1.66 1.175 13.51.70 14.2 3.60 1.51 1.20 12.11.75 12.7 3.70 1.38 1.225 111.80 11.5 3.80 1.26 1.25 9.911.85 10.5 3.90 1.14 1.275 8.971.90 9.61 4.0 1.04 1.30 8.131.95 8.85 4.10 0.939 1.325 7.372.0 8.18 4.20 0.847 1.35 6.682.05 7.59 4.30 0.761 1.375 6.042.10 7.07 4.40 0.680 1.40 5.462.15 6.6 4.50 0.604 1.425 4.932.20 6.18 4.60 0.533 1.45 4.442.25 5.8 4.70 0.466 1.475 3.982.30 5.45 4.80 0.402 1.50 3.562.35 5.14 4.90 0.342 1.55 2.82.40 4.85 5.0 0.285 1.60 2.132.45 4.58 5.10 0.231 1.65 1.54
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): PTH12060W/L
CAPACITOR RECOMMENDATIONS FOR THE PTH12060 SERIES OF POWER MODULES
Input Capacitor
Output Capacitors (Optional)
Ceramic Capacitors
Tantalum Capacitors
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
Table 3. Output Voltage Set-Point Resistor Values (continued)
PTH12060W PTH12060L
V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω)
2.50 4.33 5.20 0.180 1.70 1.022.55 4.11 5.30 0.131 1.75 0.5512.60 3.89 5.40 0.085 1.80 0.1302.65 3.7 5.50 0.041
The recommended input capacitance is determined by the 560 µ F minimum capacitance and 1050 mArmsminimum ripple current rating. A 10 µ F X5R/X7R ceramic capacitor can be added to reduce the reflected inputripple current. The ceramic capacitor should be located between the input electrolytic and the module.
Ripple current, less than 100 m Ωequivalent series resistance (ESR) and temperature, are major considerationswhen selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have arecommended minimum voltage rating of 2 × (max. dc voltage + ac ripple). No tantalum capacitors were foundwith sufficient voltage rating to meet this requirement. At temperatures below 0 ° C, the ESR of aluminumelectrolytic capacitors increases. For these applications, Os-Con, polymer-tantalum, and polymer-aluminum typesshould be considered.
For applications with load transients (sudden changes in load current), regulator response benefits from externaloutput capacitance. The value of 330 µ F is used to define the transient response specification. For mostapplications, a high quality, computer-grade aluminum electrolytic capacitor is adequate. These capacitorsprovide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient temperaturesabove 0 ° C. Below 0 ° C, tantalum, ceramic, or Os-Con type capacitors are recommended. When using one ormore nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 m Ω(7 m Ωusing themanufacturer's maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified inTable 4 .
In addition to electrolytic capacitance, adding a 10 µ F X5R/X7R ceramic capacitor to the output reduces theoutput ripple voltage and improves the regulator's transient response. The measurement of both the output rippleand transient response is also best achieved across a 10 µ F ceramic capacitor.
Above 150 kHz, the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramiccapacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can beused to reduce the reflected ripple current at the input, and improve the transient response of the output. Whenused on the output, their combined ESR is not critical as long as the total value of ceramic capacitance does notexceed 300 µ F. Also, to prevent the formation of local resonances, do not place more than five identical ceramiccapacitors in parallel with values of 10 µ F or greater.
Tantalum type capacitors are most suited for use on the output bus, and are recommended for applicationswhere the ambient operating temperature can be less than 0 ° C. The AVX TPS, Sprague 593D/594/595, andKemet T495/T510 capacitor series are suggested over other tantalum types due to their higher rated surge,power dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors haveconsiderably higher ESR, reduced power dissipation, and lower ripple current capability. These capacitors arealso less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do nothave a stated ESR or surge current rating are not recommended for power applications.
When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit is encounteredwell before the maximum capacitance value is reached.
10 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
Capacitor Table
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Table 4 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripplecurrent (rms) ratings. The recommended number of capacitors required at both the input and output buses isidentified for each capacitor type.
Note: This is not an extensive capacitor list. Capacitors from other vendors are available with comparablespecifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are criticalparameters necessary to insure both optimum regulator performance and long capacitor life.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): PTH12060W/L
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
Table 4. Input/Output Capacitors
(1)
Capacitor Characteristics Quantity
Max RippleCapacitor Vendor,
Working Max ESR
Vendor NumberValue Current at Physical Size Input OutputType/Series (Style)
Voltage at 100 kHz( µ F) 85 ° C (Irms) (mm) Bus Bus(V) ( Ω)
(mA)
Panasonic, Aluminum 35 680 0.060 1100 12,5 × 13,5 1 1 EEVFK1V681Q
FK (SMD) 25 1000 0.060 1100 12,5 × 13,5 1 1 EEVFK1E102Q
FC (Radial) 25 560 0.065 1205 12,5 × 15 1 1 EEUFC1E561S
United Chemi-Con
PS, Poly-Aluminum (Radial) 16 330 0.0014 5050 10 × 12,5 2 ≤2 16PS330MJ12
LXZ, Aluminum 16 680 0.068 1050 10 × 16 1 1 LXZ16VB681M10X16LL
PXA, Poly-Aluminum (SMD) 16 330 0.014 5050 10 × 12,2 2 ≤2 PXA16VC331MJ12
Nichicon Aluminum
PM (Radial) 25 560 0.060 1060 12,5 × 15 1 1 UPM1E561MHH6
HD (Radial) 16 680 0.038 1430 10 × 16 1 1 UHD1C681MHR
PM (Radial) 35 560 0.048 1360 16 × 15 1 1 UPM1V561MHH6
Panasonic, Poly-Aluminum
S/SE (SMD) 6.3 180 0.005 4000 7,3 × 4,3 × 4,2 N/R
(2)
≤1
(3)
EEFSE0J181R(V
O
≤5.1V)
Sanyo
TPE, POSCAP (SMD) 10 330 0.025 3000 7,3 × 5,7 N/R
(2)
≤4 10TPE330M
SEPC, OS-CON (Radial) 16 470 0.010 > 9700 10 × 13 2 ≤1 16SEPC470M
SVP, OS-CON (SMD) 16 330 0.016 4700 11 × 12 2 ≤3 16SVP330M
AVX
TPS, Tantalum (SMD) 10 470 0.045 > 1723 N/R
(2)
≤5
(3)
TPSE477M019R0045(V
O
≤5.1V)7,3 × 5,7 × 4,1TPS, Tantalum (SMD) 10 330 0.045 > 1723 2 ≤5
(3)
TPSE337M019R0045(V
O
≤5.1V)
Kemet
T520, Poly-Tantalum (SMD) 10 330 0.040 1800 N/R
(2)
≤5
(3)
T520X337M010AS
T530, Tantalum/Organic 10 330 0.015 > 3800 4,3 × 7,3 × 4,0 N/R
(2)
≤2 T53X337M010AS
6.3 470 0.012 4200 N/R
(2)
≤2
(3)
T530X477M0061S(V
O
≤5.1V)
Vishay-Sprague
594D, Tantalum (SMD) 10 470 0.100 1440 7,2 × 6 × 4,1 N/R
(2)
595D477X0010R2T(V
O
≤5.1V)
94SP, Organic (Radial) 16 270 0.018 4200 10 × 10,5 2
(4)
≤3 94SP277X0016FBP
94SVP, Organic (SMD) 16 330 0.017 4500 10 × 12.7 2 ≤2 94SVP337X0016F12
Kemet, Ceramic X5R (SMD) 16 10 0.002 1210 case 1
(5)
≤5 C1210C106M4PAC
6.3 47 0.002 3225 mm N/R
(2)
≤5 C1210C476K9PAC
Murata, Ceramic X5R (SMD) 6.3 100 0.002 1210 case N/R
(2)
≤3 GRM32ER60J107M
6.3 47 3225 mm N/R
(2)
≤5 GRM32ER60J476M
16 22 1
(5)
≤5 GRM32ER61C226K
16 10 1
(5)
≤5 GRM32DR61C106K
TDK, Ceramic X5R (SMD) 6.3 100 0.002 1210 case N/R
(2)
≤3 C3225X5R0J107MT
6.3 47 3225 mm N/R
(2)
≤5 C3225X5R0J476MT
16 22 1
(5)
≤5 C3225X5R1C226MT
16 10 1
(5)
≤5 C3225X5R1C106MT
(1) Capacitor Supplier VerificationPlease verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because oflimited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-termconsideration for obsolescence.RoHS, Lead-free and Material DetailsPlease consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing processrequirements. Component designators or part number deviations can occur when material composition or soldering requirements areupdated.
(2) N/R – Not recommended. The capacitor voltage rating does not meet the minimum operating limits.(3) The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V.(4) A total capacitance of 540 µ F is acceptable based on the combined ripple current rating.(5) Ceramic capacitors are required to complement electrolytic types at the input and to reduce high-frequency ripple current.
12 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
Designing for Very Fast Load Transients
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
The transient response of the dc/dc converter is characterized using a load transient with a di/dt of 1 A/ µ s. Thetypical voltage deviation for this load transient is given in the data sheet specification table using the optionalvalue of output capacitance. As the di/dt of a transient is increased, the response of a converter's regulationcircuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation with any dc/dcconverter once the speed of the transient exceeds its bandwidth capability. If the target application specifies ahigher di/dt or lower voltage deviation, the requirement is met with additional output capacitor decoupling. Inthese cases, special attention must be paid to the type, value, and ESR of the capacitors selected.
If the transient performance requirements exceed that specified in this data sheet, or the total amount of loadcapacitance is above 3,000 µ F, the selection of output capacitors becomes more important.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): PTH12060W/L
Features of the PTH Family of Non-Isolated Wide Output Adjust Power Modules
Introduction
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
The PTH/PTV family of non-isolated, wide-output adjustable power modules are optimized for applications thatrequire a flexible, high performance module that is small in size. Each of these products are POLA™ compatible.POLA-compatible products are produced by a number of manufacturers, and offer customers advanced,nonisolated modules with the same footprint and form factor. POLA parts are also ensured to be interoperable,thereby, providing customers with second-source availability.
From the basic, Just Plug it In functionality of the 6-A modules, to the 30-A rated feature-rich PTHxx030, theseproducts were designed to be very flexible, yet simple to use. The features vary with each product. Table 5provides a quick reference to the features by product series and input bus voltage.
Table 5. Operating Features by Series and Input Bus Voltage
Series Input Bus (V) I
O
(A) Adjust On/Off Over- Prebias Auto- Margin Output Thermal(Trim) Inhibit Current Startup Track™ Up/Down Sense Shutdown
3.3 6 • • • • •PTHxx050 5 6 • • • • •12 6 • • • • •3.3 / 5 10 • • • • • • •PTHxx060
12 10 • • • • • • •3.3 / 5 15 • • • • • • •PTHxx010
12 12 • • • • • • •5 8 • • • • •PTVxx010
12 8 • • • • •3.3 / 5 22 • • • • • • • •PTHxx020
12 18 • • • • • • • •3.3 / 5 18 • • • • • • •PTVxx020
12 16 • • • • • • •3.3 / 5 30 • • • • • • • •PTHxx030
12 26 • • • • • • • •
For simple point-of-use applications, the PTH12050 (6 A) provides operating features such as an on/off inhibit,output voltage trim, prebias start-up and overcurrent protection. The PTH12060 (10 A), and PTH12010 (12 A)include an output voltage sense, and margin up/down controls. Then the higher output current, PTH12020 (18 A)and PTH12030 (26 A) products incorporate overtemperature shutdown protection.
The PTV12010 and PTV12020 are similar parts offered in a vertical, single in-line pin (SIP) profile, at slightlylower current ratings.
All of the products referenced in Table 5 include Auto-Track™. This feature was specifically designed to simplifythe task of sequencing the supply voltages in a power system. This and other features are described in thefollowing sections.
14 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
POWER-UP INTO A NON-PREBIASED OUTPUT — AUTO-TRACK™ FUNCTION
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
The Auto-Track function is unique to the PTH/PTV family, and is available with all POLA products. Auto-Trackwas designed to simplify the amount of circuitry required to make the output voltage from each module power upand power down in sequence. The sequencing of two or more supply voltages during power up is a commonrequirement for complex mixed-signal applications that use dual-voltage VLSI ICs such as the TMS320™ DSPfamily, microprocessors, and ASICs.
Basic Power-Up using Auto-Track™
For applications requiring output voltage on/off control, each series of the PTH family incorporates the trackcontrol pin. The Auto-Track feature should be used instead of the inhibit feature wherever there is a requirementfor the output voltage from the regulator to be turned on/off.
Figure 10 shows the typical application for basic start-up. Note the discrete transistor (Q1). The track input hasits own internal pull-up to a potential of 5 V to 13.2 V The input is not compatible with TTL logic devices. Anopen-collector (or open-drain) discrete transistor or supply voltage supervisor (TPS3808 or TPS7712) isrecommended for control.
Figure 10. Basic Start-up Control Circuit
Turning on Q1 applies a low voltage to the track control pin and disables the output of the module. If Q1 is thenturned off, the output ramps immediately to the regulated output voltage. A regulated output voltage is producedwithin 35 ms. With the initial application of the input source voltage, the track pin must be held low (Q1 turnedON) for at least 40 ms. Figure 11 shows the typical rise in both the output voltage and input current, following theturn off of Q1. The turn off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms weremeasured with a 10-A constant current load.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PTH12060W/L
Q1VDS (2 V/div)
VO (2 V/div)
II (2 A/div)
t − Time − 40 ms/div
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
Figure 11. Power-Up from Track Control
NOTE:
If a prebias condition is not present, it is highly recommended that the Track controlpin be used for controlled power-up and power-down. If Track control is not used, theoutput voltage starts up and overshoots by as much as 10%, before settling at theoutput voltage setpoint.
How Auto-Track™ Works
Auto-Track works by forcing the module output voltage to follow a voltage presented at the Track control pin
(1)
.This control range is limited to between 0 V and the module set-point voltage. Once the track-pin voltage israised above the set-point voltage, the module output remains at its set-point
(2)
. As an example, if the Track pinof a 2.5-V regulator is at 1 V, the regulated output is 1 V. If the voltage at the Track pin rises to 3 V, the regulatedoutput does not go higher than 2.5 V.
When under Auto-Track control, the regulated output from the module follows the voltage at its Track pin on avolt-for-volt basis. By connecting the Track pin of a number of these modules together, the output voltages followa common signal during power up and power down. The control signal can be an externally generated masterramp waveform, or the output voltage from another power supply circuit
(3)
. For convenience, the Track inputincorporates an internal RC-charge circuit. This operates off the module input voltage to produce a suitable risingwaveform at power up.
16 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Typical Auto-Track Application
The basic implementation of Auto-Track allows for simultaneous voltage sequencing of a number of Auto-Trackcompliant modules. Connecting the Track inputs of two or more modules forces their track input to follow thesame collective RC-ramp waveform, and allows their power-up sequence to be coordinated from a commonTrack control signal. This can be an open-collector (or open-drain) device, such as a power-up reset voltagesupervisor IC. See U3 in Figure 12 .
To coordinate a power-up sequence, the Track control must first be pulled to ground potential through R
TRK
asdefined in Figure 12 . This should be done at or before input power is applied to the modules. The ground signalshould be maintained for at least 40 ms after input power has been applied. This brief period gives the modulestime to complete their internal soft-start initialization
(4)
, enabling them to produce an output voltage. A low-costsupply voltage supervisor IC, that includes a built-in time delay, is an ideal component for automaticallycontrolling the Track inputs at power up.
Figure 12 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequencedpower up of two 12-V input Auto-Track modules. The output of the TL7712A supervisor becomes active abovean input voltage of 3.6 V, enabling it to assert a ground signal to the common track control well before the inputvoltage has reached the module's undervoltage lockout threshold. The ground signal is maintained untilapproximately 43 ms after the input voltage has risen above U3's voltage threshold, which is 10.95 V. The 43-mstime period is controlled by the capacitor C3. The value of 3.3 µ F provides sufficient time delay for the modulesto complete their internal soft-start initialization. The output voltage of each module remains at zero until the trackcontrol voltage is allowed to rise. When U3 removes the ground signal, the track control voltage automaticallyrises. This causes the output voltage of each module to rise simultaneously with the other modules, until eachreaches its respective set-point voltage.
Figure 13 shows the output voltage waveforms from the circuit of Figure 12 after input voltage is applied to thecircuit. The waveforms, V
O
1 and V
O
2, represent the output voltages from the two power modules, U1 (3.3 V) andU2 (1.8 V), respectively. V
TRK
, V
O
1, and V
O
2 are shown rising together to produce the desired simultaneouspower-up characteristic.
The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltagethreshold, the ground signal is re-applied to the common track control. This pulls the track inputs to zero volts,forcing the output of each module to follow, as shown in Figure 14 . In order for a simultaneous power-down tooccur, the track inputs must be pulled low before the input voltage has fallen below the modules' undervoltagelockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longerpresent, their outputs can no longer follow the voltage applied at their track input. During a power-downsequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and theAuto-Track slew rate. If the Track pin is pulled low at a slew rate greater than 1 V/ms, the discharge of the outputcapacitors will induce large currents which could exceed the peak current rating of the module. This will result ina reduction in the maximum allowable output capacitance as listed in the Electrical Characteristics table. Whencontrolling the Track pin of the PTH12060W using a voltage supervisor IC, the slew rate is increased, thereforeC
O
max is reduced to 2200 µF.
Notes on Use of Auto-Track™1. The Track pin voltage must be allowed to rise above the module set-point voltage before the moduleregulates at its adjusted set-point voltage.2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with rampspeeds of up to 1 V/ms.3. The absolute maximum voltage that may be applied to the Track pin is the input voltage V
I
.4. The module cannot follow a voltage at its track control input until it has completed its soft-start initialization.This takes about 40 ms from the time that a valid voltage has been applied to its input. During this period, itis recommended that the Track pin be held at ground potential.5. The Auto-Track function is disabled by connecting the Track pin to the input voltage (V
I
). When Auto-Track isdisabled, the output voltage rises at a quicker and more linear rate after input power has been applied.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PTH12060W/L
N = Number of Track pins connected together
10 kΩ
# RTRK = 100 Ω / N
VI = 12 V Vo1 = 3.3 V
RSET1
CO1
+
C
+
PTH12050W
5
63
4
2
Track
VIVO
GND
Inhibit 1Adjust
TL7712A
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
CT
CREF RRST
Vo2 = 1.8 V
CO2
+
C
+
PTH12060W
7
10
4
5
62
3
9 8
Track
VIVO
GNDInhibit 1
Up Dn Sense
Adjust
SET2
U1
U2
U3
RTRK #
2.0 kΩ
11.5 kΩ
I2
0.1 µF3.3 µF
50 Ω
I1
R
t − Time − 20 ms/div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
t − Time − 400 µs/div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
Figure 12. Sequenced Power Up and Power Down Using Auto-Track
Figure 13. Simultaneous Power Up With Auto-Track Figure 14. Simultaneous Power Down with Auto-TrackControl Control
18 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
POWER-UP INTO A PREBIASED OUTPUT — START-UP USING INHIBIT CONTROL
t − Time − 10 ms/div
VO1 (1 V/div)
VO2 (1 V/div)
IO2 (5 V/div)
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series ofpower modules. (Note that this is a feature enhancement for the many of the W-suffix products)
[1]
.
A prebias startup condition occurs as a result of an external voltage being present at the output of a powermodule prior to its output becoming active. This often occurs in complex digital systems when current fromanother power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Anotherpath might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. Aprebias can cause problems with power modules that incorporate synchronous rectifiers. This is because undermost operating conditions, such modules can sink as well as source output current. The 12-V input PTH modulesall incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit pin is heldlow.
Conditions for Prebias Holdoff
In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions mustbe maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the outputis allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of theground signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Trackdisabled
[2]
. To further ensure that the regulator doesn ’ t sink output current, (even with a ground signal applied toits Inhibit), the input voltage must always be greater than the applied prebias source. This condition must existthroughout the power-up sequence
[3]
.
The soft-start period is complete when the output begins rising above the prebias voltage. Once it is completethe module functions as normal, and sinks current if a voltage higher than the nominal regulation value is appliedto its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risento either the set-point voltage, or the voltage applied at the module's Track control pin, whichever is lowest.to its output.
Prebias Demonstration Circuit
Figure 15 shows the startup waveforms for the demonstration circuit shown in Figure 16 . The initial rise in V
O
2 isthe prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that theoutput current from the PTH12010L module (I
O
2) is negligible until its output voltage rises above the appliedprebias.
Figure 15. Prebias Startup Waveforms
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PTH12060W/L
Up Dn Sense
V =12V
I
ASIC
VCORE VC CI O
I 2
O
PTH12010L
1
10
4
5
62
3
9
Tra ck
GND
Inhibit
7
Vadj
Sense
+
V 1=3.3V
O
V 2=1.8V
O
R1
2kW
R5
10k0
R4
100kW
R3
11k0
R1
130 W
C2
330 Fm
C4
330 Fm
C6
0.68 Fm
C5
0.1 Fm
C3
330 Fm
C1
330 Fm
+
+
PTH12020W
7
10
4
5
62
3
9
Tra ck
VI
VI
VO
VO
GND
Inhibit
1
Adjust
+
TL7702B
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
+
8
8
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
Figure 16. Application Circuit Demonstrating Prebias Startup
Notes:
1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now beenincorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with aproduction lot date code of 0423 or later.2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by thevoltage applied to the Track control pin, the output sinks current during the period that the track controlvoltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track bedisabled when not being used. This is accomplished by connecting the Track pin to the input voltage, V
I
. Thisraises the Track pin voltage well above the set-point voltage prior to the module ’ s start up, thereby, defeatingthe Auto-Track feature.3. To further ensure that the regulator's output does not sink current when power is first applied (even with aground signal applied to the Inhibit control pin), the input voltage must always be greater than the appliedprebias source. This condition must exist throughout the power-up sequence of the power system.
20 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
Remote Sense
Overcurrent Protection
Overtemperature Protection (OTP)
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Products with this feature incorporate an output voltage sense pin, V
O
Sense. A remote sense improves the loadregulation performance of the module by allowing it to compensate for any IR voltage drop between its outputand the load. An IR drop is caused by the high output current flowing through the small amount of pin and traceresistance.
To use this feature simply connect the V
O
Sense pin to the V
O
node, close to the load circuit (see data sheetstandard application circuit). If a sense pin is left open-circuit, an internal low-value resistor (15- Ωor less)connected between the pin and the output node, ensures the output remains in regulation.
With the sense pin connected, the difference between the voltage measured directly between the V
O
and GNDpins, and that measured from V
O
Sense to GND, is the amount of IR drop being compensated by the regulator.This should be limited to a maximum of 0.3 V.Note: The remote sense feature is not designed to compensate for the forward drop of nonlinear orfrequency dependent components that may be placed in series with the converter output. Examples includeOR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the remotesense connection, they are effectively placed inside the regulation control loop, which can adversely affectthe stability of the regulator.
For protection against load faults, all modules incorporate output overcurrent protection. Applying a load thatexceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, amodule periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode ofoperation, whereby, the module continues in a cycle of successive shutdown and power up until the load fault isremoved. During this period, the average current flowing into the fault is significantly reduced. Once the fault isremoved, the module automatically recovers and returns to normal operation.
The PTH12020, PTV12020, and PTH12030 products have overtemperature protection. These products have anon-board temperature sensor that protects the module's internal circuitry against excessively high temperatures.A rise in the internal temperature may be the result of a drop in airflow, or a high ambient temperature. If theinternal temperature exceeds the OTP threshold, the module's Inhibit control is internally pulled low. This turnsthe output off. The output voltage drops as the external output capacitors are discharged by the load circuit. Therecovery is automatic, and begins with a soft-start power up. It occurs when the sensed temperature decreasesby about 10 ° C below the trip point.Note: The overtemperature protection is a last resort mechanism to prevent thermal stress to the regulator.Operation at or close to the thermal shutdown temperature is not recommended and will reduce thelong-term reliability of the module. Always operate the regulator within the specified Safe Operating Area(SOA) limits for the worst-case conditions of ambient temperature and airflow.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PTH12060W/L
Margin Up/Down Controls
U
D
499
R 99.8 k
%
499
R 99.8 k
%
æ ö
= - W
ç ÷
D
è ø
æ ö
= - W
ç ÷
D
è ø
(2)
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
The PTH12060, PTH12010, PTH12020, and PTH12030 products incorporate Margin Up and Margin Downcontrol inputs. These controls allow the output voltage to be momentarily adjusted
[1]
, either up or down, by anominal 5%. This provides a convenient method for dynamically testing the operation of the load circuit over itssupply margin or range. It can also be used to verify the function of supply voltage supervisors. The ± 5% changeis applied to the adjusted output voltage, as set by the external resistor, R
SET
at the V
O
Adjust pin.
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal
[2]
. Alow-leakage, open-drain device, such as an n-channel MOSFET or p-channel JFET is recommended for thispurpose
[3]
. Adjustments of less than 5% can also be accommodated by adding series resistors to the controlinputs. The value of the resistor can be selected from Table 6 , or calculated using Equation 2 .
Margin Up/Down Adjust Resistance Calculation
To reduce the margin adjustment to a value less than 5%, series resistors are required (See R
D
and R
U
inEquation 2 ). For the same amount of adjustment, the resistor value calculated for R
U
and R
D
is the same. Theformula is as follows.
Where Δ% = The desired amount of margin adjust in percent.
Notes:
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they areactivated simultaneously, the affect on the output voltage may not completely cancel, resulting in thepossibility of a slightly higher error in the output voltage set point.2. The ground reference should be a direct connection to the module GND. This produces a more accurateadjustment at the load circuit terminals. The transistors Q1 and Q2 should be located close to the regulator.3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. Thisincludes TTL logic. These are analog inputs and should only be controlled with a true open-drain device(preferably a discrete MOSFET transistor). The device selected should have low off-state leakage current.Each input sources 8 µ A when grounded, and has an open-circuit voltage of 0.8 V.
Table 6. Margin Up/Down Resistor Values
% Adjust 5% 4% 3% 2% 1%
R
U
/ R
D
(k Ω)0.0 24.9 66.5 150.0 397.0
22 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
CO
+
CI
VI
GND
MarginDown
L
O
A
D
Q2
+VO
+VO
Q1
+
MarginUp
0V
RDRU
PT H12010W
(TopView)
1
2
10 9 8 7
6
54
3
GND
R
0.1W,1%
SET
PTH12060W/L
www.ti.com
.................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
Figure 17. Margin Up/Down Application Schematic
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): PTH12060W/L
TAPE AND REEL SPECIFICATIONS
TRAY SPECIFICATIONS
PTH12060W/L
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 ....................................................................................................................................................
www.ti.com
24 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
PTH12060LAH ACTIVE Through-
Hole Module EUW 10 36 RoHS (In
Work) & Green
(In Work)
SN N / A for Pkg Type -40 to 85
PTH12060LAS ACTIVE Surface
Mount Module EUY 10 36 RoHS (In
Work) & Green
(In Work)
SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060LAST ACTIVE Surface
Mount Module EUY 10 250 RoHS (In
Work) & Green
(In Work)
SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060LAZ ACTIVE Surface
Mount Module EUY 10 36 RoHS (In
Work) & Green
(In Work)
SNAGCU Level-3-260C-168 HR -40 to 85
PTH12060LAZT ACTIVE Surface
Mount Module EUY 10 250 RoHS (In
Work) & Green
(In Work)
SNAGCU Level-3-260C-168 HR -40 to 85
PTH12060WAD ACTIVE Through-
Hole Module EUW 10 36 RoHS (In
Work) & Green
(In Work)
SN Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060WAH ACTIVE Through-
Hole Module EUW 10 36 RoHS (In
Work) & Green
(In Work)
SN Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060WAS ACTIVE Surface
Mount Module EUY 10 36 RoHS (In
Work) & Green
(In Work)
SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060WAST ACTIVE Surface
Mount Module EUY 10 250 RoHS (In
Work) & Green
(In Work)
SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS -40 to 85
PTH12060WAZ ACTIVE Surface
Mount Module EUY 10 36 RoHS (In
Work) & Green
(In Work)
SNAGCU Level-3-260C-168 HR -40 to 85
PTH12060WAZT ACTIVE Surface
Mount Module EUY 10 250 RoHS (In
Work) & Green
(In Work)
SNAGCU Level-3-260C-168 HR -40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2017
Addendum-Page 2
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
PTH12060WAD PTH12060WAH PTH12060WAS PTH12060WAST PTH12060WAZ PTH12060WAZT