High Accuracy Instrumentation Amplifier AMP02 FEATURES Low Offset Voltage: 100 V max Low Drift: 2 V/C max Wide Gain Range: 1 to 10,000 High Common-Mode Rejection: 115 dB min High Bandwidth (G = 1000): 200 kHz typ Gain Equation Accuracy: 0.5% max Single Resistor Gain Set Input Overvoltage Protection Low Cost Available in Die Form APPLICATIONS Differential Amplifier Strain Gage Amplifier Thermocouple Amplifier RTD Amplifier Programmable Gain Instrumentation Amplifier Medical Instrumentation Data Acquisition Systems FUNCTIONAL BLOCK DIAGRAM 8-Lead PDIP and CERDIP 16-Lead SOIC RG1 1 8 RG2 -IN 2 7 V+ +IN 3 6 OUT NC 3 14 NC V- 4 5 REFERENCE -IN 4 13 V+ +IN 5 12 SENSE 16 NC NC 1 RG1 2 15 RG2 NC 6 11 OUT V- 7 10 REFERENCE NC 8 9 NC NC = NO CONNECT V+ +IN RG -IN G= 3 - 1 RG1 8 RG2 2 + 7 6 OUT 5 4 REFERENCE V- VOUT 50k = (+IN) - (-IN) RG ( ) +1 FOR SOL CONNECT SENSE TO OUTPUT Figure 1. Basic Circuit Connections GENERAL DESCRIPTION The AMP02 is the first precision instrumentation amplifier available in an 8-lead package. Gain of the AMP02 is set by a single external resistor and can range from 1 to 10,000. No gain set resistor is required for unity gain. The AMP02 includes an input protection network that allows the inputs to be taken 60 V beyond either supply rail without damaging the device. Laser trimming reduces the input offset voltage to under 100 V. Output offset voltage is below 4 mV, and gain accuracy is better than 0.5% for a gain of 1000. ADI's proprietary thin-film resistor process keeps the gain temperature coefficient under 50 ppm/C. Due to the AMP02's design, its bandwidth remains very high over a wide range of gain. Slew rate is over 4 V/s, making the AMP02 ideal for fast data acquisition systems. A reference pin is provided to allow the output to be referenced to an external dc level. This pin may be used for offset correction or level shifting as required. In the 8-lead package, sense is internally connected to the output. For an instrumentation amplifier with the highest precision, consult the AMP01 data sheet. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002. All rights reserved. AMP02* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Materials View a parametric search of comparable parts Technical Articles * Auto-Zero Amplifiers * High-performance Adder Uses Instrumentation Amplifiers * Input Filter Prevents Instrumentation-amp RF-Rectification Errors * The AD8221 - Setting a New Industry Standard for Instrumentation Amplifiers Documentation Application Notes * AN-244: A User's Guide to I.C. Instrumentation Amplifiers * AN-245: Instrumentation Amplifiers Solve Unusual Design Problems * AN-282: Fundamentals of Sampled Data Systems * AN-589: Ways to Optimize the Performance of a Difference Amplifier * AN-671: Reducing RFI Rectification Errors in In-Amp Circuits Data Sheet * AMP02: High Accuracy 8-Pin Instrumentation Amplifier Data Sheet Technical Books * A Designer's Guide to Instrumentation Amplifiers, 3rd Edition, 2006 Design Resources * * * * AMP02 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AMP02 EngineerZone Discussions Sample and Buy Tools and Simulations Visit the product page to see pricing options * In-Amp Error Calculator * AMP02 SPICE Macro-Model Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. AMP02-SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter OFFSET VOLTAGE Input Offset Voltage Input Offset Voltage Drift Output Offset Voltage (@ VS = 15 V, VCM = 0 V, TA = 25C, unless otherwise noted.) Symbol Conditions VIOS TA = 25C -40C TA +85C -40C TA +85C TA = 25C -40C TA +85C -40C TA +85C VS = 4.8 V to 18 V G = 100, 1000 G = 10 G=1 VS = 4.8 V to 18 V -40C TA +85C G = 1000, 100 G = 10 G=1 TCVIOS VOOS Output Offset Voltage Drift TCVOOS Power Supply Rejection PSR Min AMP02E Typ Max 20 50 0.5 1 4 50 100 200 2 4 10 100 120 110 90 105 90 70 110 95 75 dB dB dB Differential, G 1000 Common Mode, G = 1000 TA = 25C1 VCM = 11 V G = 1000, 100 G = 10 G=1 VCM = 11 V -40C TA +85C G = 100, 1000 G = 10 G=1 10 16.5 OUTPUT RATING Output Voltage Swing GTC NOISE Voltage Density, RTI fO = 1 kHz G = 1000 G = 100 G = 10 G=1 fO = 1 kHz, G = 1000 0.1 Hz to 10 Hz G = 1000 G = 100 G = 10 Noise Current Density, RTI in Input Noise Voltage en p-p DYNAMIC RESPONSE Small-Signal Bandwidth (-3 dB) G = 100, 1000 Slew Rate Settling Time BW G=1 G = 10 SR tS G = 10, RL = 1 k To 0.01% 10 V Step G = 1 to 1000 5 11 20 10 nA pA/C nA pA/C 10 16.5 G G V 110 95 75 115 110 90 dB dB dB 110 95 75 120 110 90 105 90 70 115 105 85 dB dB dB 0.50 0.30 0.25 0.02 10k 0.006 20 en 4 250 2 15 120 115 95 1 TA = 25C, RL = 1 k RL = 1 k, -40C TA +85C Output-to-Ground Short Output-to-Ground Short 10 115 100 80 G = 1 to 1000 1 G 10002, 3 VOUT Positive Current Limit Negative Current Limit 11 G = 1000 G = 100 G = 10 G=1 G V V V/C mV mV V/C 110 95 75 RIN Gain Range Nonlinearity Temperature Coefficient 200 350 4 8 20 200 dB dB dB INPUT Input Resistance 50 k +1 RG 40 100 1 2 9 100 115 100 80 2 150 1.2 9 G= Unit 110 95 75 TA = 25C -40C TA +85C TA = 25C -40C TA +85C GAIN Gain Equation Accuracy Max 125 110 90 IB TCIB IOS TCIOS IVR CMR AMP02F Typ 115 100 80 INPUT CURRENT Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift Input Voltage Range Common-Mode Rejection Min 12 11 4 13 12 22 32 0.70 0.50 0.40 0.05 10k 1 0.006 20 50 12 11 50 % % % % V/V % ppm/C 13 12 22 32 V V mA mA 9 10 18 120 0.4 9 10 18 120 0.4 nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz 0.4 0.5 1.2 0.4 0.5 1.2 V p-p V p-p V p-p 1200 300 200 6 1200 300 200 6 kHz kHz kHz V/s 10 10 s 4 SENSE INPUT Input Resistance Voltage Range RIN 25 11 25 11 k V REFERENCE INPUT Input Resistance Voltage Range Gain to Output RIN 50 11 1 50 11 1 k V V/V -2- REV. E AMP02 Parameter Symbol POWER SUPPLY Supply Voltage Range Supply Current VS ISY Conditions Min AMP02E Typ Max Min 18 6 6 4.5 5 5 4.5 TA = 25C -40C TA +85C AMP02F Typ 5 5 Max Unit 18 6 6 V mA mA NOTES 1 Input voltage range guaranteed by common-mode rejection test. 2 Guaranteed by design. 3 Gain tempco does not include the effects of external component drift. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1, 2 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 3 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for P-DIP package; JA is specified for device soldered to printed circuit board for SOIC package. Supply Voltage 18 V Common-Mode Input Voltage [(V-) - 60 V] to [(V+) + 60 V] Differential Input Voltage [(V-) - 60 V] to [(V+) + 60 V] Output Short-Circuit Duration Continuous Operating Temperature Range -40C to +85C Storage Temperature Range -65C to +150C Function Temperature Range -65C to +150C Lead Temperature (Soldering, 10 sec) 300C Package Type JA3 JC Unit 8-Lead Plastic DIP (P) 16-Lead SOIC (S) 96 92 37 27 C/W C/W ORDERING GUIDE Model AMP02EP AMP02FP AMP02AZ/883C AMP02FS AMP02GBC AMP02FS-REEL VIOS max @ VOOS max @ Temperature TA = 25C TA = 25C Range Package Description 100 V 200 V 200 V 200 V 4 mV 8 mV 10 mV 8 mV -40C to +85C -40C to +85C -55C to +125C -40C to +85C 200 V 8 mV -40C to +85C 8-Lead Plastic DIP 8-Lead Plastic DIP 8-Lead CERDIP 16-Lead SOIC Die 16-Lead SOIC V+ 25k SENSE 25k OUT 25k 25k REFERENCE -IN +IN RG1 RG2 V- Figure 2. Simplified Schematic REV. E -3- AMP02 8 1. RG1 2. -IN 3. +IN 4. V- 5. REFERENCE 6. OUT 7. V+ 8. RG2 9. SENSE CONNECT SUBSTRATE TO V- 1 DIE SIZE 0.103 inch 0.116 inch, 11,948 sq. mils (2.62 mm 2.95 mm, 7.73 sq. mm) NOTE: PINS 1 and 8 are KELVIN CONNECTED Die Characteristics WAFER TEST LIMITS* (@ V = 15 V, V S CM = 0 V, TA = 25C, unless otherwise noted.) AMP02 GBC Limits Unit VIOS 200 V max VOOS 8 mV max Parameter Symbol Input Offset Voltage Output Offset Voltage Conditions VS = 4.8 V to 18 V G = 1000 G = 100 G = 10 G=1 110 110 95 75 Power Supply Rejection PSR Input Bias Current IB 20 nA max Input Offset Current IOS 10 nA max Input Voltage Range IVR Guaranteed by CMR Tests 11 V min CMR VCM = 11 V G = 1000 G = 100 G = 10 G=1 110 110 95 75 Common-Mode Rejection G= Gain Equation Accuracy Output Voltage Swing VOUT Supply Current ISY 50 k + 1, G = 1000 RG RL = 1 k dB dB 0.7 % max 12 V min 6 mA max *Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AMP02 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. E Typical Performance Characteristics-AMP02 TA = 25C 1000 VS = 15V 160 3000 UNITS FROM 3 RUNS 400 UNITS FROM 3 RUNS VS = 15V 140 800 NUMBER OF UNITS 700 600 500 400 300 120 100 80 60 40 200 0 -100 -80 -60 -40 -30 0 20 40 60 80 100 INPUT OFFSET VOLTAGE - V 0 TPC 1. Typical Distribution of Input Offset Voltage 1100 TA = 25C 1000 VS = 15V 3000 UNITS FROM 3 RUNS 0 NUMBER OF UNITS NUMBER OF UNITS 700 600 500 400 300 -5 150 125 100 75 0 5 TPC 4. Typical Distribution of Output Offset Voltage 20 40 32 VS = 15V VCM = 0V INPUT BIAS CURRENT - nA 2.0 1.5 1.0 0.5 25 0 50 TEMPERATURE - C 75 TPC 7. Input Offset Current vs. Temperature 100 -1.0 6 24 20 16 12 8 0 -50 0 5 10 15 POWER SUPPLY VOLTAGE - V 20 TPC 6. Output Offset Voltage Change vs. Supply Voltage VS = 15V VCM = 0V 5 4 3 2 1 4 -25 -0.5 VS = 15V VCM = 0V 28 2.5 0 60 80 100 120 140 160 TCVOOS - V/C TPC 5. Typical Distribution of TCVOOS TA = 25C 0.5 -1.5 0 20 1.0 INPUT BIAS CURRENT - nA 3.0 5 10 15 POWER SUPPLY VOLTAGE - V 1.5 400 UNITS FROM 3 RUNS VS = 15V 25 0 1 2 3 4 -5 -4 -3 -2 -1 0 OUTPUT OFFSET VOLTAGE - mV 0 200 50 100 INPUT OFFSET CURRENT - nA 0 TPC 3. Input Offset Voltage Change vs. Supply Voltage 200 REV. E 5 TPC 2. Typical Distribution of TCVIOS 900 0 -50 10 -10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVIOS - V/C 175 800 TA = 25C 15 20 100 INPUT OFFSET VOLTAGE - mV NUMBER OF UNITS 900 20 INPUT OFFSET VOLTAGE - V 1100 -25 0 50 25 TEMPERATURE - C 75 TPC 8. Input Bias Current vs. Temperature -5- 100 0 0 10 15 5 POWER SUPPLY VOLTAGE - V TPC 9. Input Bias Current vs. Supply Voltage 20 AMP02 G = 100 40 G = 10 20 G=1 0 -20 -40 1k 10k 100k 1M FREQUENCY - Hz 10M TPC 10. Closed-Loop Voltage Gain vs. Frequency G = 1000 120 G = 100 100 G = 10 80 60 G=1 40 TA = 25C 20 VS = 15V VCM = 2V p-p 0 1 100 1k 10 FREQUENCY - Hz POWER SUPPLY REJECTION - dB G = 10 100 G=1 80 60 40 TA = 25C VS = 15V VS = 1V 20 1 10 1k 100 FREQUENCY - Hz 10k 100k TPC 13. Positive PSR vs. Frequency G=1 80 60 40 TA = 25C VS = 15V VS = 1V 20 1 1k VOLTAGE NOISE - nV/ Hz 50 40 30 20 10 1k 100 FREQUENCY - Hz 10k 100k 1 10 1k 100 FREQUENCY - Hz 10k TPC 16. Voltage Noise Density vs. Frequency 100k 100 10 1 80 1 100 10 VOLTAGE GAIN - G 1k TA = 25C VS = 15V RL = 600 VOUT = 20V p-p 0.100 G = 100 0.010 G=1 G = 10 1k 100 FREQUENCY - Hz 10k TPC 15. Total Harmonic Distortion vs. Frequency 100mV 10 0 90 0.01 10 TA = 25C VS = 15V f = 1kHz TA = 25C VS = 15V G = 1000 60 G = 100 G = 10 100 TPC 14. Negative PSR vs. Frequency 70 VOLTAGE NOISE DENSITY - nV/ Hz 120 0 100 1s NOISE VOLTAGE - 200nV/DIV POWER SUPPLY REJECTION - dB 120 110 1.000 G = 1000 G = 100 120 TPC 12. Common-Mode Rejection vs. Voltage Gain 140 G = 1000 TA = 25C VS = 15V 130 70 100k TPC 11. Common-Mode Rejection vs. Frequency 140 0 10k TOTAL HARMONIC DISTORTION - % VOLTAGE GAIN - dB 60 COMMON-MODE REJECTION - dB G = 1000 140 140 TA = 25C VS = 15V COMMON-MODE REJECTION - dB 80 1 100 10 VOLTAGE GAIN - G TPC 17. RTI Voltage Noise Density vs. Gain -6- 1k TIME - S TPC 18. 0.1 Hz to 10 Hz Noise AV = 1000 REV. E AMP02 20 15 10 14 5 TA = 25C VS = 15V 100 I OUT = 20mA p-p 12 10 8 6 4 1k 10k 100k FREQUENCY - Hz 0 10 1M 7 7 SLEW RATE - Vs 8 6 TA = -25C, +25C, +85C 5 1k 10k 100 LOAD RESISTANCE - 100k TPC 20. Maximum Output Voltage vs. Load Resistance 8 4 3 VS = 15V TA = -40C, +25C, +85C 6 5 4 3 2 0 10 5 15 SUPPLY VOLTAGE - V TPC 22. Supply Current vs. Supply Voltage REV. E 20 1 80 60 40 20 0 2 TPC 19. Maximum Output Swing vs. Frequency 1 120 TA = 25C VS = 15V OUTPUT IMPEDANCE - 25 0 100 SUPPLY CURRENT - mA 16 TA = 25C VS = 15V RL = 1k OUTPUT VOLTAGE - V PEAK- TO-PEAK AMPLITUDE - V 30 1 100 10 VOLTAGE GAIN - G TPC 23. Slew Rate vs. Voltage Gain -7- 1k -20 100 1k 100k 10k FREQUENCY - Hz 1M TPC 21. Closed Loop Output Impedance vs. Frequency 10M AMP02 The voltage gain can range from 1 to 10,000. A gain set resistor is not required for unity-gain applications. Metal-film or wirewound resistors are recommended for best results. APPLICATIONS INFORMATION Input and Output Offset Voltages Instrumentation amplifiers have independent offset voltages associated with the input and output stages. The input offset component is directly multiplied by the amplifier gain, whereas output offset is independent of gain. Therefore at low gain, output-offset errors dominate while at high gain, input-offset errors dominate. Overall offset voltage, VOS, referred to the output (RTO) is calculated as follows: The total gain accuracy of the AMP02 is determined by the tolerance of the external gain set resistor, RG, combined with the gain equation accuracy of the AMP02. Total gain drift combines the mismatch of the external gain set resistor drift with that of the internal resistors (20 ppm/C typ). Maximum gain drift of the AMP02 independent of the external gain set resistor is 50 ppm/C. VOS ( RTO ) = (VIOS x G ) + VOOS All instrumentation amplifiers require attention to layout so thermocouple effects are minimized. Thermocouples formed between copper and dissimilar metals can easily destroy the TCVOS performance of the AMP02, which is typically 0.5 V/C. Resistors themselves can generate thermoelectric EMFs when mounted parallel to a thermal gradient. where VIOS and VOOS are the input and output offset voltage specifications and G is the amplifier gain. The overall offset voltage drift TCVOS, referred to the output, is a combination of input and output drift specifications. Input offset voltage drift is multiplied by the amplifier gain, G, and summed with the output offset drift: The AMP02 uses the triple op amp instrumentation amplifier configuration with the input stage consisting of two transimpedance amplifiers followed by a unity-gain differential amplifier. The input stage and output buffer are laser-trimmed to increase gain accuracy. The AMP02 maintains wide bandwidth at all gains as shown in Figure 3. For voltage gains greater than 10, the bandwidth is over 200 kHz. At unity gain, the bandwidth of the AMP02 exceeds 1 MHz. TCVOS ( RTO ) = (TCVIOS x G ) + TCVOOS where TCVIOS is the input offset voltage drift, and TCVOOS is the output offset voltage drift. Frequently, the amplifier drift is referred back to the input (RTI), which is then equivalent to an input signal change: TCVOS ( RTI ) = TCVIOS + TCVOOS G 80 For example, the maximum input-referred drift of an AMP02EP set to G = 1000 becomes: VOLTAGE GAIN - dB TCVOS ( RTI ) = 2 V oC + 60 100 V oC = 2.1 V oC 1000 Input Bias and Offset Currents Input transistor bias currents are additional error sources that can degrade the input signal. Bias currents flowing through the signal source resistance appear as an additional offset voltage. Equal source resistance on both inputs of an IA will minimize offset changes due to bias current variations with signal voltage and temperature; however, the difference between the two bias currents (the input offset current) produces an error. The magnitude of the error is the offset current times the source resistance. 0 G = 100 G = 10 G=1 -40 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 3. The AMP02 Keeps Its Bandwidth at High Gains Common-Mode Rejection Ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects common-mode voltages and noise. In practice, there is a small change in output voltage when both inputs experience the same common-mode voltage change; the ratio of these voltages is called the common-mode gain. Common-mode rejection (CMR) is the logarithm of the ratio of differential-mode gain to common-mode gain, expressed in dB. Laser trimming is used to achieve the high CMR of the AMP02. Gain The AMP02 only requires a single external resistor to set the voltage gain. The voltage gain, G, is: 50 k +1 RG and RG = 20 G = 1000 -20 A current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. Floating inputs such as thermocouples should be grounded close to the signal source for best common-mode rejection. G= 40 TA = 25C VS = 15V 50 k G -1 -8- REV. E AMP02 3 +IN 8 RG2 V1 25k 25k R 25k RG RG1 1 SENSE (SOIC-16 ONLY) 6 OUT R 25k 25k -IN 2 25k 5 REFERENCE V2 Figure 4. Triple Op Amp Topology Figure 4 shows the triple op amp configuration of the AMP02. With all instrumentation amplifiers of this type, it is critical not to exceed the dynamic range of the input amplifiers. The amplified differential input signal and the input common-mode voltage must not force the amplifier's output voltage beyond 12 V (VS = 15 V) or nonlinear operation will result. Grounding The majority of instruments and data acquisition systems have separate grounds for analog and digital signals. Analog ground may also be divided into two or more grounds that will be tied together at one point, usually at the analog power supply ground. In addition, the digital and analog grounds may be joined--normally at the analog ground pin on the A/D converter. Following this basic practice is essential for good circuit performance. The input stage amplifier's output voltages at V1 and V2 equal: 2R VD V1 = - 1 + + VCM RG 2 = -G Mixing grounds causes interactions between digital circuits and the analog signals. Since the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. Using separate ground returns minimizes the current flow in the sensitive analog return path to the system ground point. Consequently, noisy ground currents from logic gates interact with the analog signals. VD + VCM 2 2R VD V2 = 1 + + VCM RG 2 =G Inevitably, two or more circuits will be joined together with their grounds at differential potentials. In these situations, the differential input of an instrumentation amplifier, with its high CMR, can accurately transfer analog information from one circuit to another. VD + VCM 2 Sense and Reference Terminals where: VD The sense terminal completes the feedback path for the instrumentation amplifier output stage and is internally connected directly to the output. For SOIC devices, connect the sense terminal to the output. The output signal is specified with respect to the reference terminal, which is normally connected to analog ground. The reference may also be used for offset correction level shifting. A reference source resistance will reduce the common-mode rejection by the ratio of 25 k/RREF. If the reference source resistance is 1 , the CMR will be reduced 88 dB (25 k/1 = 88 dB). = Differential input voltage = (+IN) - (-IN) VCM = Common-mode input voltage G = Gain of instrumentation amplifier If V1 and V2 can equal 12 V maximum, the common-mode input voltage range is: GVD CMVR = 12 V - 2 REV. E -9- AMP02 Overvoltage Protection Power Supply Considerations Instrumentation amplifiers invariably sit at the front end of instrumentation systems where there is a high probability of exposure to overloads. Voltage transients, failure of a transducer, or removal of the amplifier power supply while the signal source is connected may destroy or degrade the performance of an unprotected device. A common technique is to place limiting resistors in series with each input, but this adds noise. The AMP02 includes internal protection circuitry that limits the input current to 4 mA for a 60 V differential overload (see Figure 5) with power off, 2.5 mA with power on. Achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. For example, supply noise and changes in the nominal voltage directly affect the input offset voltage. A PSR of 80 dB means that a change of 100 mV on the supply (not an uncommon value) will produce a 10 V input offset change. Consequently, care should be taken in choosing a power unit that has a low output noise level, good line and load regulation, and good temperature stability. In addition, each power supply should be properly bypassed. 4 LEAKAGE CURRENT - mA 3 TA = 25C VS = 15V POWER OFF 2 POWER ON 1 0 -1 -2 -3 -4 -100 -80 -60 -40 -20 0 20 40 60 80 100 DIFFERENTIAL INPUT VOLTAGE Figure 5. AMP02's Input Protection Circuitry Limits Input Current During Overvoltage Conditions -10- REV. E AMP02 OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) 8-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 8 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 5 0.310 (7.87) 0.220 (5.59) PIN 1 1 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.180 (4.57) MAX 0.055 (1.40) MAX 4 0.100 (2.54) BSC 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) MIN 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 0.060 (1.52) 0.015 (0.38) 0.023 (0.58) 0.014 (0.36) SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 16-Lead Standard Small Outline Package [SOIC] Wide Body (R-16) Dimensions shown in millimeters and (inches) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 8 1 0.51 (0.0201) 0.33 (0.0130) 0.75 (0.0295) 45 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.32 (0.0126) 0.23 (0.0091) 8 0 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. E 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX -11- AMP02 Revision History Location Page 1/03--Data Sheet changed from REV. D to REV. E. Edits to Die Characteristics .............................................................................................................................................................4 PRINTED IN U.S.A. Updated OUTLINE DIMENSIONS.............................................................................................................................................11 C00248-0-1/03(E) Edits to Figure 2 .............................................................................................................................................................................3 -12- REV. E