MBM2732-35 MBM2732-45 NOT RECOMMENDED FOR NEW DESIGNS. SEE PART NUMBER MBM2732A. FUJITSU MICROELECTRONICS UV ERASABLE 32,768-BIT READ ONLY MEMORY DESCRIPTION The Fujitsu MBM2732 is a high speed 32,768-bit static N-channel MOS erasable and electrically reprogrammable read only mem- ory (EPROM). It is especially well suited for applications where rapid turn-around and/or bit pat- tern experimentation are impor- tant. A 24-pin duat-in-line package with a transparent lid is used to package the MBM2732. The transparent lid allows the user to expose the device to ultraviolet light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be written into the memory. The MBM2732 is fabricated us- ing N-channel double polysilicon gate technology with single tran- sistor stacked gate cells. It is organized as 4096 words by 8-bits for use in microprocessor applications. Single +5V opera- tion greatly facilitates its use in systems. L CERDIP PACKAGE DIP-24C-C02 PIN ASSIGNMENT ad 7 2[Vce FEATURES AgLl2 23] ]Ag * 4096 words by 8-bits * Three-state output with AsL{3 22[ Ae organization, fully decoded OR:-tle capability Al 4 = 21 TAs * Simple programming * Output Enable (OE) pin for ass 3 we 20, 10EVpp requirements simplified ee P ace >} 5 19[ Ato * Single location expansion AL]? #28 isLIcE rogrammin prog 9 Fast access time: Aol {8 171108 Programs with one 50ms MBM2732-35 350ns 0,LC)9 16[]07 pulse MBM2732-45 450ns o2C}10 15[J05 * Low power requirement: O31 ry 825mW max (active) * Single +5V operation 3 144105 165mW max (standby) VssC]12 13} 104 No clocks required (fully static operation) TTL compatible inputs and outputs Standard 24-pin DIP package * Pin compatible with Intel 2732 This device contains circuitry to protect the inputs against damage due to high static valtages or electric fialds. However, it is ad- vised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high im- pedance circuit. 4-7MBM2732-35 / MBM2732-45 NOT RECOMMENDED FOR NEW DESIGNS. SEE PART NUMBER MBM2732A. Fig. 1 MBM2732 BLOCK DIAGRAM 0, Og OE_=| OUTPUT ENABLE & CHIP ENABLE guTeUR 53 - LOGIC Cr Do DATA INPUT ; BUFFER & ' PROGRAMMING CONTROL _+ , 0; Og fd Pp----+--4 A Yo COLUMN o COLUMN 1 GATING A DECODER 1 3 oT Yis { 256x128 A Xo CELL MATRIX 4 7 ROW T ' 1 Ay DECODER 1 X 255 Vpp(OE PIN) Vee Vss CAPACITANCE (Ta = 25C; f = 1MHz) Parameter Symbol Min Tyr Max Unit Input Capacitance (Except OE/Vpp, Vin = OV) CiNt 4 6 pF OE/Vpp Input Capacitance (Vin = OV) Cin2 _ 14 20 pF Output Capacitance (Vout = OV) Cout _ 8 12 pF 4-8NOT RECOMMENDED FOR NEW DESIGNS. SEE PART NUMBER MBM2732-35 / MBM2732-45 MBM2732A. ABSOLUTE MAXIMUM RATINGS (see Note) Rating Symbol Value Unit Temperature Under Bias Ta ~25 to +85 C Storage Temperature Tstg -65 to +125 C Inputs/Outputs (Except OE/Vpp) with Respect to Vss Vin. Vout ~0.3 to +7 Vv Output Enable/Program Input with Respect to Vss OEN pp 0.3 to +26.5 Vv Voc with Respect to Vgs Voc -0.3 to +7 v NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may aftect device reliability. FUNCTIONS AND PIN CONNECTIONS Vcci24) = +5, Vss(12) =.GND Function (Pin No.) Address lec Input Data VO cE OE/Vpp Supply Mode (1~8, 19,21 ~ 23) (9~11,13~17) - (18) (20) (24) Read AIN Dout - Vit Vit loca Stand By Don't Care High Z Vin Don't Care loc Program AIN Din ViL Vpp icc2 Program Verify Ain DouT - Vit Vit loca Program inhibit Don't Care High Z VIH Vpp loci RECOMMENDED OPERATING CONDITIONS (Referenced to Vsg = GND) Operating Parameter Symbol Min Typ Max Unit Temperature MBM2732-35 45 5.0 5.5 Supply Voltage(t) Voc Vv MBM2732-45 4.75 5.0 5.25 Supply Voltage Vss - GND _ Vv 0C to +70C Input High Voltage Vin 2.0 _ Voc +1 Vv Input Low Voltage Vic -0.1 _ 0.8 v Note: (1) Voc must be applied either before or coincident with Vpp and removed either after or coincident with Vpp. DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Parameter Symbol Min Typ Max Unit Input Load Current (Vij = 5.5V) Iu - _ 10 pA Output Leakage Current (Vout = 5.5V) lLo - _ 10 nA Vcc Supply Current (Standby) loc1 _ _- 30 mA Vec Supply Current (Active) icc2 _ - 150 mA Output Low Voltage (Io_ = 2.1mA) VoL - - 0.45 v Output High Voltage (lo = 400,A) VoH 2.4 - - v 4-9NOT RECOMMENDED FOR NEW MBM2732-35 / MBM2732-45 DESIGNS. SEE PART NUMBER MBM2732A. Fig. 2 AC TEST CONDITIONS (including Programming) Input Pulse Levels: 0.8V to 2.2V Input Rise and Fall Time: x 20ns { 4.0V and 2.0V for inputs c Timing Measurement Reference Levels: L 0.8V and 2.0V for outputs Output Load: 1 TTL gate and C_ = 100pF = AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) MBM2732-35 MBM2732-45 Parameter Symbol Unit Min Typ Max Min Typ Max Address to Output Delay tacc _ - 350 - - 450 ns Chip Enable to Output Delay tce -_ - 350 _ _ 450 ns Output Enable to Output Delay toe - - 120 - _- 120 ns Address to Output Hold tou 0 - - 0 _ _ ns Output Enable High to Output Float tor 0 _ 100 0 - 100 ns READ OPERATION TIMING DIAGRAM ADDRESSES & ADDRESSES kK VALID CE tcE| _ OE Toe (1) {ae tacc 1) OUTPUT HIGH Z AA Note: (1) OE may be delayed up to tacc - toe after the falling edge of CE without impact on tacc- (2) tor is specified from OE or CE, whichever occurs first. 4-40NOT RECOMMENDED FOR NEW DESIGNS. SEE PART NUMBER MBM2732A. PROGRAMMING/ ERASING INFORMATION Memory Cell Description The MBM2732 is fabricated using a single-transistor stacked gate cell construction, implemented via double-layer polysilicon tech- nology. The individual cells con- sist of a bottom floating gate and atop select gate (see Fig. 14). The top gate is connected to the row decoder, while the floating gate is used for charge storage. The ceil is programmed by the injection of high energy electrons through the oxide and onto the floating gate. The presence of the charge on the floating gate causes a shift in the cell threshold (refer to Fig. 15). In the initial state the cell has a low threshold (VtH1) which will enable the transistor to be turned on when the ceil is selected (via the top select gate). Programming shifts the threshold to a higher level (VTHo), thus preventing the cell transistor from turning on when selected. The status of the ceil (i.e., whether programmed or not) can be determined by ex- amining its state at the sense threshold (VTHs), as indicated by the dotted line in Fig. 15. Programming Upon delivery from Fujitsu, or after each erasure (see Erasure section), the MBM2732 has all 32,768 bits in the 1, or high state. 0s are loaded into the MBM2732 through the procedure of programming. The program ode is entered when C25V is applied to the OE/Vpp pin. A 0.1pF capacitor between OE/Vpp and Vss is need- ed to prevent excessive voltage transients, which could damage the device. The address to be pro- grammed is applied to the proper address pins. 8-bit patterns are placed on the respective data out- put pins. The voltage levels should be standard TTL levels. When both the address and data are stable, a 50 msec, TTL low- level pulse is applied to the CE in- put to accomplish the programm- ing. MBM2732-35 / MBM2732-45 Fig. 14 MEMORY CELL SELECT GATE _ fem | | a FLOATING GATE q fsck Fig. 15 MEMORY CELL THRESHOLD SHIFT NOT PROGRAMMED aye CURRENT THROUGH CELL TRANSISTOR PROGRAMMED O" PROGRAM t I I I 1 I ( ' ERASE I ! I i L Vint VTHs VTHD {NOT PROGRAMMED) (SENSE THRESHOLD) (PROGRAMMED! SELECT GATE VOLTAGE (V) The procedure can be done manually, address by address, randomly, or automatically via the proper circuitry. All that is re- quired is that one 50 msec pro- gram pulse be applied for each address to be programmed. It is necessary that this program pulse width not exceed 55 msec. Therefore, applying a DC level to the CE input is prohibited-when programming. Erasure In order to clear all locations of their programmed contents, it is necessary to expose the MBM 2732 to an ultraviolet light source. A dosage of 15 W-second/cm2 is required to completely erase an MBM2732. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (A)) with inten- sity of 12000xWicm? for 15 to 20 minutes. The MBM2732 should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the MBM2732 and similar devices, will erase with light sources hav- ing wavelengths shorter than 4000A. Although erasure times will be much longer than with UV sources at 2537A, nevertheless the exposure to fluorescent light and sunlight will eventually erase the MBM2732, and exposure to them should be prevented to realize maximum system reliabil- ity. If used in such an environ- ment, the package window should be covered by an opaque label or substance.MBM2732-35 / MBM2732-45 PROGRAMMING/ ERASING INFORMATION (continued) NOT RECOMMENDED FOR NEW DESIGNS. SEE PART NUMBER MBM2732A. Dc Characteristics (Ta = 25C, Vocll) = 5V +5%, Vppl.2) = 25V + 1V, Vss = GND Parameter Symbol Min Typ Max Unit Input Leakage Current (Vin = 5.25V/0.45V) lu - - 10 BA Vep Supply Current During Programming Pulse (CE = Vi, OE/Vpp = Vpp) Ipp _ = 30 mA Voc Supply Current loc2 - - 150 mA Input Low Level Vie -0.1 _ 0.8 v Input High Level VIH 2.0 _ Voc +1 Vv Output Low Voltage During Verify (lot = 2.1MA) VoL - - 0.45 v Output High Voltage During Verify (lon = 400%A) Vou 2.4 _ Vv Note: (1) Voc must be applied either coincidently (2) Vpp must not be greater than 26 volts including oversh into socket when Vpp = 25 volts. Also, during CE = Vit, or before Vpp and removed either coincidently or after Vpp. oot. Permanent device damage may occur if the device is taken out or put Vpp must not be switched from Vii to 25 volts or vise-versa. AC Characteristics (Ta = 25C) Parameter Symbol Min Typ Max Unit Address Setup Time tas 2 _ Ss Output Enable Setup Time toes 2 _ = us Data Setup Time tps 2 - - us Address Hold Time tay 0 _ _ BS Output Enable Hold Time toEH 2 _ _ 2S Data Hold Time tpH 2 _ _ BS Chip Enable to Output Float Delay (OE = Vit) tor 0 _ 120 ns Chip Enable to Data Valid Time (CE = Vi_, OE/Vpp = Viv) tov _ 1 aS Program Pulse Width tpw 45 50 55 ms Program Pulse Rise Time tpRT 50 ns Vpp Recovery Time tvr 2 _ usDESIGNS. SEE SO UMBER MBM2732-35 / MBM2732-45 MBM2732A. PROGRAMMING WAVEFORMS No. 1 PROGRAM VERIFY | Vin ADDRESSES VALID ADDRESSES VIL L tan TAS DATA DATA IN STABLE our Vpp OE/Vpp tPRT Vit Vin CE Mit No. 2 Lg ROG RAM Vin y ADDRESSES x VALID ADDRESSES ,, VALID ADDRESSES, Vin N tas tau taH yo DATA _ DATA IN STABLE DATA IN STABLE RK tos tox tpH] Vpp _ OE/Vpp teRT h Vie toes tpw TPW =| toEH Vp} | ly - cE Vin Note: In PROGRAMMING WAVEFORMS No. 2, Address Hold Time ta, must be more than 2 ys.