ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold General Description Features The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 450 MHz. Operating on a single 3.3V power supply, this device consumes just 357 mW at 66 MSPS, including the reference current. The Power Down feature reduces power consumption to just 50 mW. The differential inputs provide a full scale input swing equal to VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary. This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of -40C to +85C. n n n n Single supply operation Low power consumption Power down mode On-chip reference buffer Key Specifications n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) Data Latency Supply Voltage Power Consumption, 66 MHz 12 Bits 66 MSPS 450 MHz 0.4 LSB(typ) 66 dB(typ) 80 dB(typ) 6 Clock Cycles +3.3V 300 mV 357 mW(typ) Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Base Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends Connection Diagram 20032801 (c) 2002 National Semiconductor Corporation DS200328 www.national.com ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold April 2002 ADC12L066 Ordering Information Industrial (-40C TA +85C) Package ADC12L066CIVY 32 Pin LQFP ADC12L066CIVYX 32 Pin LQFP Tape and Reel ADC12L066EVAL Evaluation Board Block Diagram 20032802 www.national.com 2 ADC12L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O VIN+ Non-Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. 3 VIN- Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. This pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. 1 VREF Reference input. This pin should be bypassed to AGND with a 0.1 F monolithic capacitor. VREF is 1.0V nominal and should be between 0.8V and 1.5V. 31 VRP 32 VRM 30 VRN 2 These pins are high impedance reference bypass pins only. Connect a 0.1 F capacitor from each of these pins to AGND. DO NOT connect anything else to these pins. DIGITAL I/O CLK Digital clock input. The range of frequencies for this input is 10 MHz to 80 MHz (typical) with guaranteed performance at 66 MHz. The input is sampled on the rising edge of this input. 11 OE OE is the output enable pin that, when low, enables the TRI-STATE data output pins. When this pin is high, the outputs are in a high impedance state. 8 PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 10 3 www.national.com ADC12L066 Pin Descriptions and Equivalent Circuits Pin No. Symbol 14-19, 22-27 D0-D11 Equivalent Circuit (Continued) Description Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 F monolithic capacitors located within 1 cm of these power pins, and with a 10 F capacitor. The ground return for the analog supply. DIGITAL POWER 13 VD 9, 12 DGND 21 20 www.national.com Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and bypassed to DGND with a 0.1 F monolithic capacitor in parallel with a 10 F capacitor, both located within 1 cm of the power pin. The ground return for the digital supply. VDR Positive digital supply pin for the ADC12L066's output drivers. This pin should be connected to a voltage source of +1.8V to VD and bypassed to DR GND with a 0.1 F monolithic capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 F tantalum capacitor. The voltage at this pin should never exceed the voltage on VD by more than 300 mV. All bypass capacitors should be located within 1 cm of the supply pin. DR GND The ground return for the digital supply for the ADC12L066's output drivers. This pin should be connected to the system digital ground, but not be connected in close proximity to the ADC12L066's DGND or AGND pins. See Section 5.0 (Layout and Grounding) for more details. 4 Soldering Temperature, Infrared, 10 sec. (Note 6) (Notes 1, 2) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VA, VD, VDR Supply Voltage (VA, VD) -0.3V to VA or VD +0.3V 25 mA 50 mA Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25C Output Driver Supply (VDR) +1.8V to VD VREF Input 0.8V to 1.5V -0.05V to VD + 0.05V VIN Input -0V to (VA - 0.5V) VCM ESD Susceptibility Machine Model (Note 5) +3.0V to +3.60V CLK, PD, OE See (Note 4) Human Body Model (Note 5) -40C TA +85C Operating Temperature 100 mV Voltage on Any Pin -65C to +150C Operating Ratings (Notes 1, 2) 4.2V |VA-VD| 235C 0.5V to VA -1.5V 100 mV |AGND-DGND| 2500V 250V Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) 12 Bits +2.7 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non Linearity (Note 11) DNL Differential Non Linearity 1.2 0.4 Positive Error GE Gain Error -0.15 Negative Error +0.4 Offset Error (VIN+ = VIN-) +0.2 -3 LSB (min) +1 LSB (max) -0.95 LSB (min) 3 %FS (max) +4 %FS (max) -5 %FS (min) 1.3 %FS (max) Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage CIN VIN Input Capacitance (each pin to GND) VREF VIN = 1.0 Vdc + 1 VP-P Reference Voltage (Note 13) Reference Input Resistance 5 V (min) 0.5 1.5 V (max) (CLK LOW) 8 pF (CLK HIGH) 7 pF 0.8 V (min) 1.5 V (max) 100 M (min) www.national.com ADC12L066 Absolute Maximum Ratings ADC12L066 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) 2.0 V (min) 0.8 V (max) CLK, PD, OE DIGITAL INPUT CHARACTERISTICS VIN(1) Logical "1" Input Voltage VD = 3.3V VIN(0) Logical "0" Input Voltage VD = 3.3V IIN(1) Logical "1" Input Current VIN+, VIN- = 3.3V 10 A IIN(0) Logical "0" Input Current VIN+, VIN- = 0V -10 A CIN Digital Input Capacitance 5 pF D0-D11 DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical "1" Output Voltage IOUT = -0.5 mA VDR - 0.18 V (min) VOUT(0) Logical "0" Output Voltage IOUT = 1.6 mA 0.4 V (max) IOZ TRI-STATE Output Current +ISC Output Short Circuit Source Current -ISC Output Short Circuit Sink Current VOUT = 2.5V VOUT = 3.3V 100 nA VOUT = 0V -100 nA VOUT = 0V -20 mA 20 mA POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = 1.0V PD Pin = VDR 103 4 139 mA (max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VDR 5.3 2 6.2 mA (max) mA IDR Digital Output Supply Current PD Pin = DGND, (Note 14) PD Pin = VDR <1 Total Power Consumption PD Pin = DGND, CL = 0 pF (Note 15) PD Pin = VDR 357 50 Power Supply Rejection Rejection of Full-Scale Error with VA = 3.0V vs 3.6V 58 PSRR1 mA mA 0 479 mW (max) mW dB DYNAMIC CONVERTER CHARACTERISTICS BW Full Power Bandwidth 0 dBFS Input, Output at -3 dB fIN = 10 MHz, Differential VIN = -0.5 dBFS 450 85C 25C -40C fIN = 25 MHz, Differential VIN = -0.5 dBFS SNR Signal-to-Noise Ratio fIN = 150 MHz, Differential VIN = -6 dBFS fIN = 240 Hz, Differential VIN = -6 dBFS www.national.com 6 66 MHz 64.6 dB(min) 65 dB(min) 64.6 dB(min) 65 85C 25C 55 -40C 52 dB 52 dB(min) 54 dB(min) 51 dB(min) dB (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions fIN = 10 MHz, Differential VIN = -0.5 dBFS 85C 25C fIN = 25 MHz, Differential VIN = -0.5 dBFS SINAD Signal-to-Noise & Distortion fIN = 150 MHz, Differential VIN = -6 dBFS 85C 25C Effective Number of Bits fIN = 150 MHz, Differential VIN = -6 dBFS 85C 25C Second Harmonic Distortion fIN = 150 MHz, Differential VIN = -6 dBFS fIN = 240 Hz, Differential VIN = -6 dBFS 7 dB(min) 64.8 dB(min) 63 dB(min) dB 51.8 dB(min) 53.9 dB(min) 50 dB(min) dB 10.3 10.7 -40C 10.5 85C 25C Bits 8.3 8.8 -40C 8.6 85C -80 -40C Bits -73 dB(max) -73 dB(max) -68 dB(max) -80 85C 25C Bits(min) 8.0 8.2 25C Bits(min) 10.2 10.3 fIN = 25 MHz, Differential VIN = -0.5 dBFS 2nd Harm 64.3 51 fIN = 240 Hz, Differential VIN = -6 dBFS fIN = 10 MHz, Differential VIN = -0.5 dBFS 55 -40C fIN = 25 MHz, Differential VIN = -0.5 dBFS ENOB Units (Limits) 64 fIN = 240 Hz, Differential VIN = -6 dBFS fIN = 10 MHz, Differential VIN = -0.5 dBFS 66 -40C Limits (Note 10) -81 -40C -61 dB -66 dB(max) -66 dB(max) -56 dB(max) dB www.national.com ADC12L066 DC and Logic Electrical Characteristics ADC12L066 DC and Logic Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions fIN = 10 MHz, Differential VIN = -0.5 dBFS 85C 25C fIN = 25 MHz, Differential VIN = -0.5 dBFS 3rd Harm Third Harmonic Distortion fIN = 150 MHz, Differential VIN = -6 dBFS 85C 25C Total Harmonic Distortion fIN = 150 MHz, Differential VIN = -6 dBFS 85C 25C Spurious Free Dynamic Range fIN = 150 MHz, Differential VIN = -6 dBFS fIN = 240 Hz, Differential VIN = -6 dBFS www.national.com 8 -77 -40C dB(max) -74 dB(max) -71 dB(max) dB -68 dB(max) -68 dB(max) -64 dB(max) dB -72 dB(max) -72 dB(max) -66 dB(max) -71 85C 25C -69 -40C dB -63 dB(max) -63 dB(max) -53 dB(max) -57 85C 25C dB 73 80 -40C fIN = 25 MHz, Differential VIN = -0.5 dBFS SFDR -74 -78 fIN = 240 Hz, Differential VIN = -6 dBFS fIN = 10 MHz, Differential VIN = -0.5 dBFS -78 -40C fIN = 25 MHz, Differential VIN = -0.5 dBFS THD Units (Limits) -79 fIN = 240 Hz, Differential VIN = -6 dBFS fIN = 10 MHz, Differential VIN = -0.5 dBFS -84 -40C Limits (Note 10) 73 73 85C 25C dB(min) 68 dB 66 74 -40C 66 dB(min) 56 61 dB Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25C (Notes 7, 8, 9, 10, 12) Symbol Typical (Note 10) Limits (Note 10) Units (Limits) Maximum Clock Frequency 80 66 MHz(min) Minimum Clock Frequency 1 Parameter Conditions Clock Duty Cycle MHz 40 %(min) 60 %(max) tCH Clock High Time 6.5 ns(min) tCL Clock Low Time 6.5 ns(min) tCONV Conversion Latency tOD Data Output Delay after Rising CLK Edge tAD Aperture Delay 2 ns tAJ Aperture Jitter 1.2 ps rms tDIS Data outputs into TRI-STATE Mode 10 ns tEN Data Outputs Active after TRI-STATE 10 ns tPD Power Down Mode Exit Cycle 20 tCLK 6 Clock Cycles VDR = 2.5V 7.5 11 ns (max) VDR = 3.3V 6.7 10.5 ns(max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA, VD or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/JA. In the 32-pin LQFP, JA is 79C/W, so PDMAX = 1,582 mW at 25C and 823 mW at the maximum operating ambient temperature of 85C. Note that the power consumption of this device under normal operation will typically be about 612 mW (357 typical power consumption + 255 mW output loading with 250 MHz input). The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0. Note 6: The 235C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220C. Only one excursion above 183C is allowed per reflow cycle. Note 7: The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be 3.4V to ensure accurate conversions. 20032807 Note 8: To guarantee accuracy, it is required that |VA-VD| 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2 VP-P differential input), the 12-bit LSB is 488 V. Note 10: Typical figures are at TA = TJ = 25C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. 9 www.national.com ADC12L066 AC Electrical Characteristics ADC12L066 AC Electrical Characteristics (Continued) Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2 bandgap voltage reference is recommended for this application. Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR =VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 15: Power consumption excludes output driver power. See (Note 14). PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 112 LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12L066, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the dc power supply voltage, expressed in dB. PSRR2 is a measure of how well an a. c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error - Offset Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (12 LSB below the first code transition) through positive full scale (12 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12L066 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ - VIN-) just causing a transition from negative full scale to the first code and its ideal value of 0.5 LSB. OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. www.national.com where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power in the first 9 harmonic frequencies. Second Harmonic Distortion (2nd Harm) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 10 ADC12L066 Timing Diagram 20032809 Output Timing Transfer Characteristic 20032810 FIGURE 1. Transfer Characteristic 11 www.national.com ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. DNL DNL vs. fCLK 200328E6 20032891 DNL vs. Clock Duty Cycle DNL vs. Temperature 20032892 20032893 INL INL vs. fCLK 200328E7 www.national.com 20032894 12 VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) INL vs. Clock Duty Cycle INL vs. Temperature 20032895 20032896 SNR vs. VA SNR vs. VDR 20032897 20032898 SNR vs. VCM SNR vs. fCLK 200328B1 200328B2 13 www.national.com ADC12L066 Typical Performance Characteristics ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SNR vs. Clock Duty Cycle SNR vs. VREF 200328B3 200328B4 SNR vs. Temperature THD vs. VA 200328B5 200328B6 THD vs. VDR THD vs. VCM 200328B7 www.national.com 200328B8 14 VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) THD vs. fCLK THD vs. Clock Duty Cycle 200328C1 200328B9 THD vs. VREF THD vs. Temperature 200328C3 200328C2 SINAD vs. VA SINAD vs. VDR 200328C4 200328C5 15 www.national.com ADC12L066 Typical Performance Characteristics ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SINAD vs. VCM SINAD vs. fCLK 200328C6 200328C7 SINAD vs. Clock Duty Cycle SINAD vs. VREF 200328C8 200328C9 SINAD vs. Temperature SFDR vs. VA 200328D1 www.national.com 200328D2 16 VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) SFDR vs. VDR SFDR vs. VCM 200328D3 200328D4 SFDR vs. fCLK SFDR vs. Clock Duty Cycle 200328D6 200328D5 SFDR vs. VREF SFDR vs. Temperature 200328D8 200328D7 17 www.national.com ADC12L066 Typical Performance Characteristics ADC12L066 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) Power Consumption vs. fCLK tOD vs. VDR 200328D9 200328E1 Spectral Response @ 10 MHz Input Spectral Response @ 25 MHz Input 200328E4 200328E8 Spectral Response @ 50 MHz Input Spectral Response @ 75MHz Input 200328E9 www.national.com 200328J0 18 VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF = 1.0V, unless otherwise stated. (Continued) Spectral Response @ 100 MHz Input Spectral Response @ 150 MHz Input 200328J1 200328J2 Spectral Response @ 240 MHz Input 200328E5 19 www.national.com ADC12L066 Typical Performance Characteristics ADC12L066 1.2 REFERENCE PINS Functional Description The ADC12L066 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range of 0.8V to 1.5V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12L066. Increasing the reference voltage (and the input signal swing) beyond 1.5V will degrade THD for a full-scale input. It is very important that all grounds associated with the reference voltage and the input signal make connection to the analog ground plane at a single point to minimize the effects of noise currents in the ground path. The three Reference Bypass Pins (VRP, VRM and VRN) are made available for bypass purposes only. These pins should each be bypassed to ground with a 0.1 F capacitor. DO NOT LOAD these pins. Operating on a single +3.3V supply, the ADC12L066 uses a pipelined architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 12 bits. Each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, VREF, be centered around VREF/2 and be 180 out of phase with each other. Table 1 and Table 2 indicate the input to output relationship of the ADC12L066. Biasing one input to VREF/2 and driving the other input with its full range signal results in a 6 dB reduction of the output range, limiting it to the range of 14 to 34 of the minimum output range obtainable if both inputs were driven with complimentary signals. Section 1.3 explains how to avoid this signal reduction. 1.3 SIGNAL INPUTS The signal inputs are VIN+ and VIN-. The input signal, VIN, is defined as VIN = (VIN+) - (VIN-) TABLE 1. Input to Output Relationship -- Differential Input VIN+ VIN- Output VCM -0.5* VREF VCM +0.5* VREF 0000 0000 0000 VCM -0.25* VREF VCM +0.25* VREF 0100 0000 0000 VCM VCM 1000 0000 0000 VCM +0.25* VREF VCM -0.25* VREF 1100 0000 0000 VCM +0.5* VREF VCM -0.5* VREF 1111 1111 1111 Figure 2 shows the expected input signal range. Note that the nominal input common mode voltage is VREF/2 and the nominal input signals each run between the limits of AGND and VREF. The Peaks of the input signals should never exceed the voltage described as Peak Input Voltaged = VA - 1.0 to maintain dynamic performance. TABLE 2. Input to Output Relationship -- Single-Ended Input VIN+ VIN- Output VCM -VREF VCM 0000 0000 0000 VCM -0.5* VREF VCM 0100 0000 0000 VCM VCM 1000 0000 0000 VCM +0.5* VREF VCM 1100 0000 0000 VCM +VREF VCM 1111 1111 1111 The output word rate is the same as the clock frequency, which can be between 10 MSPS and 80 MSPS (typical). The analog input voltage is acquired at the rising edge of the clock and the digital data for that sample is delayed by the pipeline for 6 clock cycles. A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW. 20032811 FIGURE 2. Expected Input Signal Range The ADC12L066 performs best with a differential input with each input centered around VCM (minimum of 0.5V). The peak-to-peak voltage swing at both VIN+ and VIN- should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180 out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion. For angular deviations of up to 10 degrees from these two signals being 180 out of phase, the full scale error in LSB can be described as approximately EFS = dev1.79 Applications Information 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12L066: 3.0 V VA 3.6V VD = VA 1.8V VDR VD 10 MHz fCLK 80 MHz 0.8V VREF 1.5V Where dev is the angular difference between the two signals having a 180 relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100. 1.1 ANALOG INPUTS The ADC12L066 has two analog signal inputs, VIN+ and VIN-. These two pins form a differential input pair. There is one reference input pin, VREF. www.national.com 20 The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12L066 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 40% to 60%. (Continued) The clock line should be series terminated at the clock source in the characteristic impedance of that line. If the clock line is longer than 20032812 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion where tr is the clock rise time and tprop is the propagation rate of the signal along the trace, the CLOCK pin should be a.c. terminated with a series RC such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, VREF, and be centered around VCM. For single ended operation, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input. The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 1.0V, bias VIN- to 1.0V and drive VIN+ with a signal range of 0V to 2.0V. Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage while maintaining a full-range output. Tables 1, 2 indicate the input to output relationship of the ADC12L066. The VIN+ and the VIN- inputs of the ADC12L066 consist of an analog switch followed by a switched-capacitor amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when the clock is low, and 7 pF when the clock is high. Although this difference is small, a dynamic capacitance is more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. LMH6702, LMH6628, LMH6622, LMH6655 are good amplifiers for driving the ADC12L066. The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use 18 series resistors at each of the signal inputs with a 10 pF capacitor across the inputs, as can be seen in Figure 5 and Figure 6. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The 10 pF capacitor value is for undersampling application and should be replaced with a 68 pF capacitor for Nyquist application. where 'I' is the line length in inches and Zo is the characteric impedance of the clock line. This termination should be located as close as possible to, but within one centimeter of, the ADC12L066 clock pin as shown in Figure 4. 2.2 OE The OE pin, when high, puts the output pins into a high impedance state. When this pin is low the outputs are in the active state. The ADC12L066 will continue to convert whether this pin is high or low, but the output can not be read while the OE pin is high. The OE pin should NOT be used to multiplex devices together to drive a common bus as this will result in excessive capacitance on the data output pins, reducing SNR and SINAD performance of the converter. See Section 3.0. 2.3 PD The PD pin, when high, holds the ADC12L066 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 50 mW. The output data pins are undefined in this mode. Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock signal present. The data in the pipeline is corrupted while in the power down mode. 3.0 OUTPUTS The ADC12L066 has 12 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the OE and PD pins are low. While the tOD time provides information about output timing, a simple way to capture a valid output is to latch the data on the rising edge of the conversion clock (pin 10). Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, 2.0 DIGITAL INPUTS Digital inputs consist of CLK, OE and PD. 2.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 10 MHz to 80 MHz with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 10 MSPS. 21 www.national.com ADC12L066 Applications Information ADC12L066 Applications Information connected to each output pin. Additionally, inserting series resistors of 47 to 56 at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. (Continued) bus capacitance beyond the specified 20 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. While the ADC12L066 will operate with VDR voltages down to 1.8V, tOD increases with reduced VDR. Be careful of external timing when using reduced VDR. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry (74ACQ541, for example). Only one driven input should be 20032813 FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer www.national.com 22 ADC12L066 Applications Information (Continued) 20032814 FIGURE 5. Differential Drive Circuit of Figure 4 20032815 FIGURE 6. Driving the Signal Inputs with a Transformer 23 www.national.com ADC12L066 Applications Information exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12L066's other ground pins. (Continued) 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 F capacitor and with a 0.1 F ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series inductance. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. The effects of the noise generated from the ADC output switching can be minimized through the use of 47 to 56 resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. As is the case with all high-speed converters, the ADC12L066 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 1.8V to VD. This can simplify interfacing to devices and systems operating with supplies less than VD. DO NOT operate the VDR pin at a voltage higher than VD. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12L066 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can 20032816 FIGURE 7. Example of a Suitable Layout other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in Generally, analog and digital lines should cross each other at 90 to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90 crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because www.national.com 24 exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 50 to 100 in series with any offending digital input, close to the signal source, will eliminate the problem. (Continued) which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Be careful not to overdrive the inputs of the ADC12L066 with a device that is powered from supplies outside the range of the ADC12L066 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond the specified 20 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be a reduction in dynamic performance. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12L066, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 47 to 56. Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor across the analog inputs (as shown in Figures 5, 6) will improve performance. The LMH6702, LMH6628, LMH6622 and LMH6655 have been successfully used to drive the analog inputs of the ADC12L066. Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, VREF should be in the range of 0.8V VREF 1.5V Figure 7 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be placed in the digital area of the board. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single point. All ground connections should have a low inductance path to ground. 6.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 8. As mentioned in Section 5.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90 crossings have capacitive coupling, so try to avoid even these 90 crossings of the clock line. 20032817 FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to Operating outside of these limits could lead to performance degradation. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. 25 www.national.com ADC12L066 Applications Information ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC12L066CIVY NS Package Number VBE32A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.