Device Operating
Temperature Range Package

SEMICONDUCTOR
TECHNICAL DATA
HIGH VOLTAGE
OFF–LINE
SWITCHING REGULATOR
ORDERING INFORMATION
MC33363BDW TJ = –25° to +125°CSOP–16L
P SUFFIX
PLASTIC PACKAGE
CASE 648E
(DIP–16)
16
1
116
13
12
11
10
9
3
4
5
6
7
8
(Top View)
Startup Input
VCC
Gnd
RT
CT
Regulator Output
Power Switch
Drain
Gnd
Compensation
PIN CONNECTIONS
Order this document by MC33363B/D
Overvoltage
Protection Input
Voltage Feedback
Input
DW SUFFIX
PLASTIC PACKAGE
CASE 751N
(SOP–16L)
16
1
MC33363BP DIP–16
1
MOTOROLA ANALOG IC DEVICE DATA
  

The MC33363B is a monolithic high voltage switching regulator that is
specifically designed to operate from a rectified 240 Vac line source. This
integrated circuit features an on–chip 700 V/1.0 A SenseFET power switch,
450 V active off–line startup FET, duty cycle controlled oscillator, current
limiting comparator with a programmable threshold and leading edge
blanking, latching pulse width modulator for double pulse suppression, high
gain error amplifier, and a trimmed internal bandgap reference. Protective
features include cycle–by–cycle current limiting, input undervoltage lockout
with hysteresis, overvoltage protection, and thermal shutdown. This device
is available in a 16–lead dual–in–line and wide body surface mount
packages.
•On–Chip 700 V, 1.0 A SenseFET Power Switch
•Rectified 240 Vac Line Source Operation
•On–Chip 450 V Active Off–Line Startup FET
•Latching PWM for Double Pulse Suppression
•Cycle–By–Cycle Current Limiting
•Input Undervoltage Lockout with Hysteresis
•Over–Voltage Protection
•Trimmed Internal Bandgap Reference
•Internal Thermal Shutdown
Simplified Application
Startup
Reg
Osc
Thermal
LEB
PWM
DC Output
Startup Input
Gnd 4, 5, 12, 13
Mirror
7
AC Input
Regulator
Output
6
8
CT
RTPWM Latch
EA
Ipk
VCC
3
11
16
9
10
1
Compensation
Voltage
Feedback
Input
Power Switch
Drain
Overvoltage
Protection
Input
Driver
OVP
UVLO
S
RQ
Motorola, Inc. 1999 Rev 1
MC33363B
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Switch (Pin 16)
Drain Voltage
Drain Current
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
VDS
IDS
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
700
1.0
ÁÁÁ
Á
Á
Á
ÁÁÁ
V
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Startup Input Voltage (Pin 1, Note 1)
Pin 3 = Gnd
Pin 3 ≤ 1000 µF to ground
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
Vin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
400
500
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage (Pin 3)
ÁÁÁÁ
ÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
40
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
VIR
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
–1.0 to V reg
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Thermal Characteristics
P Suffix, Dual–In–Line Case 648E
Thermal Resistance, Junction–to–Air
Thermal Resistance, Junction–to–Case
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
RθJA
RθJC
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
80
15
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
°C/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DW Suffix, Surface Mount Case 751G
Thermal Resistance, Junction–to–Air
Thermal Resistance, Junction–to–Case
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RθJA
RθJC
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
95
15
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Operating Junction Temperature
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁ
ÁÁÁÁÁ
–25 to +150
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Storage Temperature
ÁÁÁÁ
ÁÁÁÁ
Tstg
ÁÁÁÁÁ
ÁÁÁÁÁ
–55 to +150
ÁÁÁ
ÁÁÁ
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
REGULATOR (Pin 8)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Voltage (IO = 0 mA, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
Vreg
ÁÁÁÁ
ÁÁÁÁ
5.5
ÁÁÁÁ
ÁÁÁÁ
6.5
ÁÁÁÁ
ÁÁÁÁ
7.5
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Line Regulation (VCC = 20 V to 40 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regline
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
30
ÁÁÁÁ
ÁÁÁÁ
500
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Load Regulation (IO = 0 mA to 10 mA)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regload
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
44
ÁÁÁÁ
ÁÁÁÁ
200
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Total Output Variation over Line, Load, and Temperature
ÁÁÁÁÁ
ÁÁÁÁÁ
Vreg
ÁÁÁÁ
ÁÁÁÁ
5.3
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
8.0
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OSCILLATOR (Pin 7)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Frequency
CT = 390 pF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
CT = 2.0 nF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
fOSC
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
260
255
60
59
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
285
–
67.5
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
310
315
75
76
ÁÁ
ÁÁ
ÁÁ
ÁÁ
kHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Frequency Change with Voltage (VCC = 20 V to 40 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
∆fOSC/∆V
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
0.1
ÁÁÁÁ
ÁÁÁÁ
2.0
kHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ERROR AMPLIFIER (Pins 9, 10)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Voltage Feedback Input Threshold
ÁÁÁÁÁ
ÁÁÁÁÁ
VFB
ÁÁÁÁ
ÁÁÁÁ
2.52
ÁÁÁÁ
ÁÁÁÁ
2.6
ÁÁÁÁ
ÁÁÁÁ
2.68
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regline
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
0.6
ÁÁÁÁ
ÁÁÁÁ
5.0
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Bias Current (VFB = 2.6 V, TJ = 0 – 125°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
IIB
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
20
ÁÁÁÁ
ÁÁÁÁ
500
nA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Open Loop Voltage Gain (TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
AVOL
ÁÁÁÁ
ÁÁÁÁ
70
ÁÁÁÁ
ÁÁÁÁ
82
ÁÁÁÁ
ÁÁÁÁ
94
dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
GBW
ÁÁÁÁ
ÁÁÁÁ
0.85
ÁÁÁÁ
ÁÁÁÁ
1.0
ÁÁÁÁ
ÁÁÁÁ
1.15
MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Voltage Swing
High State (ISource = 100 µA, VFB < 2.0 V)
Low State (ISink = 100 µA, VFB > 3.0 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VOH
VOL
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
4.0
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
5.3
0.2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
0.35
ÁÁ
V
NOTES: 1.Maximum power dissipation limits must be observed.
2.Tested junction temperature range for the MC33363B:
Tlow = –25°CT
high = +125°C
MC33363B
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted.)
Characteristic UnitMaxTypMinSymbol
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OVERVOLTAGE DETECTION (Pin 11)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Threshold Voltage
ÁÁÁÁÁ
ÁÁÁÁÁ
Vth
ÁÁÁÁ
ÁÁÁÁ
2.47
ÁÁÁÁ
ÁÁÁÁ
2.6
ÁÁÁÁ
ÁÁÁÁ
2.73
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Bias Current (Vin = 2.6 V, TJ = –25 – 125°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
IIB
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
100
ÁÁÁÁ
ÁÁÁÁ
500
nA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PWM COMPARATOR (Pins 7, 9)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
DC(max)
DC(min)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
48
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
50
0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
52
0
ÁÁ
%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
POWER SWITCH (Pin 16)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Drain–Source On–State Resistance (ID = 200 mA)
TJ = 25°C
TJ = Tlow to Thigh
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RDS(on)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
15
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
17
39
ÁÁ
Ω
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Drain–Source Off–State Leakage Current
VDS = 650 V
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ID(off)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
0.2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
100
ÁÁ
µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rise T ime
ÁÁÁÁÁ
ÁÁÁÁÁ
tr
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁ
ÁÁÁÁ
–
ns
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Fall T ime
ÁÁÁÁÁ
ÁÁÁÁÁ
tf
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁ
ÁÁÁÁ
–
ns
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OVERCURRENT COMPARATOR (Pin 16)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Current Limit Threshold (RT = 10 k)
ÁÁÁÁÁ
ÁÁÁÁÁ
Ilim
ÁÁÁÁ
ÁÁÁÁ
0.5
ÁÁÁÁ
ÁÁÁÁ
0.72
ÁÁÁÁ
ÁÁÁÁ
0.9
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
STARTUP CONTROL (Pin 1)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Peak Startup Current (Vin = 400 V) (Note 3)
VCC = 0 V
VCC = (Vth(on) – 0.2 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Istart
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
2.0
2.0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
4.0
4.0
ÁÁ
mA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Off–State Leakage Current (V in = 50 V, VCC = 20 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
ID(off)
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁÁ
ÁÁÁÁ
200
µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
UNDERVOLTAGE LOCKOUT (Pin 3)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Startup Threshold (VCC Increasing)
ÁÁÁÁÁ
ÁÁÁÁÁ
Vth(on)
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁ
ÁÁÁÁ
15.2
ÁÁÁÁ
ÁÁÁÁ
18
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Minimum Operating Voltage After T urn–On
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC(min)
ÁÁÁÁ
ÁÁÁÁ
7.5
ÁÁÁÁ
ÁÁÁÁ
9.5
ÁÁÁÁ
ÁÁÁÁ
11.5
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TOTAL DEVICE (Pin 3)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ICC
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
0.25
3.2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
0.5
5.0
ÁÁ
mA
NOTES: 3. The device can only guarantee to start up at high temperature below +115°C.
7.0
1.0 M
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 1. Oscillator Frequency
versus Timing Resistor
RT, TIMING RESISTOR (k
Ω
)
Figure 2. Power Switch Peak Drain Current
versus Timing Resistor
500 k
200 k
100 k
50 k
20 k
10 k 10 15 20 30 50
VCC = 20 V
TA = 25
°
C
CT = 100 pF
CT = 200 pF
CT = 500 pF
CT = 1.0 nF
CT = 2.0 nF
CT = 5.0 nF
CT = 10 nF 70
VCC = 20 V
CT = 1.0
µ
F
TA = 25
°
C
Inductor supply voltage and inductance value are
adjusted so that Ipk turn–off is achieved at 5.0
µ
s.
RT, TIMING RESISTOR (k
Ω
)
0.1
IPK, POWER SWITCH PEAK DRAIN CURRENT (A)
0.8
0.6
0.4
0.2
0.15
7.0 10 15 20 30 40 7050
0.3
1.0
MC33363B
4MOTOROLA ANALOG IC DEVICE DATA
0
0
1.0
70
1.80 V
10
100
7.0
0.8
0.5 V/DIV
1.0
µ
s/DIV
Vsat, OUTPUT SATURATION VOLTAGE (V)
IO, OUTPUT LOAD CURRENT (mA)
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
TIMING RESISTOR RATIO
20 mV/DIV
1.0
µ
s/DIV
VCC = 20 V
AV = –1.0
CL = 10 pF
TA = 25
°
C
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
f, FREQUENCY (Hz)
Ichg , OSCILLATOR
Figure 3. Oscillator Charge/Discharge
Current versus Timing Resistor
RT, TIMING RESISTOR (k
Ω
)
Figure 4. Maximum Output Duty Cycle
versus Timing Resistor Ratio
Figure 5. Error Amp Open Loop Gain and
Phase versus Frequency Figure 6. Error Amp Output Saturation
Voltage versus Load Current
Figure 7. Error Amplifier Small Signal
Transient Response Figure 8. Error Amplifier Large Signal
Transient Response
/Idscg
CHARGE/DISCHARGE CURRENT (mA)
θ
, EXCESS PHASE (DEGREES)
VCC = 20 V
AV = –1.0
CL = 10 pF
TA = 25
°
C
1.75 V
1.70 V
3.00 V
1.75 V
0.50 V
0.5
0.3
0.2
0.15
0.1
0.08
80
60
40
20
0
–20
60
50
40
30
–1.0
– 2.0
2.0
1.0
0
10 15 20 30 70 2.0 3.0 5.0 7.0 10
100 1.0 k 10 k 100 k 1.0 M 10 M 0.2 0.4 0.6 0.8 1.0
0
30
60
90
120
150
180
RD/RT Ratio
Discharge Resistor
Pin 6 to Gnd
VCC = 20 V
CT = 2.0 nF
TA = 25
°
C
RC/RT Ratio
Charge Resistor
Pin 6 to V reg
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 M
Ω
CL = 2.0 pF
TA = 25
°
C
Gain
Phase
VCC = 20 V
TA = 25
°
C
Source Saturation
(Load to Ground)
Sink Saturation
(Load to V ref)VCC = 20 V
TA = 25
°
C
Gnd
Vref
50
MC33363B
5
MOTOROLA ANALOG IC DEVICE DATA
1.0
160
0
2.0
0
–50
32
0
0
COSS, DRAIN–SOURCE CAP ACITANCE (pF)
VDS, DRAIN–SOURCE VOLTAGE (V)
VCC = 20 V
TA = 25
°
C
Ipk, PEAK STARTUP CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
VPin 1 = 400 V
TA = 25
°
C
ICC, SUPPL Y CURRENT (mA)
VCC, SUPPLY VOLTAGE (V)
RDS(on), DRAIN–SOURCE ON–RESISTANCE ( )
Ω
TA, AMBIENT TEMPERATURE (
°
C)
ID = 200 mA
Vreg, REGULA T OR VOLTAGE CHANGE (mV)
Figure 9. Regulator Output Voltage
Change versus Source Current
Ireg, REGULATOR SOURCE CURRENT (mA)
Figure 10. Peak Startup Current
versus Power Supply Voltage
VCC = 20 V
RT = 10 k
CPin 8 = 1.0
µ
F
TA = 25
°
C
Figure 11. Power Switch Drain–Source
On–Resistance versus Temperature Figure 12. Power Switch
Drain–Source Capacitance versus Voltage
Figure 13. Supply Current versus Supply Voltage
Pulse tested with an on–time of 20
µ
s to 300
µ
s
at < 1.0% duty cycle. The on–time is adjusted at
Pin 1 for a maximum peak current out of Pin 3.
∆
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible. COSS measured at 1.0 MHz with 50 mVpp.
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = Gnd
TA = 25
°
C
–20
–40
–60
–80
24
16
8.0
0
2.4
1.6
0.8
0
1.0
0
120
40
80
0
4.0 8.0 12 16 20 2.0 4.0 6.0 8.0 10 12 14
–25 0 25 50 75 150100 10 100 1000
10 20 30 40
125
0.01
100
RJA, THERMAL RESISTANCE
t, TIME (s)
Figure 14. DW and P Suffix Transient
Thermal Resistance
θ
JUNCTION–T O–AIR ( C/W)
°
0.1 1.0 10 100
10
1.0
L = 12.7 mm of 2.0 oz.
copper. Refer to Figures
15 and 16.
3.2
CT = 2.0 nF
CT = 390 pF
MC33363B
6MOTOROLA ANALOG IC DEVICE DATA
0
100
RJA, THERMAL RESISTANCE
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50
°
C
Figure 15. DW Suffix (SOP–16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
θ
JUNCTION–T O–AIR ( C/W)
°
PD, MAXIMUM POWER DISSIP ATION (W)
R
θ
JA
90
70
60
80
50
10 20 30 40 50
2.8
2.4
1.6
1.2
2.0
0.8
0.4
0
40
30 00
Figure 16. P Suffix (DIP–16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
ÏÏÏ
ÏÏÏ
Graphs represent symmetrical layout
3.0 mm
Printed circuit board heatsink example
L
L
100
80
60
40
20
10 20 30 40 50
L, LENGTH OF COPPER (mm)
PD, MAXIMUM POWER DISSIPATION (W)
5.0
4.0
3.0
2.0
1.0
0
PD(max) for TA = 70
°
C
2.0 oz
Copper
ÏÏÏ
ÏÏÏ
R
θ
JA
R , THERMAL RESISTANCE
JA
θ
JUNCTION–T O–AIR ( C/W)
°
ÏÏÏ
ÏÏÏ
ÏÏÏ
Graphs represent symmetrical layout
3.0 mm
L
L2.0 oz
Copper
ÏÏÏ
ÏÏÏ
ÏÏÏ
Printed circuit board heatsink example
PIN FUNCTION DESCRIPTION
Pin Function Description
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Startup Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain
of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges
an external capacitor that connects from the VCC pin to ground.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
2
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and
the VCC potential on Pin 3.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
3
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1.
When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied
from an auxiliary transformer winding.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
4, 5, 12, 13
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal
path from the die to the printed circuit board.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
6
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
RT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
7
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
CT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT,
programs the Oscillator frequency.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
8
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Regulator Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor
of at least 1.0 µF for stability.
ÁÁÁÁÁ
ÁÁÁÁÁ
9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Compensation
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin is the Error Amplifier output and is made available for loop compensation. It can be used as
an input to directly control the PWM Comparator.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
10
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
V oltage Feedback
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
11
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Overvoltage
Protection Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This input provides runaway output voltage protection due to an external component or connection
failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
14, 15
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
16
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Power Switch
Drain
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
MC33363B
7
MOTOROLA ANALOG IC DEVICE DATA
Figure 17. Representative Block Diagram
Oscillator
PWM
PWM Latch
Current Limit
Thermal
Shutdown
Error
Startup
Control
Band Gap
Regulator UVLO
14.5 V/
9.5 V
OVP 2.6 V
Current
2.6 V
Regulator Output
6.5 V
R
C
8
6
7
4, 5, 12, 13Gnd
11
16
9
10
1
Voltage
Compensation
Power Switch
Overvoltage
AC Input
DC Output
2.25 I
I
8.1
R
SQ
Driver
3
Startup Input
405
T
T
Comparator
Leading Edge
Blanking
Mirror
4 I
270
µ
A
VCC
Comparator
Protection
Input
Drain
Feedback Input
Amplifier
Figure 18. Timing Diagram
Capacitor C
Compensation
PWM
Comparator
Output
Oscillator Output
PWM Latch
Q Output
Power Switch
Gate Drive
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range Output Overload
Current
Limit
Threshold
0.6 V
2.6 V
Current Limit
Propagation
Delay
T
MC33363B
8MOTOROLA ANALOG IC DEVICE DATA
OPERATING DESCRIPTION
Introduction
The MC33363B represents a new higher level of
integration by providing all the active high voltage power,
control, and protection circuitry required for implementation
of a flyback or forward converter on a single monolithic chip.
This device is designed for direct operation from a rectified
240 Vac line source and requires a minimum number of
external components to implement a complete converter. A
description of each of the functional blocks is given below,
and the representative block and timing diagrams are shown
in Figures 17 and 18.
Oscillator and Current Mirror
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 3. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in a
low state, thus producing a well controlled amount of output
deadtime. The amount of deadtime is relatively constant with
respect to the oscillator frequency when operating below
1.0 MHz. The maximum Power Switch duty cycle at Pin 16
can be modified from the internal 50% limit by providing an
additional charge or discharge current path to CT, Figure 19.
In order to increase the maximum duty cycle, a discharge
current resistor RD is connected from Pin 7 to ground. To
decrease the maximum duty cycle, a charge current resistor
RC is connected from Pin 7 to the Regulator Output. Figure 4
shows an obtainable range of maximum output duty cycle
versus the ratio of either RC or RD with respect to RT.
Figure 19. Maximum Duty Cycle Modification
PWM
Current
Regulator Output
1.0
R
C
8
6
2.25 I
I
T
T
Mirror
4 I
Oscillator
Comparator
RD
RC
7
Current
Limit
Reference
Blanking
Pulse
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer to
Figure 1. Note that resistor RT also programs the Current
Limit Comparator threshold.
Ichg
ń
dscg
+
5.4
RTf
[
Ichg
ń
dscg
4CT
PWM Comparator and Latch
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non–inverting input,
while the error amplifier output is applied into the inverting
input. The Oscillator applies a set pulse to the PWM Latch
while CT is discharging, and upon reaching the valley
voltage, Power Switch conduction is initiated. When CT
charges to a voltage that exceeds the error amplifier output,
the PWM Latch is reset, thus terminating Power Switch
conduction for the duration of the oscillator ramp–up period.
This PWM Comparator/Latch combination prevents multiple
output pulses during a given oscillator clock cycle. The timing
diagram shown in Figure 18 illustrates the Power Switch duty
cycle behavior versus the Compensation voltage.
Current Limit Comparator and Power Switch
The MC33363B uses cycle–by–cycle current limiting as a
means of protecting the output switch transistor from
overstress. Each on–cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp–up period.
The Power Switch is constructed as a SenseFET allowing
a virtually lossless method of monitoring the drain current. It
consists of a total of 1462 cells, of which 36 are connected to
a 8.1 Ω ground–referenced sense resistor. The Current
Sense Comparator detects if the voltage across the sense
resistor exceeds the reference level that is present at the
inverting input. If exceeded, the comparator quickly resets
the PWM Latch, thus protecting the Power Switch. The
current limit reference level is generated by the 2.25 I output
of the Current Mirror . This current causes a reference voltage
to appear across the 405 Ω resistor. This voltage level, as
well as the Oscillator charge/discharge current are both set
by resistor RT. Therefore when selecting the values for RT
and CT, RT must be chosen first to set the Power Switch peak
drain current, while CT is chosen second to set the desired
Oscillator frequency. A graph of the Power Switch peak drain
current versus RT is shown in Figure 2 with the related
formula below.
Ipk
+
8.8
ǒ
RT
1000
Ǔ
– 1.077
MC33363B
9
MOTOROLA ANALOG IC DEVICE DATA
The Power Switch is designed to directly drive the converter
transformer and is capable of switching a maximum of 700 V
and 1.0 A. Proper device voltage snubbing and heatsinking
are required for reliable operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset
of the PWM Latch. The premature reset is generated each
time the Power Switch is driven into conduction. It appears as
a narrow voltage spike across the current sense resistor , and
is due to the MOSFET gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. The Leading Edge Blanking circuit has a
dynamic behavior in that it masks the current signal until the
Power Switch turn–on transition is completed. The current
limit propagation delay time is typically 262 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn–off.
Error Amplifier
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side voltage
sensing, Figure 17. It features a typical dc voltage gain of 82
dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of
phase margin, Figure 5. The noninverting input is internally
biased at 2.6 V ±3.1% and is not pinned out. The Error
Amplifier output is pinned out for external loop compensation
and as a means for directly driving the PWM Comparator.
The output was designed with a limited sink current capability
of 270 µA, allowing it to be easily overridden with a pull–up
resistor. This is desirable in applications that require
secondary side voltage sensing.
Overvoltage Protection
An Overvoltage Protection Comparator is included to
eliminate the possibility of runaway output voltage. This
condition can occur if the control loop feedback signal path is
broken due to an external component or connection failure.
The comparator is normally used to monitor the primary side
VCC voltage. When the 2.6 V threshold is exceeded, it will
immediately turn off the Power Switch, and protect the load
from a severe overvoltage condition. This input can also be
driven from external circuitry to inhibit converter operation.
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output stage
is enabled. The UVLO comparator monitors the VCC voltage
at Pin 3 and when it exceeds 14.5 V, the reset signal is
removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold is
crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33363B. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off–line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input, Pin 1.
This causes the MOSFET to enhance and supply internal
bias as well as charge current to the VCC bypass capacitor
that connects from Pin 3 to ground. When VCC reaches the
UVLO upper threshold of 15.2 V, the IC commences
operation and the startup MOSFET is turned off. Operating
bias is now derived from the auxiliary transformer winding,
and all of the device power is efficiently converted down from
the rectified ac line.
The startup MOSFET will provide a steady current of
1.7 mA, Figure 10, as VCC increases or shorted to ground.
The startup MOSFET is rated at a maximum of 400 V with
VCC shorted to ground, and 500 V when charging a VCC
capacitor of 1000 µF or less.
Regulator
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control system
circuitry. It is capable of up to 10 mA and has short–circuit
protection. This output requires an external bypass capacitor
of at least 1.0 µF for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature is
exceeded. When activated, typically at 150°C, the Latch is
forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It is
not intended to be used as a substitute for proper
heatsinking.
The MC33363B is contained in a heatsinkable plastic
dual–in–line package in which the die is mounted on a
special heat tab copper alloy lead frame. This tab consists of
the four center ground pins that are specifically designed to
improve thermal conduction from the die to the circuit board.
Figures 15 and 16 show a simple and effective method of
utilizing the printed circuit board medium as a heat dissipater
by soldering these pins to an adequate area of copper foil.
This permits the use of standard layout and mounting
practices while having the ability to halve the junction to air
thermal resistance. The examples are for a symmetrical
layout on a single–sided board with two ounce per square
foot of copper.
MC33363B
10 MOTOROLA ANALOG IC DEVICE DATA
DW SUFFIX
PLASTIC PACKAGE
CASE 751N–01
(SOP–16L)
ISSUE O
OUTLINE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
–A–
–B–
16 9
18
D
G
H
S
C
13 PL
S
B
M
0.25 (0.010) T
–T–
SEATING
PLANE
J
M
L
R
PF
K
S
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.760 18.80 19.30
B0.245 0.260 6.23 6.60
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.050 0.070 1.27 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.120 0.140 3.05 3.55
L0.295 0.305 7.50 7.74
M0 10 0 10
P0.200 BSC 5.08 BSC
R0.300 BSC 7.62 BSC
S0.015 0.035 0.39 0.88
____
P SUFFIX
PLASTIC PACKAGE
CASE 648E–01
(DIP–16)
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A10.15 10.45 0.400 0.411
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0 7 0 7
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P
G
9X
D13X
SEATING
PLANE
–T–
S
A
M
0.010 (0.25) B S
T
16 9
81
F
J
RX 45
_
____
M
T
S
S2.54 BSC 0.100 BSC
T3.81 BSC 0.150 BSC
C
K
MC33363B
11
MOTOROLA ANALOG IC DEVICE DATA
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer .
MC33363B
12 MOTOROLA ANALOG IC DEVICE DATA
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MC33363B/D
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