©2001 Integrated Device Technology, Inc.
JULY 2001
DSC 4830/13
1
Functional Block Diagram
Features:
◆True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
◆Pipelined output mode
◆Counter enable and reset features
◆Dual chip enables allow for depth expansion without
additional logic
◆Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆Separate byte controls for multiplexed bus and bus
matching compatibility
◆LVTTL- compatible, single 3.3V (±150mV) power supply for
core
◆LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
◆Industrial temperature range (-40°C to +85°C) is
available for selected speeds
◆Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3579S
CNTRSTR
Counter/
Address
Reg.
A
14R
A
0R
Counter/
Address
Reg.
CNTENR
ADSR
CNTENL
ADSL
CNTRSTL
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
B
W
0
L
B
W
1
L
B
W
2
L
B
W
3
L
B
W
3
R
B
W
2
R
B
W
1
R
B
W
0
R
I/O0L-I/O
35L
A14L
A0L
I/O0R -I/O
35R
Din_L
ADDR_L
Din_R
ADDR_R
OER
OEL
4830 tbl 01
BE
3L
BE2L
BE1L
BE0L
R/WL
CE0L
BE
3R
BE2R
BE1R
BE0R
R/WR
CE0R
CE1R
CE1L
32K x 36
MEMORY
ARRAY
CLKR
CLKL
,
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3579 has been optimized for applications having unidirectional or
bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3579 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
A17
VSS
B17
I/O15R
C17
VSS
D17
I/O14R
E16
VSS E17
I/O13L
D16
I/O14L
C16
I/O15L
B16
I/O16L
A16
I/O17L
A15
OPTL
B15
VDDQR
C15
I/O16R
D15
VDDQL
E15
I/O13R
E14
I/O12L
D14
I/O17R
D13
VDD
C12
A6L C14
VDD
B14
VSS
A14
A0L
A12
CNTEN
L
B12
A5L
C11
R/WL
D12
A3L
D11
CNTRST
L
C10
VSS
B11
ADSL
A11
CLKL
D8
BE0L
C8
BE3L
A9
BE1L
D9
VDD
C9
CE1L
B9
CE0L
D10
OEL
C7
A10L
B8
BE2L
A8
A8L
B13
A1L
A13
A4L
A10
VDD
D7
A7L
B7
A9L
A7
A12L
B6
A13L
C6
A14L
D6
A11L
A5
NC
B5
NC
C5
NC
D5
NC
A4
NC
B4
VSS
C4
VDD
D4
I/O20L
A3
VSS
B3
I/O18R
C3
VDDQR
D3
I/O21L
D2
VSS
C2
I/O19R
B2
VSS
A2
IO18L
A1
IO19L
B1
I/O20R
C1
VDDQL
D1
I/O22L
E1
I/O23L E2
I/O22R E3
VDDQR E4
I/O21R
F1
VDDQL F2
I/O23R F3
I/O24L F4
VSS
G1
I/O26L G2
VSS G3
I/O25L
G4
I/O24R
H1
VDD H2
I/O26R
H3
VDDQR H4
I/O25R
J1
VDDQL J2
VDD J3VSS J4
VSS
K1
I/O28R
K2
VSS K3
I/O27R
K4
VSS
L1
I/O29R L2
I/O28L
L3
VDDQR L4
I/O27L
M1
VDDQL M2
I/O29L M3
I/O30R M4
VSS
N1
I/O31L N2
VSS N3
I/O31R
N4
I/O30L
P1
I/O32R P2
I/O32L P3
VDDQR P4
I/O35R
R1
VSS R2
I/O33L R3
I/O34R R4NC
T1
I/O33R
T2
I/O34L T3
VDDQL T4
VSS
U1
VSS U2
I/O35L U3
VDD U4
NC
P5
NC
R5NC
U6
A11R
P12
CNTEN
R
P8
A8R
U10
OER
P9
BE1R
R8
BE2R
T8
BE3R
U9
VDD
P10
VDD
T11
R/WR
U8
BE0R
P11
CLKR
R12
A5R
T12
A6R
U12
A3R
P13
A4R
P7
A12R
R13
A1R
T13
A2R
U13
A0R
R6
A13R
T5NC
U7
A7R U14
VDD
T14
VSS
R14
VSS
P14
I/O2L P15
I/O3L
R15
VDDQL
T15
I/O0R
U15
OPTR
U16
I/O0L
U17
I/O1L
T16
VSS T17
I/O2R
R17
VDDQR
R16
I/O1R
P17
I/O4L
P16
VSS
N17
I/O5L
N16
I/O4R
N15
VDDQL
N14
I/O3R
M17
VDDQR
M16
I/O5R
M15
I/O6L
M14
VSS
L17
I/O8L
L16
VSS
L15
I/O7L
L14
I/O6R
K17
VSS
K16
I/O8R
K15
VDDQL
K14
I/O7R
J17
VDDQR
J16
VSS
J15
VDD
J14
VSS
H17
I/O10R
H16
VSS
H15
IO9R
H14
VDD
G17
I/O11R
G16
I/O10L
G15
VDDQL
G14
I/O9L
F17
VDDQR
F16
I/O11L
F14
VSS
70V3579BF
BF-208(5)
208-Pin fpBGA
Top View(6)
F15
I/O12R
R9
CE0R R11
ADSR
T6
A14R
T9
CE1R
A6
NC
B10
VSS
C13
A2L
P6NC
R10
VSS
R7
A9R
T10
VSS
T7
A10R
U5NC
4830 drw02c ,
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
Pin Configuration(1,2,3,4) (con't.)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
70V3579BC
BC-256(5)
256-Pin BGA
Top View (6)
E16
I/O14R
D16
I/O16R
C16
I/O16L
B16
NC
A16
NC
A15
NC
B15
I/O17L
C15
I/O17R
D15
I/O15L
E15
I/O14L
E14
I/O13L
D14
I/O15R
D13
VDD
C12
A6L C14
OPTL
B14
VDD
A14
A0L
A12
A5L
B12
A4L
C11
ADSL
D12
VDDQR
D11
VDDQR
C10
CLKL
B11
CNTRST
L
A11
CNTEN
L
D8
VDDQR
C8
BE1L
A9
CE1L
D9
VDDQL
C9
BE0L
B9
CE0L
D10
VDDQL
C7
A7L
B8
BE3L
A8
BE2L
B13
A1L
A13
A2L
A10
OEL
D7
VDDQR
B7
A9L
A7
A8L
B6
A12L
C6
A10L
D6
VDDQL
A5
A14L
B5
NC
C5
A13L
D5
VDDQL
A4
NC
B4
NC
C4
NC
D4
VDD
A3
NC
B3NC
C3
VSS
D3
I/O20L
D2
I/O19R
C2
I/O19L
B2
NC
A2
NC
A1
NC
B1
I/O18L
C1
I/O18R
D1
I/O20R
E1
I/O21R
E2
I/O21L
E3
I/O22L
E4
VDDQL
F1
I/O23L F2
I/O22R F3
I/O23R F4
VDDQL
G1
I/O24R G2
I/O24L G3
I/O25L
G4
VDDQR
H1
I/O26L H2
I/O25R
H3
I/O26R H4
VDDQR
J1
I/O27L J2
I/O28R
J3
I/O27R
J4
VDDQL
K1
I/O29R
K2
I/O29L K3
I/O28L
K4
VDDQL
L1
I/O30L
L2
I/O31R
L3
I/O30R L4
VDDQR
M1
I/O32R
M2
I/O32L
M3
I/O31L
M4
VDDQR
N1
I/O33L N2
I/O34R N3
I/O33R
N4
VDD
P1
I/O35R
P2
I/O34L
P3NC P4
NC
R1
I/O35L
R2NC R3NC R4NC
T1NC T2NC T3NC T4NC
P5
A13R
R5
NC
P12
A6R
P8
BE1R
P9
BE0R
R8
BE3R
T8
BE2R
P10
CLKR
T11
CNTEN
R
P11
ADSR
R12
A4R
T12
A5R
P13
A3R
P7
A7R
R13
A1R
T13
A2R
R6
A12R
T5
A14R T14
A0R
R14
OPTR
P14
I/O0L
P15
I/O0R
R15
NC
T15
NC T16
NC
R16
NC
P16
I/O1L
N16
I/O2R
N15
I/O1R
N14
I/O2L
M16
I/O4L
M15
I/O3L
M14
I/O3R
L16
I/O5R
L15
I/O4R
L14
I/O5L
K16
I/O7L
K15
I/O6L
K14
I/O6R
J16
I/O8L
J15
I/O7R
J14
I/O8R
H16
I/O10R
H15
IO9L
H14
I/O9R
G16
I/O11R
G15
I/O11L
G14
I/O10L
F16
I/O12L
F14
I/O12R F15
I/O13R
R9
CE0R
R11
CNTRST
R
T6
A11R
T9
CE1R
A6
A11L
B10
R/WL
C13
A3L
P6
A10R
R10
R/WR
R7
A9R
T10
OER
T7
A8R
,
E5
VDD
E6
VDD
E7
VSS
E8
VSS
E9
VSS
E10
VSS
E11
VDD
E12
VDD
E13
VDDQR
F5
VDD
F6
VSS F8VSS
F9
VSS
F10
VSS F12
VDD
F13
VDDQR
G5
VSS G6
VSS G7
VSS
G8
VSS
G9
VSS G10
VSS G11
VSS
G12
VSS
G13
VDDQL
H5
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VSS H13
VDDQL
J5
VSS J6VSS J7
VSS J8
VSS J9
VSS J10
VSS J11
VSS J12
VSS
J13
VDDQR
K5
VSS
K6
VSS K7
VSS
K8
VSS
L5
VDD
L6VSS
L7
VSS
L8
VSS
M5
VDD M6
VDD M7
VSS M8
VSS
N5
VDDQR N6
VDDQR N7
VDDQL
N8
VDDQL
K9
VSS
K10
VSS K11
VSS
K12
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VDD
M9
VSS M10
VSS M11
VDD M12
VDD
N9
VDDQR N10
VDDQR N11
VDDQL
N12
VDDQL
K13
VDDQR
L13
VDDQL
M13
VDDQL
N13
VDD
F7
VSS F11
VSS
4830 drw 02d
,
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configuration(1,2,3,4) (con't.)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
70V3579DR
DR-208(5)
208-Pin PQFP
Top View(6)
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
VSS
VDDQL
I/O35R
I/O35L
VDD
VSS
NC
NC
NC
NC
NC
NC
NC
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
BE3R
BE2R
BE1R
BE0R
CE1R
CE0R
VDD
VDD
VSS
VSS
CLKR
OER
R/WR
ADSR
CNTENR
C
NTRSTR
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
VSS
OPTR
I/O0L
I/O0R
VDDQL
VSS
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
VSS
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
VSS
VDDQR
I/O18R
I/O18L
VSS
VDD
VSS
NC
NC
NC
NC
NC
NC
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
BE3L
BE2L
BE1L
BE0L
CE1L
CE0L
VDD
VDD
VSS
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
CNTRSTL
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VDD
VSS
OPTL
I/O17L
I/O17R
VDDQR
VSS
4830 drw 02a
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = VIH.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table IRead/Write and Enable Control(1,2,3,4)
Pin Names
Left Port Right Port Names
CE0L, CE1L CE
0R, CE1R Chip Enables
R/WLR/WRRe ad/Wri te Enable
OELOEROutput Enable
A0L - A14L A0R - A14R Address
I/O0L - I/O35L I/O0R - I/ O35R Data Input/ Outp ut
CLKLCLKRClock
ADSLADSRAddress Strobe Enable
CNTENLCNTENRCo un ter E n ab le
CNTRSTLCNTRSTRCo unte r Re se t
BE0L - BE3L BE0R - BE3R Byte Enables (9-bit b ytes)
VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1)
OPTLOPTROp tio n fo r se le c ting VDDQX(1,2)
VDD Power (3.3V)(1)
VSS Ground (0V)
4 830 t bl 01
OE CLK CE0CE1BE3BE2BE1BE0R/WBy te 3
I/O27-35 Byt e 2
I/O18-26 By te 1
I/O9-17 By te 0
I/O0-8 MODE
X↑HXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X↑XL XXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X↑L HHHHHXHigh-ZHigh-ZHigh-ZHigh-ZAll Bytes Deselected
X↑L H H H H L L High-Z High-Z High-Z DIN Wr ite to By te 0 Only
X↑LHHHLHLHigh-ZHigh-Z D
IN Hi g h-Z Wr ite to By te 1 Only
X↑LHHLHHLHigh-Z D
IN Hi g h-Z Hi g h-Z Wr ite to By te 2 Only
X↑LHLHHHL D
IN Hi g h-Z Hi gh -Z Hi g h-Z Wr ite to By te 3 Only
X↑L H H H L L L High-Z High-Z DIN DIN Wri te to Lowe r 2 B yte s Onl y
X↑LHLLHHL D
IN DIN Hi g h-Z Hi g h-Z Wri te to Up p e r 2 b y te s Onl y
X↑LHLLLLL D
IN DIN DIN DIN Write to All Bytes
L↑L H H H H L H High-Z High-Z High-Z DOUT Re ad By te 0 Only
L↑L H H H L H H High-Z High-Z DOUT Hi g h-Z Re a d By te 1 Onl y
L↑LHHLHHHHigh-Z D
OUT High-Z Hi g h-Z Re ad B y te 2 Onl y
L↑LHLHHHHD
OUT High-Z High-Z Hi g h-Z Re ad B y te 3 Onl y
L↑L H H H L L H High-Z High-Z DOUT DOUT Read Lo wer 2 Bytes Only
L↑LHLLHHHD
OUT DOUT Hig h-Z Hi g h-Z Re ad Up p e r 2 B y te s On ly
L↑LHLLLLHD
OUT DOUT DOUT DOUT Re ad All Bytes
H↑LHLLLLXHigh-ZHigh-ZHigh-ZHigh-ZOutputs Disabled
4830 tbl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V),
then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be
supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will
operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are
independent of one another—both ports can operate at 3.3V levels, both can
operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
Recommended Operating
Temperature and Supply Voltage(1,2)
Recommended DC Operating
Conditions with VDDQ at 2.5V
Absolute Maximum Ratings(1)
Truth Table IIAddress Counter Control(1,2)
NOTES:
1 . "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied
as indicated above.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
Address Previous
Address Addr
Used CLK(6) ADS CNTEN CNTRST I/O(3) MODE
XX0
↑XX L
(4) DI/O(0) Counter Reset to Address 0
An X An ↑ L(4) XHD
I/O (n) External Address Used
An Ap Ap ↑HH H D
I/O(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
↑H L
(5) HD
I/O(p+1) Counter Enabled—In te rn al A d dr e s s g e n e rat io n
4830 tbl 03
Grade Ambient
Temperature GND VDD
Commercial 0OC to +70OC0V3.3V
+ 150m V
Industrial -40OC to +85OC0V3.3V
+ 150m V
4830 tbl 04
Symbol Parameter Min. Typ. Max. Unit
VDD Co re Sup ply Voltag e 3.15 3.3 3.45 V
VDDQ I/O Sup p ly Vol tage (3) 2.375 2.5 2.625 V
VSS Ground 0 0 0 V
VIH Inp u t Hig h Vo l tag e (3)
(Ad d res s & Co ntrol Inp uts ) 1.7 ____ VDDQ + 125mV (2) V
VIH Input High Voltage - I/O(3) 1.7 ____ VDDQ + 125mV (2) V
VIL Inp u t Lo w Vo l tag e -0. 3(1) ____ 0.7 V
4830 tb l 05a
Symbol Rating Commercial
& Industri al Unit
VTERM(2) Terminal Vo ltag e
with Re s p e c t to
GND
-0.5 to +4.6 V
TBIAS Temperature
Under Bias -55 to + 125 oC
TSTG Storage
Temperature -65 to + 150 oC
IOUT DC Outp ut Curre nt 50 mA
4 830 t bl 06
Recommended DC Operating
Conditions with VDDQ at 3.3V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
Symbol Parameter Min. Typ. Max. Unit
VDD Co re Su pp ly Voltag e 3. 15 3.3 3. 45 V
VDDQ I/O Supp ly Vol tag e (3) 3.15 3.3 3.45 V
VSS Ground 0 0 0 V
VIH Inp u t High Vo l tag e
(Add ress & Co ntro l Inputs )(3) 2.0 ____ VDDQ + 1 50mV(2) V
VIH In p u t Hi g h Vo lt ag e - I/ O(3) 2.0 ____ VDDQ + 150mV (2) V
VIL Inp u t Lo w Vo l tag e -0. 3(1) ____ 0.8 V
4830 tbl 05b
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
Symbol Parameter Test Conditions
70V3579S
UnitMin. Max.
|ILI| Input Leak ag e Curre nt(1) VDDQ = Max., VIN = 0V to VDDQ ___ 10 µA
|ILO| Outp ut Le ak age Curre nt CE
0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ ___ 10 µA
VOL (3. 3V) Outp ut Low Voltag e (2) IOL = +4mA, VDDQ = Min. ___ 0.4 V
VOH (3.3V) Output High Voltage (2) IOH = -4mA, VDDQ = Mi n. 2.4 ___ V
VOL (2. 5V) Outp ut Low Voltag e (2) IOL = +2mA, VDDQ = Min. ___ 0.4 V
VOH (2.5V) Output High Voltage (2) IOH = -2mA, VDDQ = Mi n. 2.0 ___ V
4830 t bl 0 8
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol Parameter Conditions(2) Max. Unit
CIN Inp ut Capac itance VIN = 3dV 8 pF
COUT(3) Outp ut Cap acitance VOUT = 3d V 10. 5 p F
4830 tbl 07
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
8
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
70V3579S4
Com'l Only 70V3579S5
Com'l
& Ind
70V3579S6
Com'l
& Ind
Symbol Parameter Test Condition Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dynamic Ope rating
Current (Both
Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX(1)
COM'L S 375 460 285 360 245 310 mA
IND S
____ ____
285 415 245 360
I
SB1
Standby Current
(Bo th Ports - TTL
Le ve l Inp uts)
CE
L
=
CE
R
= V
IH
f = f
MAX(1)
COM'L S 145 190 105 145 95 125 mA
IND S
____ ____
105 175 95 150
I
SB2
Standby Current
(One Po rt - TTL
Le ve l Inp uts)
CE
"A"
= V
IL
and
CE
"B"
= V
IH(5)
Active Port Outputs Disabled,
f=f
MAX(1)
COM'L S 265 325 190 260 175 225 mA
IND S
____ ____
190 300 175 260
I
SB3
Full Standby Current
(B oth Ports - CM OS
Le ve l Inp uts)
Both Ports
CE
L
and
CE
R
> V
DD
- 0.2V, V
IN
> V
DD
- 0.2V
or V
IN
< 0.2V , f = 0
(2)
COM'LS615615615
mA
IND S
____ ____
630630
I
SB4
Full Standby Current
(One Po rt - CMOS
Le ve l Inp uts)
CE
"A"
< 0.2V an d
CE
"B"
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V o r V
IN
< 0.2V, Active
Port, Outputs Disable d, f = f
MAX(1)
COM'L S 265 325 180 260 170 225 mA
IND S
____ ____
180 300 170 260
4830 t b l 09
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
9
AC Test Conditions (VDDQ - 3.3V/2.5V)
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
In p ut P ul s e Lev e l s (A d d r e s s & Co ntro l s)
Input Pulse Levels (I/Os)
Inp ut Ris e /Fall Time s
Inp ut Timi ng Refere nc e Le ve ls
Output Refere nc e Leve ls
Output Load
GND to 3.0V/GND to 2.35V
GND to 3. 0V/GND to 2.35 V
3ns
1.5V/1.25V
1.5V/1.25V
F ig ures 1, 2, and 3
4830 tbl 10
1.5V/1.25
50Ω
50Ω
4830 drw 03
10pF
(Tester)
DATAOUT
,
4830 drw 04
590Ω
5pF*
435Ω
3.3V
DATAOUT
,
833Ω
5pF*
770Ω
2.5V
DATAOUT
,
-1
1
2
3
4
5
6
7
20.5 30 50 80 100 200
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
Capacitance (pF)
∆tCD
(Typical, ns)
4830 drw 05
•
•
••
,
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
70V3579S4
Com'l Only 70V3579S5
Com'l
& Ind
70V3579S6
Com'l
& Ind
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
tCYC2 Clock Cycle Time (Pipelined) 7.5 ____ 10 ____ 12 ____ ns
tCH2 Clock High Time (Pipelined) 3 ____ 4____ 5____ ns
tCL2 Clock Low Time (Pipelined) 3 ____ 4____ 5____ ns
tRClo c k Ris e Ti me ____ 3____ 3____ 3ns
tFClock Fall Time ____ 3____ 3____ 3ns
tSA Address Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHA Address Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSC Chip Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHC Chip Enable Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSB Byte Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHB By te Enab le Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSW R/W Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHW R/W Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSD Inp ut Data S e tup Time 1. 8 ____ 2.0 ____ 2.0 ____ ns
tHD Inp ut Data Ho ld Tim e 0. 7 ____ 0.7 ____ 1.0 ____ ns
tSAD ADS Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHAD ADS Ho ld Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSCN CNTEN Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHCN CNTEN Ho ld Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSRST CNTRST Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHRST CNTRST Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tOE(1) Output Enable to Data Valid ____ 4____ 5____ 6ns
tOLZ Output Enable to Output Lo w-Z 0 ____ 0____ 0____ ns
tOHZ Output Enable to Output Hig h-Z 1 4 1 4.5 1 5 ns
tCD2 Clock to Data Valid (Pipelined) ____ 4.2 ____ 5____ 6ns
tDC Data Outp ut Hold After Clo ck High 1 ____ 1____ 1____ ns
tCKHZ Clo ck Hig h to Output Hig h-Z 1 3 1 4.5 1.5 6 ns
tCKLZ Clo ck High to Outp ut Lo w-Z 1 ____ 1____ 1____ ns
Port-to-P ort Delay
tCO Clo ck -to-Clo ck Offs e t 6 ____ 8____ 10 ____ ns
4830 tbl 11
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
tSC tHC
CE0(B1)
ADDRESS(B1) A0A1A2A3A4A5
tSA tHA
CLK
4830 drw 07
Q0Q1Q3
DATAOUT(B1)
tCH2 tCL2
tCYC2
ADDRESS(B2) A0A1A2A3A4A5
tSA tHA
CE0(B2)
DATAOUT(B2) Q2Q4
tCD2 tCD2 tCKHZ tCD2
tCKLZ
tDC tCKHZ
tCD2
tCKLZ
tSC tHC
tCKHZ
tCKLZ
tCD2
A6
A6
tDC
tSC tHC
tSC tHC
An An + 1 An + 2 An + 3
tCYC2
tCH2 tCL2
R/W
ADDRESS
CE0
CLK
CE1
BE(0-3)
(3)
DATAOUT
OE
tCD2
tCKLZ
Qn Qn + 1 Qn + 2
tOHZ tOLZ
tOE
4830 drw 06
(1)
(1)
tSC tHC
tSB tHB
tSW tHW
tSA tHA
tDC
tSC tHC
tSB tHB
(4)
(1 Latency)
(5)
(5)
Timing Waveform of a Multi-Device Pipelined Read(1,2)
Timing Waveform of Read Cycle for Pipelined Operation(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3579 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
CLKL
R/WL
ADDRESSL
DATAINL
CLKR
R/WR
ADDRESSR
DATAOUTR
tSW tHW
tSA tHA
tSD tHD
tSW tHW
tSA tHA
tCO(3)
tCD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
4830 drw 08
tDC
R/W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATAIN Dn + 2
CE0
CLK
4830 drw 09
Qn Qn + 3
DATAOUT
CE1
BEn
tCD2 tCKHZ tCKLZ tCD2
tSC tHC
tSB tHB
tSW tHW
tSA tHA
tCH2 tCL2
tCYC2
READ NOP READ
tSD tHD
(3)
(1)
tSW tHW
WRITE
(4)
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
NOTES:
1. CE0, BEn, and ADS = VIL; CE 1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC2 + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
NOTES:
1. Output state (High, Low, or H igh-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
ADDRESS An
CLK
DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3
ADS
CNTEN
tCYC2
tCH2 tCL2
4830 drw 11
tSA tHA
tSAD tHAD
tCD2
tDC
READ
EXTERNAL
ADDRESS READ WITH COUNTER COUNTER
HOLD
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
Qn + 1
R/W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
DATAIN Dn + 3Dn + 2
CE0
CLK
4830 drw 10
DATAOUT Qn Qn + 4
CE1
BEn
OE
tCH2 tCL2
tCYC2
tCKLZ tCD2
tOHZ
tCD2
tSD tHD
READ WRITE READ
tSC tHC
tSB tHB
tSW tHW
tSA tHA
(3)
(1)
tSW tHW
(4)
Timing Waveform of Pipelined Read with Address Counter Advance(1)
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
NOTES:
1. Output state ( High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
ADDRESS An
D0
tCH2 tCL2
tCYC2
Q0Q1
0
CLK
DATAIN
R/W
CNTRST
4830 drw 13
INTERNAL(3)
ADDRESS
ADS
CNTEN
tSRST tHRST
tSD tHD
tSW tHW
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRESS 1 READ
ADDRESS n
Qn
An + 1 An + 2
READ
ADDRESS n+1
DATAOUT
tSA tHA
1An An + 1
(4)
(5)
(6)
Ax
tSAD tHAD
tSCN tHCN
Timing Waveform of Write with Address Counter Advance(1)
Timing Waveform of Counter Reset(2)
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS An
CLK
DATAIN Dn Dn + 1 Dn + 1 Dn + 2
ADS
CNTEN
tCH2 tCL2
tCYC2
4830 drw 12
INTERNAL(3)
ADDRESS An(7) An + 1 An + 2 An + 3 An + 4
Dn + 3 Dn + 4
tSA tHA
tSAD tHAD
WRITE
COUNTER HOLD WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
tSCN tHCN
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Functional Description
The IDT70V3579 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to
stall the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT70V3579s
for depth expansion configurations. Two cycles are required with CE0
LOW and CE1 HIGH to re-activate the outputs.
4830 drw 14
IDT70V3579 CE0
CE1
CE1
CE0
CE0
CE1
A15
CE1
CE0
VDD VDD
IDT70V3579
IDT70V3579
IDT70V3579
Control Inputs
Control Inputs
Control Inputs
Control Inputs BE,
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
Depth and Width Expansion
The IDT70V3579 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3579 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the
control signals, the devices can be grouped as necessary to accom-
modate applications needing 72-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3579
6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
16
Ordering Information
A
Power 99
Speed A
Package A
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
DR
BC
208-pin fpBGA (BF-208)
208-pin PQFP (DR-208)
256-pin BGA (BC-256)
4
5
6
XXXXX
Device
Type
IDT
Speed in nanosecond
4830 drw15
S Standard Power
70V3579 1Mbit (32K x 36-Bit) Synchronous Dual-Port RAM
(133MHz) Commercial Only
(100MHz) Commercial & Industrial
(83MHz) Commercial & Industrial
,
,
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/9/98: Initial Public Release
3/12/99: Added fpBGA package
4/28/99: Fixed typo on page 10
6/8/99: Changed drawing format
Page 2 Changed package body dimensions
6/15/99: Page 5 Deleted note 6 for Table II
8/4/99: Page 6 Improved power numbers
10/4/99: Upgraded speed to 133MHz, added 2.5V I/O capability
10/19/99: Page 4 Corrected I/O numbers in Truth Table I
11/12/99: Replaced IDT logo
4/10/00: Added new BGA package, added full 2.5V interface capability
1/12/01: Page 6 Updated Truth Table II
Increated storage temperature parameter
Clarified TA Parameter
Page 8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed note 7 on DC Electrical Characteristics table
Removed Preliminary status
4/10/01: Added Industrial Temperature Ranges and removed related notes
7/19/01: Page 3 Replaced incorrect BGA package drawing
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
