PRODUCTPREVIEW
UCC2917
UCC3917
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SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Positive Floating Hot-Swap Power Manager
Check for Samples: UCC2917,UCC3917
1FEATURES DESCRIPTION
The UCCx917 family of positive-floating hot-swap
•Manages Hot-Swap of 15 V and Above managers provides complete power management,
•Precision Fault Threshold hot-swap, and fault handling capability. The voltage
•Programmable Average Power Limiting limitation of the application is only restricted by the
external component voltage limitations. The device
•Programmable Linear Current Control provides its own supply voltage via a charge pump
•Programmable Overcurrent Limit referenced to VOUT. The onboard 10-V shunt
•Programmable Fault Time regulator protects the device from excess voltage.
The devices also have catastrophic fault indication to
•Internal Charge Pump to Control External alert the user that the ability to shut off the output
N-channel MOSFET Device N-channel MOSFET has been bypassed. All control
•Fault Output and Catastrophic Fault Indication and housekeeping functions are integrated and
•Fault Mode Programmable to Latch or Retry externally programmable. These include the fault
current level, maximum output sourcing current,
•Shutdown Control maximum fault time, soft-start time, and average
•Undervoltage Lockout N-channel MOSFET power limiting.
The fault level across the current-sense amplifier is
APPLICATIONS fixed at 50 mV to minimize total drop out. Once 50
•390-V DC Distribution mV is exceeded across the current-sense resistor,
•General High-Voltage Power Management the fault timer starts. The maximum allowable
sourcing current is programmed with a voltage divider
from the VREF/CATFLT pin to generate a fixed
voltage on the MAXI pin. The current level at which
the output appears as a current source is equal to
VMAXI divided by the current-sense resistor. If desired,
a controlled current startup can be programmed with
a capacitor on MAXI.
When the output current is below the fault level, the
output device is switched on with full gate drive.
When the output current exceeds the fault level, but
is less than maximum allowable sourcing level
programmed by MAXI, the output remains switched
on, and the fault timer starts charging the timing
capacitor CT. Once CTcharges to 2.5 V, the output
device is turned off and attempts either a retry
sometime later or waits for the state on the LATCH
pin to change if in latch mode. When the output
current reaches the maximum sourcing current level,
the output device appears as a current source.
ORDERING INFORMATION
TJPACKAGED DEVICES
DIP (J) DIP (N) SOIC (D)
–40°C to 85°C UCC2917J UCC2917N UCC2917D
0°C to 70°C UCC3917J UCC3917N UCC3917D
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the Copyright ©2000–2011, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
PRODUCTPREVIEW
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
MIN MAX
Supply (2) 20 mA
Output Current SHTDWN, LATCH, VREF (2) –500 µA
Line Current PLIM 10 mA
Input voltage MAXI VDD + 0.3 V
Junction temperature, TJ–55 150 °C
Storage temperature, Tstg –65 150 °C
Lead temperature (Soldering, 10 sec.) 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.colsep
(2) Currents are positive into, negative out of the specified terminal. Consult the Packaging section of the Interface Products Data Book (TI
Literature Number SLUD002) for thermal limitations and considerations of package.
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ELECTRICAL CHARACTERISTICS
0°C≤TA≤70°C for the UCC3917, –40°C to 85°C for the UCC2917, CCT = 4.7 nF, TA= TJ, all voltages are with respect to
VOUT, current is positive into and negative out of the specified terminal, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
IDD Supply current(1) From VOUT 4.0 5 11 mA
UVLO turn on threshold 7.9 8.8 9.7 V
UVLO off voltage 5.5 6.5 7.5 V
VSS regulator voltage –6–5–4 V
FAULT TIMING
TA= 25°C 47.5 50 53 mV
Overcurrent threshold Over operating temperature 46 50 54 mV
Overcurrent input bias 50 500
CT charge current bias VCT = 1 V –78 –50 –28 µA
CT catastrophic fault threshold 3.4 4.5 V
CT fault threshold 2.25 2.5 2.75 V
CT reset threshold 0.32 0.5 0.62 V
D Output duty cycle Fault condition 1.7% 2.7% 3.7%
OUTPUT
IOUT = 0 6 8 10
VOH High-level output voltage V
IOUT =–100 µA 5 7 9
IOUT = 500 µA 0.03 0.50
VOL Output low voltage V
IOUT = 1 mA 0.6 0.9
LINEAR CURRENT
VMAXI = 100 mV 85 100 115 mV
Sense control voltage VMAXI = 400 mV 370 400 430 mV
IBIAS Input bias current VMAXI = 200 mV 50 500 nA
SHUTDOWN
Shutdown threshold 2.0 2.4 2.8 V
Input current VSHTDWN = 0 V 24 40 60 µA
Shutdown delay 100 500 ns
LATCH
VLATCH Latch threshold 1.7 2 2.3 V
Input current VLATCH = 0 V 24 40 60 µA
FLTOUT
Fault output high VCT = 0 V, ISOURCE = 0 µA 6 8 10 V
Fault output low VCT = 5 V, ISINK = 200 µA 0.01 0.05 V
POWER LIMITING
VSENSE regulator voltage IPLIM = 64 µA 4.5 5. 5.5 V
IPLIM = 64 µA 0.6% 1.2% 1.7%
Duty cycle control IPLIM = 1 mA 0.045% 0.1% 0.2%
VREF/CATFLT
VREF regulator voltage 4.5 5. 5.5 V
Fault output low IVREF/CATFLT = 5 mA 0.22 0.50 V
ISINK Output sink current VCT = 5 V, VVREF/CATFLT = 5 V 15 40 70 mA
Overload comparator threshold Relative to MAXI 110 200 290 mV
(1) Set by user using the RSS resistor.
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PRODUCTPREVIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LATCH
VREF/
MAXI
VDD
SHTDWN
FLTOUT
CT
VSS
CATFLT
PLIM
SENSE
OUTPUT
VOUT
C2N
C2P
C1N
C1P
2
3
4
5
6
710
11
12
13
14
15
LATCH
VREF/
MAXI
VDD
SHTDWN
FLTOUT
CT
VSS
PLIM
SENSE
OUTPUT
VOUT
C2N
C2P
C1N
C1P
1
8 9
16
CATFLT
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
D PACKAGE J, N PACKAGE
16 PINS 16 PINS
(TOP VIEW) (TOP VIEW)
DEVICE INFORMATION
PIN DESCRIPTIONS
PIN I/O DESCRIPTION
NAME NO.
I
C1N 7 Negative side of the upper charge-pump capacitor.
C1P 8 I Positive side of the upper charge-pump capacitor.
C2N 5 I Negative side of the lower charge-pump capacitor.
C2P 6 I Positive side of lower charge-pump capacitor.
A capacitor is connected to this pin to set the fault time. The fault time must be more than the time to charge
CT 10 I the external load capacitance (see application information).
Provides fault output indication. Interface to this pin is usually performed through level-shift transistors.
Under a non-fault condition, FLTOUT is pulled to a high state. When a fault is detected by the fault timer or
FLTOUT 11 O the undervoltage lockout, this pin is driven to a low state, indicating the output N-channel MOSFET is in the
off state.
Pulling this pin low causes a fault to latch until this pin is brought high or a power-on reset is attempted.
However, pulling this pin high before the reset time is reached does not clear the fault until the reset time is
LATCH 16 I reached. Keeping LATCH high results in normal operation of the fault timer. Users should note there is an
R-C delay dependent upon the external capacitor at this pin.
Programs the maximum-allowable sourcing current. Since VREF/CATFLT is a regulated voltage, a voltage
divider can be derived to generate the program level for MAXI. The current level at which the output
appears as a current source is equal to the voltage on MAXI divided by the current-sense resistor. If
MAXI 14 I desired, a controlled current start-up can be programmed with a capacitor on MAXI (to VOUT), and a
programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an
RC network.
OUTPUT 3 O Gate drive to the N-channel MOSFET pass element.
This feature ensures that the average external N-channel MOSFET power dissipation is controlled. A
resistor is connected from this pin to the drain of the external N-channel MOSFET pass element. When the
PLIM 1 I voltage across the N-channel MOSFET exceeds 5 V, current flows into PLIM, which adds to the fault timer
charge current, reducing the duty cycle from the 3% level.
Input voltage from the current-sense resistor. When there is greater than 50 mV across this pin with respect
SENSE 2 I to VOUT, a fault is sensed, and the CCT capacitor starts to charge.
This pin provides shutdown control. Interface to this pin is usually performed through level-shift transistors.
SHTDWN 12 I When shutdown is driven low, the output disables the N-channel MOSFET pass device.
VOUT 4 I Ground reference for the device.
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12
11
8
7
6
5
10
4
2
3
1
13 16
9 15 14
+
–
5 V
+
–
VOUT
Disable
Output Low
On-Time
Delay
VDD
40 mA
VOUT
UVLO
>10 V = Enable
< 6 V = Disable
5 V
Reference
Logic
Supply
10 V
5 V
SHTDWN
FLTOUT
C1P
C1N
C2P
C2N
VSS VREF/CATFLT MAXI
CT
VOUT
SENSE
OUTPUT
PLIM
LATCHVDD
+
200 mV
OC
+
–
+
–
+
50 mV
+
–
4 V
+
40 mA
VOUT
VDD
VDD
UDG-99055
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
PIN DESCRIPTIONS (continued)
PIN I/O DESCRIPTION
NAME NO.
Power to the device is supplied by an external current-limiting resistor on initial power up or if the load is
shorted. As the load voltages rises (VOUT), a small amount of power is drawn from VOUT by an internal
VDD 13 I charge pump. The charge pump's input voltage is regulated by an on-device 5-V zener. Power to VDD is
supplied by the charge pump under normal operation (i.e., external FET is on).
This pin primarily provides an output reference for the programming of MAXI. Secondarily, it provides
catastrophic fault indication. In a catastrophic fault, when the device unsuccessfully attempts to shutdown
VREF/CATFLT 15 O the N-channel MOSFET pass device, this pin pulls to a low state when CT charges above the catastrophic
fault threshold. A possible application for this pin is to trigger the shutdown of an auxiliary FET in series with
the main FET for redundancy.
VSS 9 I Negative reference out of the device. This pin is normally current fed via a resistor to load ground.
FUNCTIONAL BLOCK DIAGRAM
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PRODUCTPREVIEW
( )
IN VOUT
PL
PL
V V
IR
-
=
S Q
QR
+
–
+
–
I3
1 mA
+
–
2.5 V
0.5 V
I3
50 mA
I2
1.5 mA
10
+
SENSE
MAXI
0.2 V
Overload
H = Close
+
–
+
–
4
2
1
+
RSENSE
IPL
H = Close Fault
Latch OUTPUT
Drive
H = Off
Fault
Reset
VOUT
CCT
CT
OC
PLIM Ampllifier
PLIM
SENSE
VOUT
50 mV
To
Load
OUTPUT
RPL
VIN
VOUT
5 V
+
UGD-00073
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
APPLICATION INFORMATION
FAULT TIMING
Figure 1 shows the detailed circuitry for the fault timing function of the UCC3917. For simplicity, first consider a
typical fault mode where the overload comparator and the current source I3 do not come into play. A typical fault
occurs once the voltage across the current-sense resistor, RS, exceeds 50 mV. This causes the overcurrent
comparator to trip and the timing capacitor to charge with current source I1 plus the current from the power
limiting amplifier, or PLIM amplifier. The PLIM amplifier is designed to only source current into the CT pin once
the voltage across the output FET exceeds 5 V. The current IPL is related to the voltage across the FET as
shown in Equation 1.
(1)
Figure 1. Fault Timing Circuitry for the UCC3917, Including Power Limit and Overload
NOTE
Under normal fault conditions where the output current is slightly above the fault level,
VVOUT ≅VIN, IPL = 0, and the CCT charging current is I1.
During a fault, CCT charges at a rate determined by the internal charging current and the external timing
capacitor, CT. Once CCT charges to 2.5 V, the fault comparator switches and sets the fault latch. Setting the fault
latch causes both the output to switch off and the charging switch to open. CT must now discharge with current
source I2 until 0.5 V is reached. Once the voltage at CCT reaches 0.5 V, the fault latch resets (assuming LATCH
is high, otherwise the fault latch does not reset until the LATCH pin is brought high or a power-on reset occurs).
This re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still
present, the overcurrent comparator closes the charging switch causing the cycle to repeat.
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PRODUCTPREVIEW
m
= =
- + m
2
PL 1 PL
I1.5 A
DI I I 50 A
( ) ( ) ( )
IN VOUT MAXI IN VOUT MAXI
FET avg PL
1.5 A
P V V I D V V I I 50 A
m
= - ´ ´ = - ´ ´ + m
( )
IN VOUT
PL
PL
V V
IR
-
=
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Under a constant fault the duty cycle is shown in Equation 2.
where
•IPL is 0 µA under normal operations (see Figure 2) (2)
However, during large transients average power dissipations can be limited using the PLIM pin. The average
dissipation in the pass element is shown in Equation 3.
where
•both Equation 4 and Equation 5 are true (3)
(4)
(5)
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t0t1t2t3t4t5t6t7t8t9t10
VOUT
VIN
0 V
2.5 V
0.5 V
0 V
IFAULT
IOUT(nom)
IMAXI
Timing capacitor
(CCT) voltage
(w/r/t VOUT)
VCT
IOUT
VOUT
(w/r/t GND)
UDG-99147
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
Figure 2. Typical Timing Diagram
Table 1. Timing Stages
TIME CONDITION DESCRIPTION
t0 Safe condition Output current is nominal, output voltage is at the positive rail, VIN
Fault control
t1 Output current rises above the programmed fault value, CTbegins to charge with approximately 50 µA
reached
Maximum current
t2 Ooutput current reaches the programmed maximum level and becomes a constant current with value IMAX.
reached
CCT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VOUT
t3 Fault occurs discharges to ground
CThas discharged to 0.5 V, but fault current is still exceeded, CTbegins charging again, FET is on, VVOUT
t4 Retry rises to VIN.
t5 t5 = t3 This Illustrates 3% duty cycle.
t6 t6 = t4
Output short if VOUT is short circuited to ground, CTcharges at a higher rate depending upon the values for VIN and
t7 circuit RPL.
t8 Fault occurs Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted.
t9 Fault remains Output short circuit released, still in fault mode.
t10 t10 = t0 Fault released, safe condition –return to normal operation of the circuit breaker.
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( )
PL
IN VOUT
1.5 A R
DV V
m ´
=-
( ) ( ) ( )
PL
IN VOUT MAXI MAXI PL
FET avg IN VOUT
1.5 A R
P V V I I 1.5 A R
V V
m ´
= - ´ ´ = ´ m ´
-
( )
=´ m
FET avg
PL
MAX
P
RI 1.5 A
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
25
0 30 60 90 120 150 180 210
MOSFET Voltage (Output Shorted) (V)
Average Power (W)
RPL = ∞
RPL = 10 MΩ
RPL = 5 MΩ
RPL = 2 MΩ
RPL = 1 MΩ
RPL = 500 kΩ
RPL = 200 kΩ
G000
= ´
OVERLOAD MAX
S
200mV
I I R
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Note that t6 –t5 ≅36 ×(t5 –t4).
and where IPL >> 50 µA, the duty cycle can be approximated in Equation 6.
(6)
Therefore the average power dissipation in the MOSFET can be approximated by Equation 7.
(7)
Notice that since (VIN –VVOUT) cancels, average power dissipation is limited in the N-channel MOSFET pass
element (see Figure 3). Also, a value for RPL can be approximated by using Equation 8.
(8)
Figure 3.
OVERLOAD COMPARATOR
The overload comparator provides protection against a shorted load during normal operation when the external
N-channel FET is fully enhanced. Once the FET is fully enhanced the linear current amplifier essentially
saturates and the system is in effect operating open loop. Once the FET is fully enhanced the linear current
amplifier requires a finite amount of time to respond to a shorted output possibly destroying the external FET.
The overload comparator is provided to quickly shutdown the external MOSFET in the case of a shorted output
(if the FET is fully enhanced). During an output short, CTis charged by I3 at ≈1 mA. The current threshold for
the overload comparator is a function of IMAX and a fixed offset and is defined as:
(9)
WHen the overcurrent comparator trips, the UCC3917 enters a programmed fault mode (hiccup or latched). It
should be noted that on subsequent retries during hiccup mode or if a short should occur when the UCC3917 is
actively limiting the current, the output current does not exceed IMAX. In the event that the external FET does not
respond during a fault the UCC3917 sets the VREF/CATFLT pin low to indicate a catastrophic failure.
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( )
LOAD IN
START
MAX LOAD
C V
tI I
´
=-
æ ö
= ´ ´ ´ -
ç ÷
´
è ø
IN
START LOAD LOAD
MAX LOAD
V
t R C ln 1 I R
( ) ´
=CH START
T min CT
I t
CdV
( )
( ) LOAD LOAD
t
R C
IN MAX LOAD
CH
T min PL CT
V I R 1 e
dt
C I R dV
æ ö
-
ç ÷
´
è ø
æ ö
é ù
ç ÷
ê ú
- ´ ´ -
ç ÷
ê ú
ç ÷
ê ú
ç ÷
ë û
= + ´
ç ÷
ç ÷
ç ÷
ç ÷
ç ÷
è ø
( ) ( ) ( )
( )
CH PL IN MAX LOAD START IN LOAD LOAD
T min PL CT
1
C I R V I R t V R C
R dV
é ù
= ´ ´ + - ´ ´ + ´ ´
ë û
´
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
SELECTING THE MINIMUM TIMING CAPACITANCE
To ensure that the device starts up correctly the designer must ensure that the fault time programmed by CT
exceeds the startup time of the load. The startup time (tSTART) is a function of several components; load
resistance and load capacitance, soft-start components R1, R2 and CSS, the power limit current contribution
determined by RPL, and CIN.
Use Equation 10 to calculate the start time using a parallel capacitor-constant current load.
(10)
Use Equation 11 to calculate calculate the start time using a parallel R-C load.
(11)
If the power limit function is not be used, then CCT(min) can be found using Equation 12.
where
•dVCT is the hysteresis on the fault detection circuitry (12)
During operation in the latched fault mode configuration dVCT = 2.5 V. When the UCC3917 is configured for the
hiccup or retry mode of fault operation dVCT = 2.0 V.
If the power limit function is used, the CCT charging current becomes a function of ICH + IPL. CCT(min) is found by
integrating Equation 13 with respect to VCT.
(13)
The minimum timing capacitance is calculated in Equation 14.
(14)
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=
SENSE
FAULT
50mV
RI
( )
æ ö
-
=ç ÷
ç ÷
è ø
IN
SS
DD
V 5 V
RI
( )
æ ö
-
=ç ÷
ç ÷
è ø
IN
DD
DD
V 10 V
RI
R2
R1
C1
+
VREF 15
14MAXI
4VOUT
UDG-00017
R3
Q1
R2
R1
C1
+
VREF 15
14MAXI
4VOUT
Q1
UDG-11278
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
SELECTING OTHER EXTERNAL COMPONENTS
Other external components are necessary for correct operation of the device. Referring to Figure 13, resistors
RSENSE, RSS, RDD, R17, R18, and R19 and Equation 15 theough Equation 17 apply:
(15)
(16)
(17)
(R17 + R18 + R19) >20 kΩ(current limit out of VREF)
Use a value of 0.1 µF for the external charge pump capacitors.
SOFT-START OPERATION
The soft-start circuits in Figure 4, and Figure 5 gradually ramp up the load current on power-up, retry, or if the
SHTDWN pin is pulled high. Control circuitry (not shown) turns on Q1 to discharge C1 when FLTOUT or
SHTDWN are low (i.e., external power MOSFET is off) so the load current always ramps from zero. The circuit in
Figure 4 uses an inexpensive bipolar transistor for Q1 so the component cost is lower than the circuit in Figure 5.
Figure 4. Soft-Start Circuit Using A Higher-Cost Figure 5. Soft-Start Circuit Using A Lower-Cost
Bi-Polar Transistor MOSFET
Soft-start operation minimizes the voltage disturbance on the power bus when a circuit card is inserted into a live
back plane. This disturbance could reset a system, which is not desirable when high availability is required. A
server is an example of a high availability system.
Soft-start operation is initiated with the SHTDWN pin in as shown in Figure 6. The anode of D2 is grounded
when the card is in the back plane. R2 limits the SHTDWN pin current to between 60 µA and 500 µA (i.e., 60 µA
<0.65 V / R2 <500 µA).
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U1
UCC3917
13 VDD
8 C1P
7 C1N
6 C2P
5 C2N
11 FLOUT
12 SHTDWN
16 LATCH
1PLIM
3OUTPUT
2SENSE
15VREF/CATFLT
14MAXI
10CT
4VOUT
9VSS
D2
RDD
R1
Q1
D1
R2
D2
RGR
Z
Back PlanePlug-In Card
VIN
GND
Short Pin
UDG-00019
IN
1 kW
GND
4N25
SHTDWN
UDG-11202
VOUT
4
12
LATCH
16
1 kW
4N25
SHTDWN
UDG-11202
VOUT
4
12
LATCH
16
IN
GND
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
Figure 6. Soft-Start Operation with SHTDWN
I/O INTERFACE
The SHTDWN and LATCH inputs and FLTOUT output are referenced to VOUT. Level-shifting circuits are
needed if the device communicates with logic that is referenced to load/system ground.
INTERFACING TO LATCH AND SHTDWN
Two level shift circuits for LATCH and SHTDWN are shown in Figure 7. The optocoupler (Figure 7) is simple, but
the constant-current sink (Figure 8) is a low-cost solution.
Figure 7. Optocoupler Interface Figure 8. Constant-Current Sink Interface
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( ) æ ö
- ´ < ¾¾® >
ç ÷
+
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2 1
B BE
IL max 1 2 2
R R
V V V 0.23
R R R
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2 1
B BE
IL max 1 2 2
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V V V 0.23
R R R
( )
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CE sat
C
3
1.7 V V
I 500 A R3 3.2k
R
( )
= + < ¾¾® <
C E E
CE sat
V V V 1.7 V V 1.6 V
( )
= - < ¾¾® <
E B BE B
V V V 1.6 V V 2.25 V
( )
()
- ´ < ¾¾® >
+
B 2
IH max 1
1 2 2
V V R R
2.25 V 1.222
R R R
( )
()
( )
2
IH min
B
1 2 1
2
V R 2 V
VR R R
1R
´
= ¾¾®
+æ ö
+ç ÷
è ø
( ) ( )
- -
= > m ¾¾® < m
B BE B BE
C 3
3
V V V V
I 60 A R
R 60 A
>
1
2
R1.222
R
( )
-
W < < =
mæ ö
+ç ÷
è ø
B
3 B
1
2
V 0.65 2 V
3.2k R , where V
60 A R
1R
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Design Example 1: Using the TTL Signal to Control the LATCH Pin Input
A TTL signal controls the LATCH input of the UCC3917 using the circuit in Figure 8. Determine the component
values if the maximum load voltage is 60 V.
The assumptions for this analysis are:
•VBE ≈0.65 V
•VCE(sat) ≈0.1 V
•R1||R2 << hfe ×R3
•Voltage measurements are with respect to load ground
Calculation Steps
Step 1. Select Q1.
The LATCH input is internally pulled up to the charge pump voltage, which is 10 V above the load voltage. Q1 is
therefore subjected to 70 V in a 60 V system. A FMMTA06 transistor, with a VCEO(max) of 80 V, is suitable for Q1
in this application.
Step 2. Determine R1, R2 and R3.
The interface circuit responds to a TTL input as follows.
•Logic "0" input: 0 V <VIL <0.8 V ⇒0µA<IC<60 µA and VC>1.7 V
•Logic "1" input: 2 V <VIH <5 V ⇒60 mA <IC<500 µA and VC<1.7 V
This response establishes the relationship between R1, R2, and R3.
If VIN = VIL(max) = 0.8 V, then Q1 is off and
If VIN = VIH(max) = 5 V, then:
If VIN = VIH(max) = 2 V, then:
In summary, R1, R2, and R3 obey the inequalities:
and
If R1 / R2 = 1.3, then 3.2 kΩ < R3 <3.66 kΩ. R1 = 4.64 kΩfor the case where R2 = R3 = 3 kΩ.
The same design can be used to control the UCC3917's SHTDWN input.
Copyright ©2000–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
R3
Q1
R2
R4
R1
13 VDD
11 FLTOUT
UDG-00022
FLTOUT
GND
( ) ( ) ( )
E
C on CE sat
V V V 2.4 V TTL output high= + >
( ) ( )
( )
E
C on
If V 2.6 V, then V 2.6 V 0.1V 2.5 V= = + - =
( ) ( ) ( )
---
= = = = W
m
E E
3
E C
6 V V 6 V V 6 V 2.5V
R 35k
I I 100 A
( )
B E BE
V V V 2.5 V 0.65 V 1.85 V= + = - =
( ) ( ) ( )
´ @ - =
+ -
2 1
B
1 2 2 B
R R 6 V
6 V 6 V V or
R R R V 1
´=
13
2
Rhfe R
R
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
Interfacing to FLTOUT
The level shift circuit in Figure 9 is a way to interface to FLTOUT. The operation of this circuit and the SHTDWN /
LATCH level shift circuit in Figure 8 are similar.
Design Example 2: A TTL-Compatible Output Level Shifter Using FLOUT
This design example describes a TTL compatible output level shifter for FLTOUT. The maximum system voltage
is 60 V.
Use a level shift circuit as shown in Figure 9. The FLTOUT output can swing to the charge pump voltage, which
is 10 V above the load voltage. In a 60-V application, the collector-emitter of Q1 can be as high as –70 V. A
FMMT593 transistor, with a VCEO(max) rating of –100 V, is a suitable choice for Q1.
Figure 9. Interfacing to FLTOUT
Calculation Steps
Step 1. Output saturation voltage constraint.
(18)
(19)
Step 2. Source current constraint.
IC= 100 µA
Step 3. Calculate the value of R3.
(20)
Step 4. Calculate the base voltage.
(21)
Step 5. Calculate the voltage divider.
The voltage divider formula for R1 and R2 is shown in Equation 22
(22)
Equation 23 assumes negligible loading by Q1.
(23)
14 Submit Documentation Feedback Copyright ©2000–2011, Texas Instruments Incorporated
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
( ) ( )
æ ö
= = << ´ W =
ç ÷
ç ÷
-
è ø
1 1
2 2
R R
62.24 and 100 35k 3.5M
R 1.85 1 R
´ > > = W
m
C 4 4
2.4 V
I R 2.4 V, R 24 k
100 A
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
If hfe = 100, then:
(24)
If R2 = R3 = 34.8 kΩ, then R1 = 15.4 kΩ
Step 6. Calculate the output voltage.
The output voltage is set by R4.
(25)
Choose an R4 value of 49.9 kΩ.
Copyright ©2000–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
RDD
RSS
LOAD
Sneak Path
GND
VOUT
UCC3917
VDD
VSS
OUTPUT
VOUT
+
–
10 V
5 V
UDG-00021
VIR
GND
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
PRELOADING THE OUTPUT
RDD provides a sneak path for current between 3 mA and 11 mA (e.g., at 0 V output) to trickle into the load when
the power FET is off (see Figure 10).
Figure 10. Simplified Schematic Illustrating IDD Sneak Path
This current causes an unacceptably high output voltage at shutdown if the output is not adequately loaded. In
this case, it is necessary to preload the HSPM output to keep the shutdown voltage level acceptable. The
preload also insures reliable start-up of the UCC3917 by holding the output voltage low when power is first
applied to the HSPM.
A resistor is usually an unacceptable preload because it creates a power dissipation problem when the FET turns
on. For example, a 90.9-Ωpreload (used to limit the shutdown voltage of a 48-V HSPM to less than 1 V) adds
25-W of power dissipation to the system. In a 100-V system, this dissipation increases to 110 W. The power
dissipation overhead increases with the system voltage squared for a resistive preload.
16 Submit Documentation Feedback Copyright ©2000–2011, Texas Instruments Incorporated
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
Q3
4 VOUT
Q1
R1
R2
R3R4
TAPER –
VIN
Q2
UDG-00024
( ) = >
BE
SNKFET off 1
V
I 11A
R
( ) ( )
æ ö
æ ö
æ ö
= - ´ ç ÷
ç ÷
ç ÷
ç ÷ ç ÷
´
è ø
è ø è ø
BE 2
OUT
SNKFET on 11 3
V R
I V
RR R
( ) ( )
æ ö
= ´
ç ÷ ´
è ø
2
3
BE
D max Q1 1 2
R
V
P2 R R
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Figure 11 shows how the active load limits the shutdown voltage without creating a power dissipation problem.
Figure 11. Active Preload
This load is a constant-current sink (i.e., Q3 is off) when the power FET is off. The shutdown voltage is less than
0.85 V if the sink current, set by R1, is greater than 11 mA.
(26)
The power dissipation of Q1 is kept to a minimum when the power FET turns on by tapering the sink current as
the load voltage rises as shown in Equation 27 .
(27)
For R1 << R2 << R3
Control circuitry turns on Q3 to activate current tapering. Tapering the current causes the power dissipation of Q1
to peak when the load voltage is calculated in Equation 28.
(28)
The power dissipated by Q1 at this voltage is shown in Equation 29.
(29)
In the case of a brownout or if the input voltage rises slowly (e.g., adjustable lab power supply), it is possible for
Q1 to remain in the maximum power dissipation region for a significant time. Limiting the power dissipation of Q1
below its maximum rating insures reliable operation in this case.
Copyright ©2000–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
( )
= = = W
BE
1
SNKFET off
V0.65 V
R 46.4
I 14mA
( )
22
31D max Q1
2 BE
R2 2
R P 46.4 0.15 W 65.9
R V 0.65 V
æ ö æ ö
= ´ ´ = ´ W ´ =
ç ÷ ç ÷
è ø
è ø
0
0.1
0.2
0.3
0.4
0.5
0.6
0 5 10 15 20 25 30 35 40
Output Voltage (V)
Power Dissipation (W)
Constant Current
Tapered Current
R1 = 46.4 Ω
R2 = 3.01 k Ω
R2 =198 k Ω
G000
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
Design Example 3: A 14-mA Active Preload for a 60-V Hot Swap Power Manager (HSPM)
Calculation Steps
Step 1. Set the sink current.
(30)
Use a BC846B transistor for Q1. This device has a collector breakdown voltage of 65 V and power dissipation
rating of 225 mW.
Step 2. Select R2 and R3.
Select R2 and R3 to limit the power dissipation of Q1 to less than 225 mW, in this example 150 mW is chosen.
(31)
If R2 = 3.01 kΩ, then R3 = 198 kΩ.
The power dissipation of Q1 is shown in Figure 12.
Figure 12. Output Voltage vs. Power Dissipation
PROTECTING THE 5-V REGULAOR
The UCC3917's 5-V regulator can overvoltage if VOUT is loaded with less than 11 mA (min) on power up. The
overvoltage mechanism is best understood by recognizing that the 5-V Zener diode in the UCC3917 block
diagram, is actually a feedback shunt regulator. This regulator turns on when the voltage across the UCC3917's
10-V Zener diode is greater than the UVLO threshold. If VOUT is unloaded and power is applied to the
UCC3917, the UVLO threshold cannot be reached and the 5-V regulator impedance is infinite.
Consequently, the entire input voltage appears across the shunt regulator causing it to break down. Clamping its
voltage with Zener diode to 5.6 V can protect the regulator.
NOTE
The Zener diode is unnecessary if the current drawn from VOUT is greater than 11 mA
when power is initially applied to the UCC3917.
EVALUATION CIRCUIT EXAMPLE
A 28 V to 60 V at 1-A HSPM evaluation circuit is shown in Figure 13. Level translation circuitry allows
communications with logic referenced to load ground. This circuit is available as a DV3917 Evaluation Board.
Contact your local Texas Instruments sales representative for more information.
18 Submit Documentation Feedback Copyright ©2000–2011, Texas Instruments Incorporated
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
13
7
8
6
11
5
16
12
1
2
3
15
10
14
9
4
C7 0.1 mF
C8 0.1 mF
VDD
C1P
C1N
C2P
C2N
FLTOUT
SHTDWN
LATCH
PLIM
OUTPUT
SENSE
VREF/CATFLT
MAXI
CT
VOUT
VSS
C11
0.1 mF
VDD
D1
1N4148
R24
4.7 kW
1W
R23
200 kW
VIN Q1
JRF530S
C1
4.7 mF
100 V
J1
+
–
IN 2
1
C13 0.01 mF
C14 0.01 mF
D3
1N4148
D2
1N4148
R3
15.4 kW
R2
34.8 kW
Q2
FMMT593
R1
34.8 kW
P1
+
–
Fault 1
2
R4
49.9 kW*D4
BZX04C4V3ZX
4.3 V
Q3
FMMTA 06
R7
3.57 kW
R6
3.57 kW
Q4
FMMTA 06
R10
3.57 kW
R9
3.57 kW
R5
7.32 kW
R8
7.32 kW
P3
+
–
Remote
Latch
1
2
P2
+
–
Remote
Shutdown
1
2
R17 49.9 kW
R11
5.6 kW
1W
C9
0.1 mF
D5
BZX84C5V6
5.6V
R19
2 kW
R13
200 kW
Q5
MMBT 5809
Q6
FMMT593
R21
1 MW
R20
150 kW
VDD
R16
1 MW
TP1
GND
1
2
3
Q7
MMBT 5039
R12
200 kW
VIN
Q8
BC346B
R14
3.01 kW
R15
47 W
TP2
CS
123
R22 0.05
1W 2%
+–
C10
4.7 mF
100 V
+
J2
+
–OUT
2
1
C2 C3 C4 C5 C6
SS
1
2
3
4
567 8
C2-C6 0.22 mF
UCC3917
R18
49.9 kW
C12
10 mF
10 V
Q5
FMMT593
S6
S1
S2
S3
S4
S7
UDG-00025
UCC2917
UCC3917
www.ti.com
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
Figure 13. A 28 V to 60 V at 1-A Positive Floating HSPM Evaluation Circuit Using the UCC3917
Copyright ©2000–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): UCC2917 UCC3917
PRODUCTPREVIEW
UCC2917
UCC3917
SLUS203C –FEBRUARY 2000–REVISED FEBRUARY 2011
www.ti.com
SAFETY RECOMMENDATIONS
Although the UCC3917 is designed to provide system protection for all fault conditions, all integrated circuits can
ultimately fail short. For this reason, if the UCC3917 is intended for use in safety critical applications where UL or
some other safety rating is required, a redundant safety device such as a fuse should be placed in series with
the power device. The UCC3917 prevents the fuse from blowing for virtually all fault conditions, increasing
system reliability and reducing maintenance cost, in addition to providing the hot-swap benefits of the device.
20 Submit Documentation Feedback Copyright ©2000–2011, Texas Instruments Incorporated
Product Folder Link(s): UCC2917 UCC3917
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC2917D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2917DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2917DTR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2917DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2917N ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC2917NG4 ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3917D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3917DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3917DTR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3917DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3917N ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3917NG4 ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2011
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC2917DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
UCC3917DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2917DTR SOIC D 16 2500 367.0 367.0 38.0
UCC3917DTR SOIC D 16 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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