Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. D
05/09/12
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS65C256AL
IS62C256AL
FEATURES
Access time: 25 ns, 45 ns
Low active power: 200 mW (typical)
Low standby power
— 150 µW (typical) CMOS standby
— 15 mW (typical) operating
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
Lead-free available
Industrial and Automotive temperatures avail-
able
DESCRIPTION
The ISSI IS62C256AL/IS65C256AL is a low power,
32,768 word by 8-bit CMOS static RAM. It is fabricated
using ISSI's high-performance, low power CMOS tech-
nology.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62C256AL/IS65C256AL is pin compatible with
other 32Kx8 SRAMs in plastic SOP or TSOP (Type I)
package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
32K x 8 LOW POWER CMOS STATIC RAM
MAY 2012
2Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL
PIN CONFIGURATION
28-Pin SOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CONFIGURATION
28-Pin TSOP
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Select Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected XHXHigh-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
Integrated Silicon Solution, Inc. 3
Rev. D
05/09/12
IS65C256AL
IS62C256AL
OPERATING RANGE
Part No. Range Ambient Temperature VDD
IS62C256AL Commercial 0°C to +70°C 5V ± 10%
IS62C256AL Industrial –40°C to +85°C 5V ± 10%
IS65C256AL Automotive –40°C to +125°C 5V ± 10%
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.4 V
VOL Output LOW Voltage VDD = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.5 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND
VIN
VDD Com. –1 1µA
Ind. –2 2
Auto. –10 10
ILO Output Leakage GND
VOUT
VDD,Com. –1 1µA
Outputs Disabled Ind. –2 2
Auto. –10 10
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
4Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8pF
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 ns -45 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC1VDD Operating VDD = Max., CE = VIL Com. 15 15 mA
Supply Current IOUT = 0 mA, f = 0 Ind. 20 20
Auto. 25 25
ICC2VDD Dynamic Operating VDD = Max., CE = VIL Com. 25 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind.30 25
Auto. 35 30
typ.
(2)
15 12
ISB1TTL Standby Current VDD = Max., Com.100 100
µA
(TTL Inputs) VIN = VIH or VIL Ind.120 120
CE VIH, f = 0 Auto. 150 150
ISB2CMOS Standby VDD = Max., Com.15 15
µA
Current (CMOS Inputs) CE VDD – 0.2V, Ind.20 20
VIN VDD – 0.2V, or Auto. 50 50
VIN 0.2V, f = 0 typ.
(2)
5 5
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. 5
Rev. D
05/09/12
IS65C256AL
IS62C256AL
Figure 1. Figure 2.
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
AC TEST LOADS
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-25 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 25 45 ns
tAA Address Access Time 25 45 ns
tOHA Output Hold Time 22ns
tACS CE Access Time 25 45 ns
tDOE OE Access Time 13 25 ns
tLZOE(2) OE to Low-Z Output 00ns
tHZOE(2) OE to High-Z Output 012 020 ns
tLZCS(2) CE to Low-Z Output 33ns
tHZCS(2) CE to High-Z Output 012 020 ns
tPU(3) CE to Power-Up 00ns
tPD(3) CE to Power-Down 20 30 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
1838
100 pF
Including
jig and
scope
993
OUTPUT
5V
6Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA
t OHA
t RC
DOUT
ADDRESS
t RC
t OHA
t AA
t DOE
t LZOE
t ACS
t LZCS
t HZOE
HIGH-Z DATA VALID
ADDRESS
OE
CE
DOUT
t HZCS
CS_RD2.eps
Integrated Silicon Solution, Inc. 7
Rev. D
05/09/12
IS65C256AL
IS62C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-25 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 25 45 ns
tSCS CE to Write End 15 35 ns
tAW Address Setup Time to Write End 15 25 ns
tHA Address Hold from Write End 00ns
tSA Address Setup Time 00ns
tPWE1, WE Pulse Width 15 25 ns
tPWE2(4)
tSD Data Setup to Write End 12 20 ns
tHD Data Hold from Write End 00ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t WC
VALID ADDRESS
t SCS
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN DATAIN VALID
t LZWE
t SD
CS_WR1.eps
8Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL
AC WAVEFORMS
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(OE is LOW During Write Cycle)
(1)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
DATA UNDEFINED
t WC
VALID ADDRESS
LOW
LOW
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA t HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t LZWE
t SD
CS_WR3.eps
Integrated Silicon Solution, Inc. 9
Rev. D
05/09/12
IS65C256AL
IS62C256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.0 5.5 V
IDR Data Retention Current VDD = 2.0V, CE VDD – 0.2V Com. 15 µA
VIN VDD – 0.2V, or VIN
VSS + 0.2V
Ind. 20
Auto. 50
tSDR Data Retention Setup Time See Data Retention Waveform 0ns
tRDR Recovery Time See Data Retention Waveform tRC ns
Note:
1. Typical Values are measured at V
DD
= 5V, T
A
= 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (CECE
CECE
CE Controlled)
VDD
CE1 VDD - 0.2V
tSDR tRDR
VDR
CE1
GND
4.5V
2.2V
Data Retention Mode
10 Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns) Order Part No. Package
45 IS62C256AL-45T TSOP
IS62C256AL-45TL TSOP, Lead-free
IS62C256AL-45UL Plastic SOP, Lead-free
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed
(ns) Order Part No. Package
25 IS62C256AL-25TI TSOP
IS62C256AL-25ULI Plastic SOP, Lead-free
45 IS62C256AL-45TI TSOP
IS62C256AL-45TLI TSOP, Lead-free
IS62C256AL-45ULI Plastic SOP, Lead-free
ORDERING INFORMATION
Automotive Range: –40°C to +125°C
Speed
(ns) Order Part No. Package
25 IS65C256AL-25TA3 TSOP
IS65C256AL-25TLA3 TSOP, Lead-free
IS65C256AL-25ULA3 Plastic SOP, Lead-free
45 IS65C256AL-45TA3 TSOP
IS65C256AL-45TLA3 TSOP, Lead-free
IS65C256AL-45ULA3 Plastic SOP, Lead-free
Integrated Silicon Solution, Inc. 11
Rev. D
05/09/12
IS65C256AL
IS62C256AL
12 Integrated Silicon Solution, Inc.
Rev. D
05/09/12
IS65C256AL
IS62C256AL