1. General description
The 74ABT16240A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16240A is an inverting 16-bit buffer that is ideal for driving bus lines. The
device features four outpu t enab le inputs (1OE, 2 OE, 3OE, 4OE), each controlling four of
the 3-state outputs.
2. Features and benefits
16-bit bus interfa ce
Multiple VCC and GND pins minimize switching noise
Power-up 3-state
3-state buffers
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA and 32 mA
Live insertion an d ex tra ct i on perm i tte d
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD-A114E exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
3. Ordering information
74ABT16240A
16-bit inverting buffer/line driver; 3-state
Rev. 6 — 3 November 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ABT16240ADGG 40 C to +85 C TSSOP48 plastic thin shrink small outli ne package; 48 leads;
body width 6.1 mm SOT362-1
74ABT16240ADL 40 C to +85 C SSOP48 plastic shrink small outline package; 48 leads; body
width 7.5 mm SOT370-1
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 2 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aad261
47
46
44
43
2
3
5
6
1A0
1A1
1A2
1A3
1Y0
1Y1
1Y2
1Y3
11OE 3OE
36
35
33
32
13
14
16
17
3A0
3A1
3A2
3A3
3Y0
3Y1
3Y2
3Y3
25
30
29
27
26
19
20
22
23
4A0
4A1
4A2
4A3
4Y0
4Y1
4Y2
4Y3
24 4OE2OE
41
40
38
37
8
9
11
12
2A0
2A1
2A2
2A3
2Y0
2Y1
2Y2
2Y3
48
11
1
1
1
3
2
4
001aad262
33
32
30
29
27
26
16
17
19
20
22
23
47
46
44
43
41
40
38
37
36
35
2
3
5
6
8
9
11
12
13
14
24
25
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
48
1
4OE
1OE
2OE
3OE
EN1
EN2
EN3
EN4
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 3 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration
74ABT16240A
1OE 2OE
1Y0 1A0
1Y1 1A1
GND GND
1Y2 1A2
1Y3 1A3
VCC VCC
2Y0 2A0
2Y1 2A1
GND GND
2Y2 2A2
2Y3 2A3
3Y0 3A0
3Y1 3A1
GND GND
3Y2 3A2
3Y3 3A3
VCC VCC
4Y0 4A0
4Y1 4A1
GND GND
4Y2 4A2
4Y3 4A3
4OE 3OE
001aaj891
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Table 2. Pin description
Symbol Pin Description
1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 output enable (LOW active)
1Y0, 1Y1, 1Y2, 1Y3 2, 3, 5, 6 1 data output
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 supply voltage
2Y0, 2Y1, 2Y2, 2Y3 8, 9, 11, 12 2 data output
3Y0, 3Y1, 3Y2, 3Y3 13, 14, 16, 17 3 data output
4Y0, 4Y1, 4Y2, 4Y3 19, 20, 22, 23 4 data output
4A0, 4A1, 4A2, 4A3 30, 29, 27, 26 4 data input
3A0, 3A1, 3A2, 3A3 36, 35, 33, 32 3 data input
2A0, 2A1, 2A2, 2A3 41, 40, 38, 37 2 data input
1A0, 1A1, 1A2, 1A3 47, 46, 44, 43 1 data input
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 4 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 3. Function table[1]
Control Input Output
nOE nAn nYn
LLH
LHL
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage [1] 1.2 +7.0 V
VOoutput voltage output in OFF - state or HIGH-state [1] 0.5 +5.5 V
IIK input clamping current VI < 0 V 18 - mA
IOK output clamping current VO < 0 V 50 - mA
IOoutput current output in LOW-state - 128 mA
output in HIGH-state - 64 mA
Tjjunction temperature [2] - 150 C
Tstg storage temperature 65 +150 C
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIinput voltage 0 - VCC V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level Input voltage - - 0.8 V
IOH HIGH-level output current 32--mA
IOL LOW-level output current - - 32 mA
duty cycle 50 %; fi 1 kHz --64mA
t/V input transition rise and fall rate - - 10 ns/V
Tamb ambient temperature in free air 40 - +85 C
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 5 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
9. Static characteristics
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %,
a transition time of up to 100 s is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.
[4] This data sheet limit may vary among suppliers.
Table 6. Static characteristics
Symbol Parameter Conditions 25 C40 C to +85 CUnit
Min Typ Max Min Max
VIK input clamping voltage VCC = 4.5 V; IIK =18 mA 1.2 0.9 - 1.2 - V
VOH HIGH-level outp ut
voltage VI = VIL or VIH
VCC = 4.5 V; IOH =3 mA 2.5 2.9 - 2.5 - V
VCC = 5.0 V; IOH =3 mA 3.0 3.4 - 3.0 - V
VCC = 4.5 V; IOH =32 mA 2.0 2.4 - 2.0 - V
VOL LOW-level output
voltage VCC = 4. 5 V; IOL =64mA;
VI=V
IL or VIH
- 0.42 0.55 - 0.55 V
IIinput leakage current VCC = 5.5 V; VI=V
CC or GND - 0.01 1.0 - 1.0 A
IOFF power-off leakage
current VCC = 0 V; VI or VO 4.5 V - 5.0 100 - 100 A
IO(pu/pd) power-up/power-down
output current VCC = 2.0 V; VO=0.5V;
VI=GNDor V
CC; nOE =HIGH [1] -5.0 50 - 50 A
IOZ OFF-state output
current VCC = 5.5 V; VI = VIL or VIH
output HIGH-state at VO = 5.5 V - 1.0 10 - 10 A
output LOW-state at VO = 0.5 V - 1.0 10 - 10 A
ILO output leakage current HIGH-state; VO=5.5V;
VCC =5.5V; V
I=GNDor V
CC
-1.050 - 50A
IOoutput current VCC = 5.5 V; VO = 2.5 V [2] 180 70 50 180 50 mA
ICC supply current VCC = 5.5 V; VI = GND or VCC
outputs HIGH-st a te - 0.5 1.0 - 1.0 mA
outputs LOW-st ate - 8 19 - 19 mA
outputs 3-state - 0.5 1.0 - 1.0 mA
ICC additional supply
current per input pin; VCC = 5.5 V; one input
at 3.4 V and other inputs at VCC or
GND
[3][4] -10200 - 200A
CIinput capacitance VI = 0 V or VCC -4- - -pF
CI/O input/output
capacitance output s disabled; VO=0V orV
CC -6- - -pF
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 6 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V. For test circuit, see Figure 6.
Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +85 C;
VCC = 5.0 V 0.5 V Unit
Min Typ Max Min Max
tPLH LOW to HIGH
propagation delay nAn to nYn, see Figure 4 1.0 2.0 3.0 1.0 3.7 ns
tPHL HIGH to LOW
propagation delay nAn to nYn, see Figure 4 1.0 1.5 3.0 1.0 3.5 ns
tPZH OFF-state to HIGH
propagation delay nOE to nYn; see Figure 5 1.2 2.4 3.3 1.2 4.2 ns
tPZL OFF-state to LOW
propagation delay nOE to nYn; see Figure 5 1.2 2.3 3.2 1.0 4.2 ns
tPHZ HIGH to OFF-state
propagation delay nOE to nYn; see Figure 5 1.3 2.7 4.1 1.6 4.7 ns
tPLZ LOW to OFF-state
propagation delay nOE to nYn; see Figure 5 1.3 2.5 3.6 1.4 4.1 ns
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 7 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
11. Waveforms
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 4. Input (nAn) to output (nYn) propagation delay
input nAn
output nYn
V
M
t
PLH
t
PHL
V
M
V
M
V
M
001aaj028
V
OH
V
I
V
OL
0 V
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. 3-state output enable and disable times
001aaj892
VI
VM
VMVOL + 0.3 V
VOH − 0.3 V
VM
tPZL
tPZH
tPLZ
tPHZ
GND
3.5 V
VOL
VOH
0 V
nOE input
nYn output
nYn output
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 8 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
12. Test information
VM=1.5V
a. Input pulse definition
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination re sistance should be equal to output impedance Zo of the pulse generator.
b. Test circuit for 3-state outputs
Fig 6. Load circuitry for switching times
001aai298
VMVM
tW
tW
10 %
90 % 90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
90 %
10 % 10 %
tf
tr
tr
tf
001aac764
V
CC
V
I
V
O
V
EXT
RTRL
RL
CL
PULSE
GENERATOR DUT
Table 8. Test data
Input Load VEXT
VIfitWtr, tfCLRLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open 7.0 V open
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 9 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
13. Package outline
Fig 7. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 10 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
Fig 8. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 11 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
14. Abbreviations
15. Revision history
Table 9. Abbreviations
Acronym Description
BiCMOS Bipolar CMOS
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
CDM Charged Device Mo del
TTL Transistor-Transistor Logic
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ABT16240A v.6 20111103 Product data sheet - 74ABT16240A v.5
Modifications: •Legal pages updated
74ABT16240A v.5 20100525 Product data sheet - 74ABT16240A v.4
74ABT16240A v. 4 20090325 Produ ct data sheet - 74ABT16240A v.3
74ABT16240A v.3 20040212 Product specification 01-A15420 74ABT_H16240A v.2
74ABT_H16240A v.2 19980225 Product specification 853-1880 19019 74ABT_H16240A
74ABT_H16240A 19961001 Product specification - -
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 12 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 13 of 14
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automo tive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting fr om customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ABT16240A
16-bit inverting buffer/line driver; 3-state
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 November 2011
Document identifier: 74ABT16240A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
17 Contact information. . . . . . . . . . . . . . . . . . . . . 13
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
