© Semiconductor Components Industries, LLC, 2012
January, 2012 − Rev. 8
1Publication Order Number:
NLSV1T34/D
NLSV1T34
1-Bit Dual-Supply
Non-Inverting Level
Translator
The NLSV1T34 is a 1−bit configurable dual−supply voltage level
translator. The input An and output Bn ports are designed to track two
different power supply rails, VCCA and VCCB respectively. Both
supply rails are configurable from 0.9 V to 4.5 V allowing universal
low−voltage translation from the input An to the output Bn port.
Features
•Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V
•High−Speed w/ Balanced Propagation Delay
•Inputs and Outputs have OVT Protection to 4.5 V
•Non−preferential VCCA and VCCB Sequencing
•Power−Off Protection
•Power−Off High Impedance Inputs and Outputs
•Ultra−Small Packaging: 1.45 mm x 1.0 mm ULLGA6
2.0 mm x 2.1 mm SC−88A
1.2 mm x 1.0 mm UDFN6
1.45 mm x 1.0 mm UDFN6
•These are Pb−Free Devices
Typical Applications
•Mobile Phones, PDAs, Other Portable Devices
Important Information
•ESD Protection for All Pins:
HBM (Human Body Model) > 3000 V
Figure 1. Logic Diagram
VCCA VCCB
B
A
ULLGA6
MX1 SUFFIX
CASE 613AF
MARKING
DIAGRAMS
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PIN ASSIGNMENT
QM
ULLGA6/UDFN6
(Top View)
VCCB
NC
B
VCCA
A
GND
6
5
4
1
2
3
1
SC−88A
(SOT−353/SC−70)
DF SUFFIX
CASE 419A
1
5
1
5
Q M G
G
M
Q, A = Device Code
M = Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
SC−88A
(Top View)
VCCB
B
VCCA
A
GND
5
4
1
2
3
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
UDFN6
MU SUFFIX
CASE 517AA
M
G
1
UDFN6
MU SUFFIX
CASE 517AQ
A M
1
Q
NLSV1T34
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2
PIN ASSIGNMENT
PIN FUNCTION
VCCA Input Port DC Power Supply
VCCB Output Port DC Power Supply
GND Ground
AInput Port
BOutput Port
TRUTH TABLE
INPUTS OUTPUTS
A B
L L
H H
MAXIMUM RATINGS
Symbol Rating Value Condition Unit
VCCA, VCCB DC Supply Voltage −0.5 to +5.5 V
VIDC Input Voltage A −0.5 to +5.5 V
VODC Output Voltage (Power Down) B −0.5 to +5.5 VCCA = VCCB = 0 V
(Active Mode) B −0.5 to +5.5 V
IIK DC Input Diode Current −20 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
IODC Output Source/Sink Current ±50 mA
ICCA, ICCB DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current per Ground Pin ±100 mA
TSTG Storage Temperature −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCCA, VCCB Positive DC Supply Voltage 0.9 4.5 V
VIBus Input Voltage GND 4.5 V
VIO Bus Output Voltage (Power Down Mode) B GND 4.5 V
(Active Mode) B GND VCCB V
TAOperating Temperature Range −40 +85 °C
Dt / DVInput Transition Rise or Rate
VI, from 30% to 70% of VCC; VCC = 3.3 V ±0.3 V
0 10 nS
NLSV1T34
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3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions VCCA (V) VCCB (V)
−405C to +855C
Unit
Min Max
VIH Input HIGH Voltage 3.6 – 4.5 0.9 – 4.5 2.2 −V
2.7 – 3.6 2.0 −
2.3 – 2.7 1.6 −
1.4 − 2.3 0.65 * VCCA −
0.9 – 1.4 0.9 * VCCA −
VIL Input LOW Voltage 3.6 – 4.5 0.9 – 4.5 −0.8 V
2.7 – 3.6 −0.8
2.3 – 2.7 −0.7
1.4 − 2.3 −0.35 * VCCA
0.9 – 1.4 −0.1 * VCCA
VOH Output HIGH Voltage IOH = −100 mA; VI = VIH 0.9 – 4.5 0.9 – 4.5 VCCB – 0.2 −V
IOH = −0.5 mA; VI = VIH 0.9 0.9 0.75 * VCCB −
IOH = −2 mA; VI = VIH 1.4 1.4 1.05 −
IOH = −6 mA; VI = VIH 1.65 1.65 1.25 −
2.3 2.3 2.0 −
IOH = −12 mA; VI = VIH 2.3 2.3 1.8 −
2.7 2.7 2.2 −
IOH = −18 mA; VI = VIH 2.3 2.3 1.7 −
3.0 3.0 2.4 −
IOH = −24 mA; VI = VIH 3.0 3.0 2.2 −
VOL Output LOW Voltage IOL = 100 mA; VI = VIL 0.9 – 4.5 0.9 – 4.5 −0.2 V
IOL = 0.5 mA; VI = VIH 1.1 1.1 −0.3
IOL = 2 mA; VI = VIH 1.4 1.4 −0.35
IOL = 6 mA; VI = VIL 1.65 1.65 −0.3
IOL = 12 mA; VI = VIL 2.3 2.3 −0.4
2.7 2.7 −0.4
IOL = 18 mA; VI = VIL 2.3 2.3 −0.6
3.0 3.0 −0.4
IOL = 24 mA; VI = VIL 3.0 3.0 −0.55
IIInput Leakage Current VI = VCCA or GND 0.9 – 4.5 0.9 – 4.5 −1.0 1.0 mA
ICCA Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 − 4.5 −2.0 mA
ICCB Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 − 4.5 −2.0 mA
ICCA + ICCB Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 – 4.5 −4.0 mA
IOFF Power OFF Leakage Current VI = 4.5 V 0 0 −5.0 mA
NLSV1T34
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4
TOTAL STATIC POWER CONSUMPTION (ICCA + ICCB)
−405C to +855C
VCCB (V)
4.5 3.3 2.8 1.8 0.9
VCCA (V) Min Max Min Max Min Max Min Max Min Max Unit
4.5 2 2 2 2 < 1.5 μA
3.3 2 2 2 2 < 1.5 μA
2.8 < 2 < 1 < 1 < 0.5 < 0.5 μA
1.8 < 1 < 1 < 0.5 < 0.5 < 0.5 μA
0.9 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 μA
NOTE: Connect ground before applying supply voltage VCCA or VCCB. This device is designed with the feature that the power−up sequence
of VCCA and VCCB will not damage the IC.
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter VCCA (V)
−405C to +855C
Unit
VCCB (V)
4.5 3.3 2.8 1.8 1.2
Min Max Min Max Min Max Min Max Min Max
tPLH,
tPHL
(Note 1)
Propagation
Delay,
A to B
4.5 1.6 1.8 2.0 2.1 2.3 nS
3.3 1.7 1.9 2.1 2.3 2.6
2.8 1.9 2.1 2.3 2.5 2.8
1.8 2.1 2.4 2.5 2.7 3.0
1.2 2.4 2.7 2.8 3.0 3.3
1. Propagation delays defined per Figure 2.
CAPACITANCE
Symbol Parameter Test Conditions Typ (Note 2) Unit
CI/O I/O Pin Input Capacitance VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B 5.0 pF
CPD Power Dissipation Capacitance VCCA = VCCB = 3.3 V, VI = 0 V or VCCA, f = 10 MHz 5.0 pF
2. Typical values are at TA = +25°C.
3. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
ICC(operating) ^ CPD x VCC x fIN where ICC = ICCA + ICCB.
NLSV1T34
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5
Figure 2. AC (Propagation Delay) Test Circuit
DUT
Pulse
Generator
VCC
CLRL
Test Switch
CL = 15 pF or equivalent (includes probe and jig capacitance)
RL = 2 kW or equivalent
ZOUT of pulse generator = 50 W
Figure 3. AC (Propagation Delay) Test Circuit Waveforms
Input (An)
Output (Bn)
Vm
Vm Vm
Vm
tPLH tPHL
VIH
0 V
VOH
VOL
Waveform 1 − Propagation Delays
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Symbol
VCC
0.9 V – 4.5 V
VmA VCCA/2
VmB VCCB/2
ORDERING INFORMATION
Device Package Shipping†
NLSV1T34MUTBG UDFN6, 1.2 x 1.0, 0.4P
(Pb−Free)
3000 / Tape & Reel
NLSV1T34AMUTCG UDFN6, 1.45 x 1.0, 0.5P
(Pb−Free)
3000 / Tape & Reel
NLSV1T34AMX1TCG ULLGA6
(Pb−Free)
3000 / Tape & Reel
NLSV1T34DFT2G SC−88A
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NLSV1T34
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6
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H--- 0.10---0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
−B−
SC−88A, SOT−353, SC−70
CASE 419A
ISSUE J
ǒmm
inchesǓ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
NLSV1T34
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7
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉ
ÉÉ
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
L5X
NOTE 3
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X
0.10 C
10X
A
A1
(A3)
0.08 C
0.10 C
C
SEATING
PLANE
SIDE VIEW
L2
13
46
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b0.15 0.25
D1.20 BSC
E1.00 BSC
e0.40 BSC
L0.30 0.40
L1 0.00 0.15
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.22
6X
0.42 6X
1.07
0.40
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
L1
DETAIL A
Bottom View
(Optional)
ÉÉÉ
ÉÉÉ
ÉÉÉ
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
L2 0.40 0.50
NLSV1T34
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8
PACKAGE DIMENSIONS
UDFN6, 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
ÉÉÉ
ÉÉÉ
ÉÉÉ
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
L6X
NOTE 3
0.10 C
PIN ONE
REFERENCE
TOP VIEW
0.10 C
6X
A
A1
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
13
46
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
b0.20 0.30
D1.45 BSC
E1.00 BSC
e0.50 BSC
L0.30 0.40
L1 −−− 0.15
DIMENSIONS: MILLIMETERS
0.30
6X
1.24
0.53
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.50
1
MOUNTING FOOTPRINT
PACKAGE
OUTLINE
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
ÉÉ
ÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTIONS
A2 0.07 REF
6X
A2
DETAIL B
DETAIL A
NLSV1T34
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9
PACKAGE DIMENSIONS
ULLGA6 1.45x1.0, 0.5P
CASE 613AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
L5X
NOTE 3
0.10 C
PIN ONE
REFERENCE
TOP VIEW
0.10 C
6X
A
A1
0.05 C
0.05 C
C
SEATING
PLANE
SIDE VIEW
L1
13
46
DIM MIN MAX
MILLIMETERS
A−−− 0.40
A1 0.00 0.05
b0.15 0.25
D1.45 BSC
E1.00 BSC
e0.50 BSC
L0.25 0.35
L1 0.30 0.40
NOTE 4
SOLDERMASK DEFINED*
DIMENSIONS: MILLIMETERS
0.30
5X
0.49 6X
1.24
0.53
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.50
1
MOUNTING FOOTPRINT
PKG
OUTLINE
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5817−1050
NLSV1T34/D
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