General Description
The MAX11646/MAX11647 low-power, 10-bit, 1-/2-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, a clock, and
an I2C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11647) or 4.5V to 5.5V (MAX11646) and require
only 6µA at a 1ksps sample rate. AutoShutdown™ pow-
ers down the devices between conversions, reducing
supply current to less than 1µA at lower throughput
rates. The MAX11646/MAX11647 each measure two
single-ended or one differential input. The fully differen-
tial analog inputs are software configurable for unipolar
or bipolar and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11647 fea-
tures a 2.048V internal reference and the MAX11646
features a 4.096V internal reference.
The MAX11646/MAX11647 are available in an ultra-tiny
1.9mm x 2.2mm WLP package and an 8-pin µMAX®
package. These ADCs are guaranteed over the extend-
ed temperature range (-40°C to +85°C). For pin-com-
patible 12-bit parts, refer to the MAX11644/MAX11645
data sheet.
Applications
Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Power-Supply Monitoring
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
♦Ultra-Tiny 1.9mm x 2.2mm Wafer Level Package
♦High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
♦Single Supply
2.7V to 3.6V (MAX11647)
4.5V to 5.5V (MAX11646)
♦Internal Reference
2.048V (MAX11647)
4.096V (MAX11646)
♦External Reference: 1V to VDD
♦Internal Clock
♦2-Channel Single-Ended or 1-Channel Fully
Differential
♦Internal FIFO with Channel-Scan Mode
♦Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
♦Software-Configurable Unipolar/Bipolar
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-5134; Rev 1; 9/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-
PACKAGE
I2C SLAVE
ADDRESS
MAX11646EUA+ -40°C to +85°C 8 μMAX 0110110
MAX11647EUA+ -40°C to +85°C 8 μMAX 0110110
MAX11647EWC+ -40°C to +85°C 12 WLP 0110110
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
+
Denotes a lead(Pb)-free/RoHs-compliant package.
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
AIN0, AIN1,
REF to GND............-0.3V to the lower of (VDD + 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin .........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW
12-Pin WLP (derate 16.1mW/°C above +70°C) .........1288mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s)
µMAX only....................................................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 2)
Resolution 10 Bits
Relative Accuracy INL (Note 3) ±1 LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error ±1 LSB
Offset-Error Temperature
Coefficient Relative to FSR 0.3 ppm/°C
Gain Error (Note 4) ±1 LSB
Gain-Temperature Coefficient Relative to FSR 0.3 ppm/°C
Channel-to-Channel Offset
Matching ±0.1 LSB
Channel-to-Channel Gain
Matching ±0.1 LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)
Signal-to-Noise and Distortion SINAD 60 dB
Total Harmonic Distortion THD Up to the fifth harmonic -70 dB
Spurious-Free Dynamic Range SFDR 70 dB
Full-Power Bandwidth SINAD > 57dB 3.0 MHz
Full-Linear Bandwidth -3dB point 5.0 MHz
CONVERSION RATE
Internal clock 6.8
Conversion Time (Note 5) tCONV External clock 10.6 μs
Internal clock, SCAN[1:0] = 01 53
Throughput Rate fSAMPLE External clock 94.4 ksps
Track/Hold Acquisition Time 800 ns
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal Clock Frequency 2.8 MHz
External clock, fast mode 60
Aperture Delay (Note 6) tAD External clock, high-speed mode 30 ns
ANALOG INPUT (AIN0/AIN1)
Unipolar 0 VREFInput Voltage Range, Single-
Ended and Differential (Note 7) Bipolar 0 ±VREF/2 V
Input Multiplexer Leakage
Current On/off-leakage current, VAIN_ = 0V or VDD ±0.01 ±1 μA
Input Capacitance CIN 22 pF
INTERNAL REFERENCE (Note 8)
MAX11647 1.968 2.048 2.128
Reference Voltage VREF T
A = +25°C MAX11646 3.939 4.096 4.256 V
Reference-Voltage Temperature
Coefficient TCVREF 25 ppm/°C
REF Short-Circuit Current 2 mA
REF Source Impedance 1.5 k
EXTERNAL REFERENCE
REF Input Voltage Range VREF (Note 9) 1 VDD V
REF Input Current IREF f
SAMPLE = 94.4ksps 40 μA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage VIH 0.7
x VDD V
Input Low Voltage VIL 0.3
x VDD V
Input Hysteresis VHYST 0.1
x VDD V
Input Current IIN V
IN = 0V to VDD ±10 μA
Input Capacitance CIN 15 pF
Output Low Voltage VOL I
SINK = 3mA 0.4 V
POWER REQUIREMENTS
MAX11647 2.7 3.6
Supply Voltage VDD MAX11646 4.5 5.5
V
Internal reference 900 1150
fSAMPLE = 94.4ksps
external clock External reference 670 900
Internal reference 530
fSAMPLE = 40ksps
internal clock External reference 230
Internal reference 380
fSAMPLE = 10ksps
internal clock External reference 60
Internal reference 330
fSAMPLE =1ksps
internal clock External reference 6
Supply Current IDD
Shutdown (internal reference off) 0.5 10
μA
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio PSRR Full-scale input (Note 10) ±0.01 ±0.5 LSB/V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency fSCL 400 kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF 1.3 μs
Hold Time for a START (S)
Condition tHD:STA 0.6 μs
Low Period of the SCL Clock tLOW 1.3 μs
High Period of the SCL Clock tHIGH 0.6 μs
Setup Time for a REPEATED
START Condition (Sr) tSU:STA 0.6 μs
Data Hold Time tHD:DAT (Note 11) 0 900 ns
Data Setup Time tSU:DAT 100 ns
Rise Time of Both SDA and SCL
Signals, Receiving tR Measured from 0.3VDD to 0.7VDD 20 +
0.1CB 300 ns
Fall Time of SDA Transmitting tF Measured from 0.3VDD to 0.7VDD (Note 12) 20 +
0.1CB 300 ns
Setup Time for a STOP (P)
Condition tSU:STO 0.6 μs
Capacitive Load for Each Bus CB 400 pF
Pulse Width of Spike tSP 50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)
Serial-Clock Frequency fSCLH (Note 14) 1.7 MHz
Hold Time, REPEATED START
Condition (Sr) tHD:STA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a REPEATED
START Condition (Sr) tSU:STA 160 ns
Data Hold Time tHD:DAT (Note 11) 0 150 ns
Data Setup Time tSU:DAT 10 ns
Note 1: All WLP devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11646 is tested at VDD = 5V and the MAX11647 is tested at VDD = 3V, with an external refer-
ence for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD.
Note 8: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1µF capaci-
tor and a 2kΩseries resistor (see the
Typical Operating Circuit
).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 10: Measured as follows for the MAX11647:
and for the MAX11646, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at TA= +25°C.
Note 13: CB= total capacitance of one bus line in pF.
Note 14: fSCL must meet the minimum clock low time plus the rise/fall times.
VFS VV
FS VVREF
V
N
(. ) (. )
(.
55 45 2
55
−
⎡
⎣⎤
⎦×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−− 45.)V
VVVV
V
V
FS FS
N
REF
(. ) (. )
(.
36 27 2
36
−
⎡
⎣⎤
⎦×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−− 27.)V
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled) tRCL Measured from 0.3VDD to 0.7VDD 20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit tRCL1 Measured from 0.3VDD to 0.7VDD 20 160 ns
Fall Time of SCL Signal tFCL Measured from 0.3VDD to 0.7VDD 20 80 ns
Rise Time of SDA Signal tRDA Measured from 0.3VDD to 0.7VDD 20 160 ns
Fall Time of SDA Signal tFDA Measured from 0.3VDD to 0.7VDD (Note 12) 20 160 ns
Setup Time for a STOP (P)
Condition tSU:STO 160 ns
Capacitive Load for Each Bus
Line CB 400 pF
Pulse Width of Spike tSP (Notes 11 and 14) 0 10 ns
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 3.3V (MAX11647), VDD = 5V (MAX11646), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar,
TA= +25°C, unless otherwise noted.)
-0.3
-0.1
-0.2
0.1
0
0.2
0.3
0 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX11646 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
400200 600 800
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 400200 600 800 1000
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX11646 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-160
-140
-120
-100
-80
-60
-40
-20
0
0 10k 20k 30k 40k 50k
FFT PLOT
MAX11646 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX11646 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
INTERNAL REFERENCE MAX11646
MAX11646
MAX11647
MAX11647
INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0
0.2
0.1
0.4
0.3
0.5
0.6
2.7 5.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11646 toc05
SUPPLY VOLTAGE (V)
IDD (μA)
3.73.2 4.2 4.7
SDA = SCL = VDD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5
-25 20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11646 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX11647
MAX11646
0
100
200
300
400
500
600
700
800
900
1000
0 20406080100
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
MAX11646 toc07
CONVERSION RATE (ksps)
AVERAGE IDD (μA)
0
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
B
A
0.9990
0.9994
0.9992
0.9998
0.9996
1.0002
1.0000
1.0004
1.0008
1.0006
1.0010
-40 -10 5-25 20 35 50 65 80
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11646 toc08
TEMPERATURE (°C)
VREF NORMALIZED
MAX11646
MAX11647
NORMALIZED TO REFERENCE VALUE
TA = +25°C
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 7
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
-40 -10 5-25 20 35 50 65 80
OFFSET ERROR vs. TEMPERATURE
MAX11646 toc10
TEMPERATURE (°C)
OFFSET ERROR (LSB)
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX11647), VDD = 5V (MAX11646), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar,
TA= +25°C, unless otherwise noted.)
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11646 toc11
VDD (V)
OFFSET ERROR (LSB)
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
-40 -10 5-25 20 35 50 65 80
GAIN ERROR vs. TEMPERATURE
MAX11646 toc12
TEMPERATURE (°C)
GAIN ERROR (LSB)
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.7 3.73.2 4.2 4.7 5.2
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11646 toc13
VDD (V)
GAIN ERROR (LSB)
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
8 _______________________________________________________________________________________
Pin Description
PIN
μMAX WLP NAME FUNCTION
1,2 A1, A2 AIN0, AIN1 Analog Inputs
3 — N.C. No connection. Not internally connected.
4 A4 REF Reference Input/Output. Selected in the setup register (see Tables 1 and 6).
5 C4 SCL Clock Input
6 C3 SDA Data Input/Output
7A3, B1–B4,
C2 GND Ground
8 C1 VDD Positive Supply. Bypass to GND with a 0.1μF capacitor.
SDA
SCLREF
1
2
8
7
VDD
GNDAIN1
N.C.
AIN0
µ
MAX
TOP VIEW
3
4
6
5
MAX11646
MAX11647
+
TOP VIEW (BUMPS ON BOTTOM)
MAX11647
GND
AIN1 GND REF
GNDGND
SDA
GND
GND SCL
1234
A
B
C
WLP
VDD
AIN0
Pin Configuration
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 9
tHD:STA
tSU:DAT
tHIGH
tRtF
tHD:DAT tHD:STA
SSr A
SCL
SDA
tSU:STA
tLOW
tBUF
tSU:STO
PS
tHD:STA
tSU:DAT
tHIGH
tFCL
tHD:DAT tHD:STA
S Sr A
SCL
SDA
tSU:STA
tLOW
tBUF
tSU:STO
S
tRCL tRCL1
HS MODE F/S MODE
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING tFDA
tRDA
t
tRtF
P
Figure 1. 2-Wire Serial-Interface Timing
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
10 ______________________________________________________________________________________
Detailed Description
The MAX11646/MAX11647 ADCs use successive-
approximation conversion techniques and fully differen-
tial input T/H circuitry to capture and convert an analog
signal to a serial 10-bit digital output. The
MAX11646/MAX11647 measure either two single-
ended inputs or one differential input. These devices
feature a high-speed, 2-wire serial interface supporting
data rates up to 1.7MHz. Figure 2 shows the simplified
internal structure for the MAX11646/MAX11647.
Power Supply
The MAX11646/MAX11647 operate from a single supply
and consume 670µA (typ) at sampling rates up to
94.4ksps. The MAX11647 features a 2.048V internal ref-
erence and the MAX11646 features a 4.096V internal ref-
erence. These devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/Hold
The MAX11646/MAX11647 analog input architecture
contains an analog input multiplexer (mux), a fully dif-
ferential T/H capacitor, T/H switches, a comparator,
and a fully differential switched capacitive digital-to-
analog converter (DAC) (Figure 4).
In single-ended mode, the analog-input multiplexer con-
nects CT/H between the analog input selected by CS0
(see the
Configuration/Setup Bytes (Write Cycle)
sec-
tion) and GND (Table 3). In differential mode, the analog
input multiplexer connects CT/H to the + and - analog
inputs selected by CS0 (Table 4).
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/H as a stable sample of the input signal.
ANALOG
INPUT
MUX
AIN1
REF
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11646)
2.048V (MAX11647)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H 10-BIT
ADC
VDD
GND
MAX11646
MAX11647
Figure 2. Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 11
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕(VIN+ - VIN-) from
CT/H to the binary-weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the
Slave Address
section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11646/MAX11647 hold
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W= 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ ≥9 ✕(RSOURCE + RIN) ✕CIN
where RSOURCE is the analog input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal
clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX11646/MAX11647 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
swing from (VGND - 0.3V) to (VDD + 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
TRACK
TRACK
HOLD
CT/H
CT/H
TRACK
TRACK
HOLD
AIN0
AIN1
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REF MAX11646
MAX11647
HOLD
HOLD
TRACK
HOLD
VDD/2
Figure 4. Equivalent Input Circuit
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
12 ______________________________________________________________________________________
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11646/MAX11647 analog input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS0 and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS0 (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the
Transfer Functions
section.
In single-ended mode, the MAX11646/MAX11647
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11646/MAX11647 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11646/MAX11647 and the master
at rates up to 1.7MHz. The MAX11646/MAX11647 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ωor greater) (see the
Typical
Operating Circuit
). Series resistors (RS) are optional.
They protect the input architecture of the MAX11646/
MAX11647 from high voltage spikes on the bus lines,
minimize crosstalk, and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11646/
MAX11647. The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is stable are considered control signals
(see the
START and STOP Conditions
section). Both
SDA and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see the
HS Mode
section).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11646/MAX11647 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
SCL
SDA
SP
Sr
Figure 5. START and STOP Conditions
SCL
SDA
SNOT ACKNOWLEDGE
ACKNOWLEDGE
12 89
Figure 6. Acknowledge Bits
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 13
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX11646/MAX11647 continu-
ously wait for a START condition followed by their slave
address. When the MAX11646/MAX11647 recognize their
slave address, they are ready to accept or send data.
The slave address has been factory programmed and is
always 0110110 for the MAX11646/MAX11647 (Figure 7).
The least significant bit (LSB) of the address byte (R/W)
determines whether the master is writing to or reading
from the MAX11646/MAX11647 (R/W= 0 selects a write
condition, R/W= 1 selects a read condition). After receiv-
ing the address, the MAX11646/MAX11647 (slave) issue
an acknowledge by pulling SDA low for one clock cycle.
Bus Timing
At power-up, the MAX11646/MAX11647 bus timing is set
for fast mode (F/S mode), allowing conversion rates up to
22.2ksps. The MAX11646/MAX11647 must operate in
high-speed mode (HS mode) to achieve conversion
rates up to 94.4ksps. Figure 1 shows the bus timing for
the MAX11646/MAX11647’s 2-wire interface.
HS Mode
At power-up, the MAX11646/MAX11647 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After suc-
cessfully receiving the HS-mode master code, the
MAX11646/MAX11647 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle
(Figure 8). After the not-acknowledge, the MAX11646/
MAX11647 are in HS mode. The bus master must then
send a repeated START followed by a slave address to
initiate HS-mode communication. If the master gener-
ates a STOP condition the MAX11646/MAX11647 return
to F/S mode.
011 10 1 0 R/W A
SLAVE ADDRESS
S
SCL
SDA
123456789
DEVICE SLAVE ADDRESS
0110110MAX11646/MAX11647
Figure 7. Slave Address Byte
000 10XXXA
HS-MODE MASTER CODE
SCL
SDA
S Sr
F/S MODE HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
14 ______________________________________________________________________________________
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 7)
and a write bit (R/W= 0). If the address byte is success-
fully received, the MAX11646/MAX11647 (slave) issue
an acknowledge. The master then writes to the slave.
The slave recognizes the received byte as the setup
byte (Table 1) if the most significant bit (MSB) is 1. If the
MSB is 0, the slave recognizes that byte as the configu-
ration byte (Table 2). The master can write either 1 or 2
bytes to the slave in any order (setup byte then configu-
ration byte, configuration byte then setup byte, setup
byte or configuration byte only; see Figure 9). If the
slave receives a byte successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the bus
into F/S mode (see the
HS Mode
section).
B. 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
711
WSETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
8
P or Sr
1
A
1
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
711
WSETUP OR
CONFIGURATION BYTE
8
P or Sr
1
A
1
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
A
18
A. 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9. Write Cycle
BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X
BIT NAME DESCRIPTION
7 REG Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage (Table 6). Default to 000 at power-up.
3 CLK 1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
2 BIP/UNI 1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1RST
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
0 X Don’t-care bit. This bit can be set to 1 or 0.
Table 1. Setup Byte Format
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 15
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W= 1). If the address byte is successfully
received, the MAX11646/MAX11647 (slave) issue an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 6 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s),
it can issue an acknowledge if it wants to continue
reading or a not-acknowledge if it no longer wishes to
read. If the MAX11646/MAX11647 receive a not-
acknowledge, they release SDA, allowing the master to
generate a STOP or a repeated START condition. See
the
Clock Modes
and
Scan Mode
sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11646/MAX11647 are defaulted
to internal clock mode (CLK = 0).
BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
REG SCAN1 SCAN0 X X X CS0 SGL/DIF
BIT NAME DESCRIPTION
7 REG Register bit. 1= setup byte (see Table 1), 0 = configuration byte.
6 SCAN1
5 SCAN0
Scan-select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.
4 X
3 X
2 X
1 CS0
Channel-select bit. CS0 selects which analog input channels are to be used for conversion
(Tables 3 and 4). Defaults to 0000 at power-up.
0 SGL/DIF 1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-
Ended/Differential Input section.
Table 2. Configuration Byte Format
CS0 AIN0 AIN1 GND
0 + -
1 + -
Table 3. Channel Selection in Single-
Ended Mode (SGL/DIF = 1)
CS0 AIN0 AIN1
0 + -
1 - +
Table 4. Channel Selection in Differential
Mode (SGL/DIF = 0)
X = Don’t care.
X = Don’t care. X = Don’t care.
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
16 ______________________________________________________________________________________
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS A
711
RCLOCK STRETCH
NUMBER OF BITS
P or Sr
1
8
RESULT 8 LSBs
8
RESULT 2 MSBs A
A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
711
RCLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT 1 ( 2MSBs) A
1
A
8
RESULT 1 (8 LSBs) A
8
RESULT N (8LSBs)A
18
RESULT N (8MSBs)
SLAVE TO MASTER
MASTER TO SLAVE
CLOCK STRETCH
tACQ1
tCONV2
tACQ2
tCONVN
tACQN
tCONV
tACQ
11
tCONV1
A
Figure 10. Internal Clock Mode Read Cycles
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11646/MAX11647 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11646/MAX11647 begin tracking the analog input
after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11646/
MAX11647 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11646/
MAX11647 contain two 10-bit blocks of memory. Once
all conversions are complete, the MAX11646/MAX11647
release SCL, allowing it to be pulled high. The master can
now clock the results out of the memory in the same
order the scan conversion has been done at a clock
rate of up to 1.7MHz. SCL is stretched for a maximum
of 7.6µs per channel (see Figure 10).
The device memory contains all of the conversion results
when the MAX11646/MAX11647 release SCL. The con-
verted results are read back in a first-in/first-out (FIFO)
sequence. The memory contents can be read continu-
ously. If reading continues past the result stored in
memory, the pointer wraps around and point to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 17
External Clock
When configured for external clock mode (CLK = 1),
the MAX11646/MAX11647 use the SCL as the conver-
sion clock. In external clock mode, the MAX11646/
MAX11647 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to re-address the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11646/MAX11647 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to mem-
ory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission, the first byte
begins with six empty bits during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not pos-
sible to read the memory independently of conversion.
SLAVE ADDRESS
tCONV1
tACQ1 tACQ2
tCONVN
tACQN
tCONV
tACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
711
R
S
1711
RP OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT (8 LSBs)
8
A
1
RESULT (2 MSBs)
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
RESULT 1 (2 MSBs) RESULT 2 (8 LSBs) RESULT N (8 LSBs)
A
1
8
RESULT N (2 MSBs)
A
Figure 11. External Clock Mode Read Cycle
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS0.
0 1 Converts the input selected by CS0 eight times (see Tables 3 and 4).*
1 0 Reserved. Do not use.
1 1 Converts input selected by CS0.*
*
When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not acknowledge occurs.
Table 5. Scanning Configuration
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
18 ______________________________________________________________________________________
SEL2 SEL1 SEL0
REFERENCE VOLTAGE
REF INTERNAL REFERENCE STATE
00X V
DD Not connected Always off
0 1 X External reference Reference input Always off
1 0 0 Internal reference Not connected* Always off
1 0 1 Internal reference Not connected* Always on
1 1 0 Internal reference
Reference output
Always off
1 1 1 Internal reference
Reference output
Always on
Table 6. Reference Voltage and REF Format
X = Don’t care.
*
Preferred configuration for internal reference.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel conver-
sion on AIN0 using the internal clock with VDD as the refer-
ence. The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11646/MAX11647 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, not-
acknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not nec-
essary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all con-
version results are written to memory (Figure 10). When
using an external reference or VDD as a reference, all
analog circuitry is inactive in shutdown and supply cur-
rent is less than 0.5µA (typ). The digital conversion
results obtained in internal clock mode are maintained
in memory during shutdown and are available for
access through the serial interface at any time prior to a
STOP or a repeated START condition.
When idle, the MAX11646/MAX11647 continuously wait
for a START condition followed by their slave address
(see the
Slave Address
section). Upon reading a valid
address byte the MAX11646/MAX11647 power up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or VDD as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11647 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the aver-
age supply current is just 1µA, or a minuscule 3µW of
power consumption (see Average Supply Current vs.
Conversion Rate (External Clock) in the
Typical Operating
Characteristics
).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference
and the REF configuration (Table 6).
Internal Reference
The internal reference is 4.096V for the MAX11646 and
2.048V for the MAX11647. When REF is configured to be
an internal reference output (SEL[2:1] = 11), decouple
REF to GND with a 0.1µF capacitor and a 2kΩseries
resistor (see the
Typical Operating Circuit
). Once powered
up, the reference always remains on until reconfigured.
The internal reference requires 10ms to wake up and is
accessed using SEL0 (Table 6). When in shutdown, the
internal reference output is in a high-impedance state. The
reference should not be used to supply current for exter-
nal circuitry. The internal reference does not require an
external bypass capacitor and works best when left
unconnected (SEL1 = 0).
External Reference
The external reference can range from 1V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output imped-
ance of 500Ωor less. If the reference has a higher out-
put impedance or is noisy, bypass it to GND as close
as possible to REF with a 0.1µF capacitor.
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 19
Transfer Functions
Output data coding for the MAX11646/MAX11647 is
binary in unipolar mode and two’s complement in bipo-
lar mode with 1 LSB = (VREF/2N) where N is the number
of bits (10). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PCBs. Wire-wrap configurations are not rec-
ommended since the layout should ensure proper sep-
aration of analog and digital traces. Do not run analog
and digital lines parallel to each other, and do not lay
out digital signal paths underneath the ADC package.
Use separate analog and digital PCB ground sections
with only one star point (Figure 14) connecting the two
ground systems (analog and digital). For lowest noise
operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass VDD to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX11646/MAX11647 power-
supply pin. Minimize capacitor lead length for best sup-
ply noise rejection, and add an attenuation resistor (5Ω)
in series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once offset
and gain errors have been nullified. The MAX11646/
MAX11647’s INL is measured using the endpoint.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0FS
FS - 3/2 LSB
FS = VREF
ZS = GND
INPUT VOLTAGE (LSB)
MAX11646
MAX11647
1 LSB = VREF
1024
Figure 12. Unipolar Transfer Function
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS 0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1 LSB
*VCOM ≥ VREF/2 *VIN = (AIN+) - (AIN-)
FS = VREF
2
-FS = -VREF
2
MAX11646
MAX11647
1 LSB = VREF
1024
Figure 13. Bipolar Transfer Function
GND
VLOGIC = 3V/5V3V OR 5V
SUPPLIES
DGND3V/5VGND
*OPTIONAL
4.7μF
R* = 5Ω
0.1μF
VDD
DIGITAL
CIRCUITRY
MAX11646
MAX11647
Figure 14. Power-Supply Grounding Connection
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
20 ______________________________________________________________________________________
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNRMAX[dB] = 6.02dB ✕N + 1.76dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 ✕log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through V5
are the amplitudes of the 2nd through 5th order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
THD VVVV
V
=× +++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
⎛
⎝
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
20 22324252
1
log
SINAD dB SignalRMS
NoiseRMS THDRMS
( ) log=× +
⎡
⎣
⎢⎤
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20
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 21
*OPTIONAL
RS*
RS*
ANALOG
INPUTS
μCSDA
SCL
GND
VDD
SDA
SCL
AIN0
AIN1
RC NETWORK*
REF
3.3V or 5V
5V
RP
CREF
0.1μF
RP
5V
MAX11646
MAX11647
0.1μF
2kΩ
Typical Operating Circuit Selector Guide
PART INPUT
CHANNELS
INTERNAL
REFERENCE
(V)
SUPPLY
VOLTAGE
(V)
INL
(LSB)
MAX11646
2 Single-
Ended/1
Differential
4.096 4.5 to 5.5 ±1
MAX11647
2 Single-
Ended/1
Differential
2.048 2.7 to 3.6 ±1
Chip Information
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 µMAX U8CN+1 21-0036 90-0092
12 WLP W121C2+1 21-0009
Refer to
Application
Note 1891
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/10 Initial release —
1 9/10
Added the WLP package to the Ordering Information,Absolute Maximum
Ratings,Pin Configuration,Pin Description, and Package Information sections 1, 2, 8, 20