TL16C2550IRHBRG4 - Texas Instruments

TL16CP754C, TL16C754C

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SLLS644G –DECEMBER 2007–REVISED MAY 2011

QUAD UARTS WITH 64-BYTE FIFO

Check for Samples: TL16CP754C,TL16C754C

1FEATURES

•ST16C654/654D Pin Compatible With •Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply

Additional Enhancements •Characterized for Operation From –40°C to

•Support up to 24-MHz Crystal Input Clock 85°C, Available in Commercial and Industrial

(1.5 Mbps) Temperature Grades

•Support up to 48-MHz Oscillator Input Clock •Software-Selectable Baud-Rate Generator

(3 Mbps) for 5-V Operation •Prescaler Provides Additional Divide-by-4

•Support up to 32-MHz Oscillator Input Clock Function

(2 Mbps) for 3.3-V Operation •Programmable Sleep Mode

•Support up to 24-MHz Input Clock (1.5 Mbps) •Programmable Serial Interface Characteristics

for 2.5-V Operation –5-, 6-, 7-, or 8-Bit Characters

•Support up to 16-MHz Input Clock (1 Mbps) for –Even, Odd, or No Parity Bit Generation and

1.8-V Operation Detection

•64-Byte Transmit FIFO –1-, 1.5-, or 2-Stop Bit Generation

•64-Byte Receive FIFO With Error Flags •False Start Bit Detection

•Programmable and Selectable Transmit and •Complete Status Reporting Capabilities in

Receive FIFO Trigger Levels for DMA and Both Normal and Sleep Mode

Interrupt Generation •Line Break Generation and Detection

•Programmable Receive FIFO Trigger Levels for •Internal Test and Loopback Capabilities

Software/Hardware Flow Control •Fully Prioritized Interrupt System Controls

•Software/Hardware Flow Control •Modem Control Functions (CTS, RTS, DSR,

–Programmable Xon/Xoff Characters DTR, RI, and CD)

–Programmable Auto-RTS and Auto-CTS •IrDA Capability

•Optional Data Flow Resume by Xon Any

Character

•RS-485 Mode Support

DESCRIPTION

The '754C is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic

hardware/software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each

UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock

source, otherwise they operate independently. Another name for the UART function is Asynchronous

Communications Element (ACE), and these terms are used interchangeably. The bulk of this document

describes the behavior of each ACE, with the understanding that four such devices are incorporated into the

'754C. The '754C offers enhanced features. It has a transmission control register (TCR) that stores received

FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY

provide the user with error indications, operational status, and modem interface control. System interrupts may

be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on

the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and

transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own

desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity

and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.

The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control

operations, and software flow control and hardware flow control capabilities.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TL16CP754C, TL16C754C

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The '754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the

TL16C754CPM device.

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register Address

A0 24 I Map.

Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register Address

A1 23 I Map.

Address bit 2 select. Internal registers address selection. Refer to Table 9 for Register Address

A2 22 I Map.

Carrier detect (active low). These inputs are associated with individual UART channels A

CDA, CDB, 64, 18, I through D. A low on these pins indicates that a carrier has been detected by the modem for that

CDC, CDD 31, 49 channel.

Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,

a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL

selects the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing

CLKSEL 21 I edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on

CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler

value.

Chip select A, B, C, and D (active low). These pins enable data transfers between the user

CSA, CSB, 7, 11, I CPU and the '754C for the channel(s) addressed. Individual UART sections (A, B, C, D) are

CSC, CSD 38, 42 addressed by providing a low on the respective CSA through CSD pin.

Clear to send (active low). These inputs are associated with individual UART channels A

through D. A low on the CTS pins indicates the modem or data set is ready to accept transmit

CTSA, CTSB, 2, 16, I data from the '754C. Status can be checked by reading MSR[4]. These pins only affect the

CTSC, CTSD 33, 47 transmit and receive operations when auto CTS function is enabled through the enhanced

feature register (EFR[7]), for hardware flow control operation.

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TERMINAL FUNCTIONS (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring

D0–D2, 53–60 I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a

D3–D7 transmit or receive serial data stream.

Data set ready (active low). These inputs are associated with individual UART channels A

DSRA, DSRB, 1, 17, I through D. A low on these pins indicates the modem or data set is powered on and is ready for

DSRC, DSRD 32, 48 data exchange with the UART.

Data terminal ready (active low). These outputs are associated with individual UART channels

A through D. A low on these pins indicates that the '754C is powered on and ready. These pins

DTRA, DTRB, 3, 15, can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR

DTRC, DTRD 34, 46 output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0],

or after a reset. These pins can also be used in the RS-485 mode to control an external RS-485

driver or transceiver.

14, 28,

GND Pwr Power signal and power ground

45, 61 Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D.

INTA−D are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable

INTA, INTB, 6, 12, O register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver

INTC, INTD 37, 43 errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is

detected. INTA−D are in the high-impedance state after reset.

Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with

MCR[3] to enable or disable the 3-state interrupts INTA-D or override MCR[3] and force

INTSEL –I continuous interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving

this pin low allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to

a 1 to enable the 3-state outputs.

Read input (active low strobe). A valid low level on IOR loads the contents of an internal

IOR 40 I register defined by address bits A0–A2 onto the '754C data bus (D0–D7) for access by an

external CPU.

Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus

IOW 9 I (D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2.

Reset. RESET resets the internal registers and all the outputs. The UART transmitter output

RESET 27 I and the receiver input are disabled during reset time. See '754C external reset conditions for

initialization details. RESET is an active high input.

Ring indicator (active low). These inputs are associated with individual UART channels A

RIA, RIB, 63, 19, through D. A low on these pins indicates the modem has received a ringing signal from the

RIC, RID 30, 50 telephone line. A low-to-high transition on these input pins generates a modem status interrupt,

if it is enabled.

Request to send (active low). These outputs are associated with individual UART channels A

through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.

RTSA, RTSB, 5, 13, Writing a 1 in the modem control register (MCR[1]) sets these pins to low, indicating data is

RTSC, RTSD 36, 44 available. After a reset, these pins are set to 1. These pins only affect the transmit and receive

operation when auto-RTS function is enabled through the enhanced feature register (EFR[6]),

for hardware flow control operation.

Receive data input. These inputs are associated with individual serial channel data to the

'754C. During the local loopback mode, these RX input pins are disabled and TX data is

RXA, RXB, 62, 20, I internally connected to the UART RX input internally. During normal mode, RXn should be held

RXC, RXD 29, 51 high when no data is being received. These outputs also can be used in IrDA mode. See the

IrDA mode section for more information.

Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel

RXRDY(1) –O FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt

occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.

(1) RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.

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TERMINAL FUNCTIONS (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

Transmit data. These outputs are associated with individual serial transmit channel data from

the '754C. During the local loopback mode, the TX input pin is disabled and TX data is

TXA, TXB, 8, 10, O internally connected to the UART RX input. During normal mode, TXn is high when no data is

TXC, TXD 39, 41 being sent. These outputs can also be used in IrDA mode, in which case TXn is low when no

data is being sent. See the IrDA mode section for more information.

Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel

TXRDY(2) –O FIFOs, TXRDY A–D. It goes low when there are a trigger level number of spares available. It

goes high when all four TX buffers are full.

4, 35,

VCC Pwr Power supply inputs

52 Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.

A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see

XTAL1 25 I Figure 10). Alternatively, an external clock can be connected to XTAL1 to provide custom data

rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal

XTAL2 26 O oscillator output or buffered clock output.

(2) RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.

NOTE: and functionality is not supported in the TL16C754CPM device.RXRDY TXRDY

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FUNCTIONAL BLOCK DIAGRAM

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A. The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a

majority vote to determine the logic level received. The Vote logic operates on all bits received.

FUNCTIONAL DESCRIPTION

The '754C UART is pin compatible with the TL16C754B and ST16C654 UARTs. It provides more enhanced

features. All additional features are provided through a special enhanced feature register.

The UART performs serial-to-parallel conversion on data characters received from peripheral devices or modems

and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each

channel of the '754C UART can be read at any time during functional operation by the processor.

The '754C UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software

overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to

64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or

programmable trigger levels. Primary outputs RXRDY and TXRDY allow Signaling of DMA transfers.

The '754C UART has selectable hardware flow control and software flow control. Both schemes significantly

reduce software overhead and increase system efficiency by automatically controlling serial data flow. Hardware

flow control uses the RTS output and CTS input signals. Software flow control uses programmable Xon/Xoff

characters.

The UART includes a programmable baud rate generator that can divide the timing reference clock input by a

divisor between 1 and (216–1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate

the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the

divide-by-1 is selected when CLKSEL is a logic 1.

Trigger Levels

The '754C UART provides independent selectable and programmable trigger levels for both receiver and

transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in

effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.

The programmable trigger levels are available via the TLR.

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Hardware Flow Control

Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be

enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output

when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is

sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is

activated/deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated

during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive

FIFO servicing latency.

Auto-RTS

Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS

functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the

RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is

reached, RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the

trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the

deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the

receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending

device to resume transmission.

A. N = receiver FIFO trigger level B.

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.

Figure 1. RTS Functional Timing

Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter

sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the

middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host

system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the

device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error can result. Figure 2 shows CTS functional timing, and Figure 3 shows

an example of autoflow control.

Serial to

Parallel

Flow

Control

Parallel to

Serial

Flow

Control

FIFO

Parallel to

Serial

Flow

Control

Serial to

Parallel

Flow

Control

FIFO

D7- D0 D7- D0

UART 1 UART 2

RTS

CTS

RTS

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A. When CTS is low, the transmitter keeps sending serial data out.

B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the

current byte, but it does not send the next byte.

C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing

Figure 3. Autoflow Control (Auto-RTS and Auto-CTS) Example

Software Flow Control

Software flow control is enabled through the enhanced feature register and the modem control register. Different

combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. Table 1

shows software flow control options.

Two other enhanced features relate to S/W flow control:

•Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff

character.

NOTE

It is possible that an Xon1 character is recognized as an Xon Any character, which could

cause an Xon2 character to be written to the RX FIFO.

•Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the

Xoff interrupt {IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The

special character is transferred to the RX FIFO.

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Table 1. Software Flow Control Options EFR[3:0]

BIT 3 BIT 2 BIT 1 BIT 0 Tx, Rx SOFTWARE FLOW CONTROLS

0 0 X X No transmit flow control

1 0 X X Transmit Xon1, Xoff1

0 1 X X Transmit Xon2, Xoff2

1 1 X X Transmit Xon1, Xon2: Xoff1, Xoff2

X X 0 0 No receive flow control

X X 1 0 Receiver compares Xon1, Xoff1 X X 0 1

X X 0 1 Receiver compares Xon2, Xoff2

Transmit Xon1, Xoff1

1 0 1 1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon2, Xoff2

0 1 1 1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1, Xon2: Xoff1, Xoff2

1 1 1 1 Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

No transmit flow control

0 0 1 1 Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

When software flow control operation is enabled, the '754C compares incoming data with Xoff1/2 programmed

characters (in certain cases Xoff1 and Xoff2 must be received sequentially(1)). When an Xoff character is

received, transmission is halted after completing transmission of the current character. Xoff character detection

also sets IIR[4] and causes INT to go high (if enabled via IER[5]).

To resume transmission an Xon1/2 character must be received (in certain cases Xon1 and Xon2 must be

received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt

disappears.

NOTE

If a parity, framing or break error occurs while receiving a software flow control character,

this character is treated as normal data and is written to the RCV FIFO.

Xoff1/2 characters are transmitted when the RX FIFO has passed the programmed trigger level TCR[3:0].

Xon1/2 characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR[7:4].

NOTE

If, after an Xoff character has been sent, software flow control is disabled, the UART

transmits Xon characters automatically to enable normal transmission to proceed. A

feature of the '754C UART design is that if the software flow combination (EFR[3:0])

changes after an Xoff has been sent, the originally programmed Xon is automatically sent.

If the RX FIFO is still above the trigger level the newly programmed Xoff1/2 is transmitted.

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the

FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least

significant bits of Xoff1,2/Xon1,2 are transmitted. The transmission of 5, 6, or 7 bits of a character is seldom

done, but this functionality is included to maintain compatibility with earlier designs.

It is assumed that software flow control and hardware flow control are never enabled simultaneously. Figure 4

shows a software flow control example.

(1) When pairs of Xon/Xoff characters are programmed to occur sequentially, received Xon1/Xoff1 characters will be written to the Rx FIFO

if the subsequent character is not Xon2/Xoff2.

UART 1

Parallel to Serial

Serial to Parallel

Xon-1 Word

Xon-2 Word

Xoff-1 Word

Transmit

FIFO

Serial to Parallel

Parallel to Serial

Xon-1 Word

Xon-2 Word

Xoff-1 Word

Xoff-2 Word

Receive

FIFO

Data

Xoff - Xon - Xoff

Compare

Programmed

Xon- Xoff

Characters

UART 2

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Figure 4. Software Flow Control Example

Software Flow Control Example

Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with

single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon

threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52.

UART1 begins transmission and sends 52 characters, at which point UART2 generates an interrupt to its

processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 continues sending

characters until a total of 60 characters have been sent. At this time UART2 will transmit a 0F to UART1,

informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff

character. Now UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level

drops to 32. UART2 now sends a 0D to UART1, informing UART1 to resume transmission.

Reset

Table 2 summarizes the state of outputs after reset.

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Table 2. Register Reset Functions(1)

RESET

CONTROL

Interrupt enable register RESET All bits cleared

Interrupt identification register RESET Bit 0 is set. All other bits cleared.

FIFO control register RESET All bits cleared

Line control register RESET Reset to 00011101 (1D hex).

Bit 6–0 cleared. Bit 7 reflects the inverse of the

Modem control register RESET CLKSEL pin value.

Line status register RESET Bits 5 and 6 set. All other bits cleared.

Modem status register RESET Bits 0–3 cleared. Bits 4–7 input signals.

Bit 6–0 is cleared. Bit 7 reflects the inverse of the

Enhanced feature register RESET CLKSEL pin value.

Receiver holding register RESET Pointer logic cleared

Transmitter holding register RESET Pointer logic cleared

Transmission control register RESET All bits cleared

Trigger level register RESET All bits cleared

Alternate function register RESET All bits (except AFR4) cleared; AFR4 set

(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,

i.e., they hold their initialization values during reset.

Table 3 summarizes the state of outputs after reset.

Table 3. Signal Reset Functions

SIGNAL RESET CONTROL RESET STATE

TX RESET High

RTS RESET High

DTR RESET High

RXRDY RESET High

TXRDY RESET Low

Interrupts

The '754C UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The

interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an

interrupt generation. The IER also can disable the interrupt system by clearing bits 0−3, 5−7. When an interrupt

is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides the type

of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.

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Table 4. Interrupt Control Functions

PRIORITY INTERRUPT

IIR[5–0] INTERRUPT SOURCE INTERRUPT RESET METHOD

LEVEL TYPE

000001 None None None None

000110 1 Receiver line OE, FE, PE, or BI errors occur in FE <PE <BI: All erroneous characters are

status characters in the RX FIFO read from the RX FIFO. OE: Read LSR

001100 2 RX timeout Stale data in RX FIFO Read RHR

000100 2 RHR interrupt DRDY (data ready) Read RHR

(FIFO disable)

RX FIFO above trigger level (FIFO enable)

000010 3 THR interrupt TFE (THR empty) Read IIR OR a write to the THR

(FIFO disable)

TX FIFO passes above trigger level (FIFO

enable)

000000 4 Modem status MSR[3:0]= 0 Read MSR

010000 5 Xoff interrupt Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR

100000 6 CTS, RTS RTS pin or CTS pin change state from Read IIR

active (low) to inactive (high)

It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors

remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the Rx

FIFO. Reading the Rx FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the

FIFO. If the Rx FIFO is empty, then LSR[4–2] is all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon

flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of

the ISR.

Interrupt Mode Operation

In interrupt mode (if any bit of IER[3:0] is1), the processor is informed of the status of the receiver and transmitter

by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see

if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.

Figure 5. Interrupt Mode Operation

Polled Mode Operation

In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the

line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the

receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows polled

mode operation.

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Figure 6. FIFO Polled Mode Operation

DMA Signaling

There are two modes of DMA operation, DMA mode 0 or 1. Bit 3 of the FIFO control register, FCR[3], selects the

DMA mode.

In DMA mode 0 of FIFO disable mode (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1

multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.

Single DMA Transfers (DMA Mode0/FIFO Disable)

The ACE transmitter logic handles characters one at a time and transmits each time a character is written to the

THR.

Block DMA Transfers (DMA Mode1)

The transmitter does not transmit data until a trigger level number of spaces is available in the FIFO. Bits 4 and 5

of the FIFO control register, FCR[5:4], select the trigger level. Bits 7 and 6 of the FIFO control register, FCR[7:6]

set the trigger level for the receive FIFO.

Sleep Mode

Sleep mode is an enhanced feature of the '754C UART. It is enabled when EFR[4], the enhanced functions bit, is

set and when IER[4] is set. Sleep mode is entered when:

•The serial data input line, RX, is idle (see break and time-out conditions).

•The TX FIFO and TX shift register are empty.

•There are no interrupts pending except THR and timeout interrupts.

Sleep mode is not entered if there is data in the RX FIFO.

In sleep mode the UART clock and baud rate clock are stopped. Because most registers are clocked using these

clocks the power consumption is greatly reduced. The UART wakes up when any change is detected on the RX

line, when there is any change in the state of the modem input pins or if data is written to the TX FIFO.

NOTE

Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done

during sleep mode. Therefore it is advisable to disable sleep mode using IER[4] before

writing to DLL or DLH.

Break and Timeout Conditions

An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×

programmed word length) + 12 bits and there is at least one byte stored in the Rx FIFO.

When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].

Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate 16)X

1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset

4 when CLKSEL = low during reset, or MCR[7] is set to 1 after reset

prescaler =

Prescaler Logic

(Divide By 1)

Prescaler Logic

(Divide By 4)

Internal

Oscillator

Logic

Bandrate

Generator

Logic

XTAL1

XTAL2

Internal

Bandrate Clock

For Transmitter

and Receiver

MCR[7] = 0

MCR[7] = 1

Input Clock

Reference

Clock

TL16CP754C, TL16C754C

SLLS644G –DECEMBER 2007–REVISED MAY 2011

www.ti.com

Programmable Baud Rate Generator

The '754C UART contains a programmable baud generator that divides reference clock by a divisor in the range

between 1 and (216−1). The output frequency of the baud rate generator is 16×the baud rate. An additional

divide-by-4 prescaler is also available and can be selected by the CLKSEL pin or MCR[7], as shown in the

following. The formula for the divisor is:

Where

Figure 7 shows the internal prescaler and baud rate generator circuitry.

Figure 7. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and

most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as

no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and

receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency

1.8432 MHz and 3.072 MHz, respectively.

TL16CP754C, TL16C754C

www.ti.com

SLLS644G –DECEMBER 2007–REVISED MAY 2011

Table 5. Baud Rates Using a 1.8432-MHz Crystal

DIVISOR USED PERCENT ERROR

DESIRED TO GENERATE DIFFERENCE BETWEEN

BAUD RATE 16×CLOCK DESIRED AND ACTUAL

50 2304

75 1536

110 1047 0.026

134.5 857 0.058

150 768

300 384

600 192

1200 96

1800 64

2000 58 0.69

2400 48

3600 32

4800 24

7200 16

9600 12

19200 6

38400 3

56000 2 2.86

Table 6. Baud Rates Using a 3.072-MHz Crystal

DIVISOR USED PERCENT ERROR

DESIRED TO GENERATE DIFFERENCE BETWEEN

BAUD RATE 16×CLOCK DESIRED AND ACTUAL

50 3840

75 2560

110 1745 0.026

134.5 1428 0.034

150 1280

300 640

600 320

1200 160

1800 107 0.312

2000 96

2400 80

3600 53 0.628

4800 40

7200 27 1.23

9600 20

19200 10

38400 5

ΩΩ

TL16CP754C, TL16C754C

SLLS644G –DECEMBER 2007–REVISED MAY 2011

www.ti.com

Figure 8 shows the crystal clock circuit reference.

A. For crystal with fundamental frequency from 1 MHz to 24 MHz

B. For input clock frequency higher then 24 MHz, the crystal is not allowed and the oscillator must be used, because the

'754C internal oscillator cell can only support the crystal frequency up to 24 MHz.

Figure 8. Typical Crystal Clock Circuits

TL16CP754C, TL16C754C

www.ti.com

SLLS644G –DECEMBER 2007–REVISED MAY 2011

ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN MAX UNIT

VCC Supply voltage range –0.5 6 V

VIInput voltage range –0.5 VCC + 0.5 V

VOOutput voltage range –0.5 VCC + 0.5 V

TL16C754C 0 70

TAOperating free-air temperature range °C

TL16C754CI –40 85

High K 0 105

TL16C754C

TJJunction temperature Low K 0 122 °C

TL16C754CI –40 105

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 7. TYPICAL PACKAGE THERMAL CHARACTERISTICS

PARAMETER TEST CONDITION(1) TYP UNIT

Low K JEDEC test board, 1s (single signal layer), no air 73.1

flow No air flow 50

θJA Junction-to-free-air thermal resistance °C/W

High K JEDEC test board, 2s2p

(double signal layer, double 400 LFM

buried power plane) 200 LFM

θJC Junction-to-case thermal resistance Cu cold plate measurement process 19 °C/W

θJB Junction-to-board thermal resistance EIA/JESD 51-8 28 °C/W

ΨJT Junction-to-top of package EIA/JESD 51-2 0.95 °C/W

ΨJB Junction-to-board EIA/JESD 51-6 25.8 °C/W

(1) For more details, please refer to TI application note on IC Package Thermal Metrics (SPRA953).

Table 8. TYPICAL PACKAGE WEIGHT

PACKAGE WEIGHT IN GRAMS

64-pin TQFP PM 0.25

RECOMMENDED OPERATING CONDITIONS, VCC = 1.8 V ±10%

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

VCC Supply voltage 1.62 1.8 1.98 V

VIInput voltage 0 VCC V

VIH High-level input voltage 1.4 1.98 V

VIL Low-level input voltage –0.3 0.4 V

VOOutput voltage 0 VCC V

IOH High-level output current All outputs 0.5 mA

IOL Low-level output current All outputs 1 mA

Oscillator/clock speed 16 MHz

TL16CP754C, TL16C754C

SLLS644G –DECEMBER 2007–REVISED MAY 2011

www.ti.com

RECOMMENDED OPERATING CONDITIONS, VCC = 2.5 V ±10%

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

VCC Supply voltage 2.25 2.5 2.75 V

VIInput voltage 0 VCC V

VIH High-level input voltage 1.8 2.75 V

VIL Low-level input voltage –0.3 0.6 V

VOOutput voltage 0 VCC V

IOH High-level output current All outputs 1 mA

IOL Low-level output current All outputs 2 mA

Oscillator/clock speed 24 MHz

RECOMMENDED OPERATING CONDITIONS, VCC = 3.3 V ±10%

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

VCC Supply voltage 3 3.3 3.6 V

VIInput voltage 0 VCC V

VIH High-level input voltage 0.7 ×VCC V

VIL Low-level input voltage 0.3 ×VCC V

VOOutput voltage 0 VCC V

IOH High-level output current All outputs 1.8 mA

IOL Low-level output current All outputs 3.2 mA

Oscillator/clock speed 32 MHz

RECOMMENDED OPERATING CONDITIONS, VCC = 5 V ±10%

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

VCC Supply voltage 5.5 V

VIInput voltage VCC V

Except XIN 0

VIH High-level input voltage V

XIN 0.7 ×VCC

Except XIN 0.8

VIL Low-level input voltage V

XIN 0.3 ×VCC

VOOutput voltage 0 VCC V

IOH High-level output current All outputs 4 mA

IOL Low-level output current All outputs 4 mA

Oscillator/clock speed 48 MHz