TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
QUAD UARTS WITH 64-BYTE FIFO
Check for Samples: TL16CP754C,TL16C754C
1FEATURES
•ST16C654/654D Pin Compatible With •Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
Additional Enhancements •Characterized for Operation From –40°C to
•Support up to 24-MHz Crystal Input Clock 85°C, Available in Commercial and Industrial
(1.5 Mbps) Temperature Grades
•Support up to 48-MHz Oscillator Input Clock •Software-Selectable Baud-Rate Generator
(3 Mbps) for 5-V Operation •Prescaler Provides Additional Divide-by-4
•Support up to 32-MHz Oscillator Input Clock Function
(2 Mbps) for 3.3-V Operation •Programmable Sleep Mode
•Support up to 24-MHz Input Clock (1.5 Mbps) •Programmable Serial Interface Characteristics
for 2.5-V Operation –5-, 6-, 7-, or 8-Bit Characters
•Support up to 16-MHz Input Clock (1 Mbps) for –Even, Odd, or No Parity Bit Generation and
1.8-V Operation Detection
•64-Byte Transmit FIFO –1-, 1.5-, or 2-Stop Bit Generation
•64-Byte Receive FIFO With Error Flags •False Start Bit Detection
•Programmable and Selectable Transmit and •Complete Status Reporting Capabilities in
Receive FIFO Trigger Levels for DMA and Both Normal and Sleep Mode
Interrupt Generation •Line Break Generation and Detection
•Programmable Receive FIFO Trigger Levels for •Internal Test and Loopback Capabilities
Software/Hardware Flow Control •Fully Prioritized Interrupt System Controls
•Software/Hardware Flow Control •Modem Control Functions (CTS, RTS, DSR,
–Programmable Xon/Xoff Characters DTR, RI, and CD)
–Programmable Auto-RTS and Auto-CTS •IrDA Capability
•Optional Data Flow Resume by Xon Any
Character
•RS-485 Mode Support
DESCRIPTION
The '754C is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each
UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock
source, otherwise they operate independently. Another name for the UART function is Asynchronous
Communications Element (ACE), and these terms are used interchangeably. The bulk of this document
describes the behavior of each ACE, with the understanding that four such devices are incorporated into the
'754C. The '754C offers enhanced features. It has a transmission control register (TCR) that stores received
FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY
register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers
provide the user with error indications, operational status, and modem interface control. System interrupts may
be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2007–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
The '754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the
TL16C754CPM device.
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register Address
A0 24 I Map.
Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register Address
A1 23 I Map.
Address bit 2 select. Internal registers address selection. Refer to Table 9 for Register Address
A2 22 I Map.
Carrier detect (active low). These inputs are associated with individual UART channels A
CDA, CDB, 64, 18, I through D. A low on these pins indicates that a carrier has been detected by the modem for that
CDC, CDD 31, 49 channel.
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL
selects the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing
CLKSEL 21 I edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on
CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler
value.
Chip select A, B, C, and D (active low). These pins enable data transfers between the user
CSA, CSB, 7, 11, I CPU and the '754C for the channel(s) addressed. Individual UART sections (A, B, C, D) are
CSC, CSD 38, 42 addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A
through D. A low on the CTS pins indicates the modem or data set is ready to accept transmit
CTSA, CTSB, 2, 16, I data from the '754C. Status can be checked by reading MSR[4]. These pins only affect the
CTSC, CTSD 33, 47 transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR[7]), for hardware flow control operation.
2Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
TERMINAL FUNCTIONS (continued)
TERMINAL I/O DESCRIPTION
NAME NO.
Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring
D0–D2, 53–60 I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a
D3–D7 transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A
DSRA, DSRB, 1, 17, I through D. A low on these pins indicates the modem or data set is powered on and is ready for
DSRC, DSRD 32, 48 data exchange with the UART.
Data terminal ready (active low). These outputs are associated with individual UART channels
A through D. A low on these pins indicates that the '754C is powered on and ready. These pins
DTRA, DTRB, 3, 15, can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR
O
DTRC, DTRD 34, 46 output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0],
or after a reset. These pins can also be used in the RS-485 mode to control an external RS-485
driver or transceiver.
14, 28,
GND Pwr Power signal and power ground
45, 61 Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D.
INTA−D are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable
INTA, INTB, 6, 12, O register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver
INTC, INTD 37, 43 errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is
detected. INTA−D are in the high-impedance state after reset.
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with
MCR[3] to enable or disable the 3-state interrupts INTA-D or override MCR[3] and force
INTSEL –I continuous interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving
this pin low allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to
a 1 to enable the 3-state outputs.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal
IOR 40 I register defined by address bits A0–A2 onto the '754C data bus (D0–D7) for access by an
external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus
IOW 9 I (D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output
RESET 27 I and the receiver input are disabled during reset time. See '754C external reset conditions for
initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A
RIA, RIB, 63, 19, through D. A low on these pins indicates the modem has received a ringing signal from the
I
RIC, RID 30, 50 telephone line. A low-to-high transition on these input pins generates a modem status interrupt,
if it is enabled.
Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
RTSA, RTSB, 5, 13, Writing a 1 in the modem control register (MCR[1]) sets these pins to low, indicating data is
O
RTSC, RTSD 36, 44 available. After a reset, these pins are set to 1. These pins only affect the transmit and receive
operation when auto-RTS function is enabled through the enhanced feature register (EFR[6]),
for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the
'754C. During the local loopback mode, these RX input pins are disabled and TX data is
RXA, RXB, 62, 20, I internally connected to the UART RX input internally. During normal mode, RXn should be held
RXC, RXD 29, 51 high when no data is being received. These outputs also can be used in IrDA mode. See the
IrDA mode section for more information.
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
RXRDY(1) –O FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.
(1) RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.
Copyright ©2007–2011, Texas Instruments Incorporated 3
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL I/O DESCRIPTION
NAME NO.
Transmit data. These outputs are associated with individual serial transmit channel data from
the '754C. During the local loopback mode, the TX input pin is disabled and TX data is
TXA, TXB, 8, 10, O internally connected to the UART RX input. During normal mode, TXn is high when no data is
TXC, TXD 39, 41 being sent. These outputs can also be used in IrDA mode, in which case TXn is low when no
data is being sent. See the IrDA mode section for more information.
Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
TXRDY(2) –O FIFOs, TXRDY A–D. It goes low when there are a trigger level number of spares available. It
goes high when all four TX buffers are full.
4, 35,
VCC Pwr Power supply inputs
52 Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
XTAL1 25 I Figure 10). Alternatively, an external clock can be connected to XTAL1 to provide custom data
rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
XTAL2 26 O oscillator output or buffered clock output.
(2) RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.
4Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
A. The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The Vote logic operates on all bits received.
FUNCTIONAL DESCRIPTION
The '754C UART is pin compatible with the TL16C754B and ST16C654 UARTs. It provides more enhanced
features. All additional features are provided through a special enhanced feature register.
The UART performs serial-to-parallel conversion on data characters received from peripheral devices or modems
and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each
channel of the '754C UART can be read at any time during functional operation by the processor.
The '754C UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software
overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to
64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or
programmable trigger levels. Primary outputs RXRDY and TXRDY allow Signaling of DMA transfers.
The '754C UART has selectable hardware flow control and software flow control. Both schemes significantly
reduce software overhead and increase system efficiency by automatically controlling serial data flow. Hardware
flow control uses the RTS output and CTS input signals. Software flow control uses programmable Xon/Xoff
characters.
The UART includes a programmable baud rate generator that can divide the timing reference clock input by a
divisor between 1 and (216–1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate
the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the
divide-by-1 is selected when CLKSEL is a logic 1.
Trigger Levels
The '754C UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in
effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.
The programmable trigger levels are available via the TLR.
6Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
Hardware Flow Control
Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be
enabled/disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output
when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is
sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated
during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive
FIFO servicing latency.
Auto-RTS
Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS
functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the
RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is
reached, RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the
deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
A. N = receiver FIFO trigger level B.
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.
Figure 1. RTS Functional Timing
Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error can result. Figure 2 shows CTS functional timing, and Figure 3 shows
an example of autoflow control.
Copyright ©2007–2011, Texas Instruments Incorporated 7
Serial to
Parallel
Flow
Control
Parallel to
Serial
Flow
Control
RX
FIFO
TX
FIFO
Parallel to
Serial
Flow
Control
Serial to
Parallel
Flow
Control
TX
FIFO
RX
FIFO
D7- D0 D7- D0
UART 1 UART 2
RX
RTS
TX
CTS
TX
CTS
RX
RTS
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
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A. When CTS is low, the transmitter keeps sending serial data out.
B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the
current byte, but it does not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. CTS Functional Timing
Figure 3. Autoflow Control (Auto-RTS and Auto-CTS) Example
Software Flow Control
Software flow control is enabled through the enhanced feature register and the modem control register. Different
combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. Table 1
shows software flow control options.
Two other enhanced features relate to S/W flow control:
•Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff
character.
NOTE
It is possible that an Xon1 character is recognized as an Xon Any character, which could
cause an Xon2 character to be written to the RX FIFO.
•Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the
Xoff interrupt {IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The
special character is transferred to the RX FIFO.
8Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 1. Software Flow Control Options EFR[3:0]
BIT 3 BIT 2 BIT 1 BIT 0 Tx, Rx SOFTWARE FLOW CONTROLS
0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2
1 1 X X Transmit Xon1, Xon2: Xoff1, Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1 X X 0 1
X X 0 1 Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
1 0 1 1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2, Xoff2
0 1 1 1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1, Xon2: Xoff1, Xoff2
1 1 1 1 Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
No transmit flow control
0 0 1 1 Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
When software flow control operation is enabled, the '754C compares incoming data with Xoff1/2 programmed
characters (in certain cases Xoff1 and Xoff2 must be received sequentially(1)). When an Xoff character is
received, transmission is halted after completing transmission of the current character. Xoff character detection
also sets IIR[4] and causes INT to go high (if enabled via IER[5]).
To resume transmission an Xon1/2 character must be received (in certain cases Xon1 and Xon2 must be
received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt
disappears.
NOTE
If a parity, framing or break error occurs while receiving a software flow control character,
this character is treated as normal data and is written to the RCV FIFO.
Xoff1/2 characters are transmitted when the RX FIFO has passed the programmed trigger level TCR[3:0].
Xon1/2 characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR[7:4].
NOTE
If, after an Xoff character has been sent, software flow control is disabled, the UART
transmits Xon characters automatically to enable normal transmission to proceed. A
feature of the '754C UART design is that if the software flow combination (EFR[3:0])
changes after an Xoff has been sent, the originally programmed Xon is automatically sent.
If the RX FIFO is still above the trigger level the newly programmed Xoff1/2 is transmitted.
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the
FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least
significant bits of Xoff1,2/Xon1,2 are transmitted. The transmission of 5, 6, or 7 bits of a character is seldom
done, but this functionality is included to maintain compatibility with earlier designs.
It is assumed that software flow control and hardware flow control are never enabled simultaneously. Figure 4
shows a software flow control example.
(1) When pairs of Xon/Xoff characters are programmed to occur sequentially, received Xon1/Xoff1 characters will be written to the Rx FIFO
if the subsequent character is not Xon2/Xoff2.
Copyright ©2007–2011, Texas Instruments Incorporated 9
UART 1
Parallel to Serial
Serial to Parallel
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-1 Word
Transmit
FIFO
Serial to Parallel
Parallel to Serial
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
Receive
FIFO
Data
Xoff - Xon - Xoff
Compare
Programmed
Xon- Xoff
Characters
UART 2
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
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Figure 4. Software Flow Control Example
Software Flow Control Example
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with
single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon
threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52.
UART1 begins transmission and sends 52 characters, at which point UART2 generates an interrupt to its
processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 continues sending
characters until a total of 60 characters have been sent. At this time UART2 will transmit a 0F to UART1,
informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff
character. Now UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level
drops to 32. UART2 now sends a 0D to UART1, informing UART1 to resume transmission.
Reset
Table 2 summarizes the state of outputs after reset.
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 2. Register Reset Functions(1)
RESET
REGISTER RESET STATE
CONTROL
Interrupt enable register RESET All bits cleared
Interrupt identification register RESET Bit 0 is set. All other bits cleared.
FIFO control register RESET All bits cleared
Line control register RESET Reset to 00011101 (1D hex).
Bit 6–0 cleared. Bit 7 reflects the inverse of the
Modem control register RESET CLKSEL pin value.
Line status register RESET Bits 5 and 6 set. All other bits cleared.
Modem status register RESET Bits 0–3 cleared. Bits 4–7 input signals.
Bit 6–0 is cleared. Bit 7 reflects the inverse of the
Enhanced feature register RESET CLKSEL pin value.
Receiver holding register RESET Pointer logic cleared
Transmitter holding register RESET Pointer logic cleared
Transmission control register RESET All bits cleared
Trigger level register RESET All bits cleared
Alternate function register RESET All bits (except AFR4) cleared; AFR4 set
(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,
i.e., they hold their initialization values during reset.
Table 3 summarizes the state of outputs after reset.
Table 3. Signal Reset Functions
SIGNAL RESET CONTROL RESET STATE
TX RESET High
RTS RESET High
DTR RESET High
RXRDY RESET High
TXRDY RESET Low
Interrupts
The '754C UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The
interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an
interrupt generation. The IER also can disable the interrupt system by clearing bits 0−3, 5−7. When an interrupt
is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides the type
of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
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TL16CP754C, TL16C754C
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Table 4. Interrupt Control Functions
PRIORITY INTERRUPT
IIR[5–0] INTERRUPT SOURCE INTERRUPT RESET METHOD
LEVEL TYPE
000001 None None None None
000110 1 Receiver line OE, FE, PE, or BI errors occur in FE <PE <BI: All erroneous characters are
status characters in the RX FIFO read from the RX FIFO. OE: Read LSR
001100 2 RX timeout Stale data in RX FIFO Read RHR
000100 2 RHR interrupt DRDY (data ready) Read RHR
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
000010 3 THR interrupt TFE (THR empty) Read IIR OR a write to the THR
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
000000 4 Modem status MSR[3:0]= 0 Read MSR
010000 5 Xoff interrupt Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR
100000 6 CTS, RTS RTS pin or CTS pin change state from Read IIR
active (low) to inactive (high)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the Rx
FIFO. Reading the Rx FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the Rx FIFO is empty, then LSR[4–2] is all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is1), the processor is informed of the status of the receiver and transmitter
by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see
if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.
Figure 5. Interrupt Mode Operation
Polled Mode Operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows polled
mode operation.
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Figure 6. FIFO Polled Mode Operation
DMA Signaling
There are two modes of DMA operation, DMA mode 0 or 1. Bit 3 of the FIFO control register, FCR[3], selects the
DMA mode.
In DMA mode 0 of FIFO disable mode (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
Single DMA Transfers (DMA Mode0/FIFO Disable)
The ACE transmitter logic handles characters one at a time and transmits each time a character is written to the
THR.
Block DMA Transfers (DMA Mode1)
The transmitter does not transmit data until a trigger level number of spaces is available in the FIFO. Bits 4 and 5
of the FIFO control register, FCR[5:4], select the trigger level. Bits 7 and 6 of the FIFO control register, FCR[7:6]
set the trigger level for the receive FIFO.
Sleep Mode
Sleep mode is an enhanced feature of the '754C UART. It is enabled when EFR[4], the enhanced functions bit, is
set and when IER[4] is set. Sleep mode is entered when:
•The serial data input line, RX, is idle (see break and time-out conditions).
•The TX FIFO and TX shift register are empty.
•There are no interrupts pending except THR and timeout interrupts.
Sleep mode is not entered if there is data in the RX FIFO.
In sleep mode the UART clock and baud rate clock are stopped. Because most registers are clocked using these
clocks the power consumption is greatly reduced. The UART wakes up when any change is detected on the RX
line, when there is any change in the state of the modem input pins or if data is written to the TX FIFO.
NOTE
Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done
during sleep mode. Therefore it is advisable to disable sleep mode using IER[4] before
writing to DLL or DLH.
Break and Timeout Conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×
programmed word length) + 12 bits and there is at least one byte stored in the Rx FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
Copyright ©2007–2011, Texas Instruments Incorporated 13
Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate 16)X
1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset
4 when CLKSEL = low during reset, or MCR[7] is set to 1 after reset
prescaler =
Prescaler Logic
(Divide By 1)
Prescaler Logic
(Divide By 4)
Internal
Oscillator
Logic
Bandrate
Generator
Logic
XTAL1
XTAL2
Internal
Bandrate Clock
For Transmitter
and Receiver
MCR[7] = 0
MCR[7] = 1
Input Clock
Reference
Clock
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Programmable Baud Rate Generator
The '754C UART contains a programmable baud generator that divides reference clock by a divisor in the range
between 1 and (216−1). The output frequency of the baud rate generator is 16×the baud rate. An additional
divide-by-4 prescaler is also available and can be selected by the CLKSEL pin or MCR[7], as shown in the
following. The formula for the divisor is:
Where
Figure 7 shows the internal prescaler and baud rate generator circuitry.
Figure 7. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as
no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and
receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
14 Copyright ©2007–2011, Texas Instruments Incorporated
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www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 5. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED PERCENT ERROR
DESIRED TO GENERATE DIFFERENCE BETWEEN
BAUD RATE 16×CLOCK DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 6. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED PERCENT ERROR
DESIRED TO GENERATE DIFFERENCE BETWEEN
BAUD RATE 16×CLOCK DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
Copyright ©2007–2011, Texas Instruments Incorporated 15
Ω
ΩΩ
ΩΩ
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Figure 8 shows the crystal clock circuit reference.
A. For crystal with fundamental frequency from 1 MHz to 24 MHz
B. For input clock frequency higher then 24 MHz, the crystal is not allowed and the oscillator must be used, because the
'754C internal oscillator cell can only support the crystal frequency up to 24 MHz.
Figure 8. Typical Crystal Clock Circuits
16 Copyright ©2007–2011, Texas Instruments Incorporated
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VCC Supply voltage range –0.5 6 V
VIInput voltage range –0.5 VCC + 0.5 V
VOOutput voltage range –0.5 VCC + 0.5 V
TL16C754C 0 70
TAOperating free-air temperature range °C
TL16C754CI –40 85
High K 0 105
TL16C754C
TJJunction temperature Low K 0 122 °C
TL16C754CI –40 105
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 7. TYPICAL PACKAGE THERMAL CHARACTERISTICS
PARAMETER TEST CONDITION(1) TYP UNIT
Low K JEDEC test board, 1s (single signal layer), no air 73.1
flow No air flow 50
θJA Junction-to-free-air thermal resistance °C/W
High K JEDEC test board, 2s2p
(double signal layer, double 400 LFM
buried power plane) 200 LFM
θJC Junction-to-case thermal resistance Cu cold plate measurement process 19 °C/W
θJB Junction-to-board thermal resistance EIA/JESD 51-8 28 °C/W
ΨJT Junction-to-top of package EIA/JESD 51-2 0.95 °C/W
ΨJB Junction-to-board EIA/JESD 51-6 25.8 °C/W
(1) For more details, please refer to TI application note on IC Package Thermal Metrics (SPRA953).
Table 8. TYPICAL PACKAGE WEIGHT
PACKAGE WEIGHT IN GRAMS
64-pin TQFP PM 0.25
RECOMMENDED OPERATING CONDITIONS, VCC = 1.8 V ±10%
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 1.62 1.8 1.98 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.4 1.98 V
VIL Low-level input voltage –0.3 0.4 V
VOOutput voltage 0 VCC V
IOH High-level output current All outputs 0.5 mA
IOL Low-level output current All outputs 1 mA
Oscillator/clock speed 16 MHz
Copyright ©2007–2011, Texas Instruments Incorporated 17
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS, VCC = 2.5 V ±10%
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 2.25 2.5 2.75 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.8 2.75 V
VIL Low-level input voltage –0.3 0.6 V
VOOutput voltage 0 VCC V
IOH High-level output current All outputs 1 mA
IOL Low-level output current All outputs 2 mA
Oscillator/clock speed 24 MHz
RECOMMENDED OPERATING CONDITIONS, VCC = 3.3 V ±10%
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIInput voltage 0 VCC V
VIH High-level input voltage 0.7 ×VCC V
VIL Low-level input voltage 0.3 ×VCC V
VOOutput voltage 0 VCC V
IOH High-level output current All outputs 1.8 mA
IOL Low-level output current All outputs 3.2 mA
Oscillator/clock speed 32 MHz
RECOMMENDED OPERATING CONDITIONS, VCC = 5 V ±10%
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 5.5 V
VIInput voltage VCC V
Except XIN 0
VIH High-level input voltage V
XIN 0.7 ×VCC
Except XIN 0.8
VIL Low-level input voltage V
XIN 0.3 ×VCC
VOOutput voltage 0 VCC V
IOH High-level output current All outputs 4 mA
IOL Low-level output current All outputs 4 mA
Oscillator/clock speed 48 MHz
18 Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS, VCC = 1.8 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH =–0.5 mA 1.3 V
VOL Low-level output voltage IOL = 1 mA 0.5 V
VCC = 1.98 V, VSS = 0,
IIInput current 10 μA
VI= 0 to 1.98 V, All other terminals floating
VCC = 1.98 V, VSS = 0,
High-impedance state VO= 0 to 1.98 V,
IOZ ±20 μA
output current Chip selected in write mode or chip deselect
VCC = 1.98 V, TA= 0°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC Supply current 4 mA
All other inputs at 0.4 V, XTAL1 at 16 MHz,
No load on outputs, Baud rate = 1 Mbit/s
CI(CLK) Clock input capacitance 5 7 pF
VCC = 0,
CO(CLK) Clock output capacitance 5 7 pF
VSS = 0,
f = 1 MHz, TA= 25°C,
CIInput capacitance 6 10 pF
All other terminals grounded
COOutput capacitance 10 15 pF
ELECTRICAL CHARACTERISTICS, VCC = 2.5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH =–1 mA 1.8 V
VOL Low-level output voltage IOL = 2 mA 0.5 V
VCC = 2.75 V, VSS = 0,
IIInput current 10 μA
VI= 0 to 2.75 V, All other terminals floating
VCC = 2.75 V, VSS = 0,
High-impedance state VO= 0 to 2.75 V,
IOZ ±20 μA
output current Chip selected in write mode or chip deselect
VCC = 2.75 V, TA= 0°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC Supply current 6 mA
All other inputs at 0.6 V, XTAL1 at 24 MHz,
No load on outputs, Baud rate = 1.5 Mbit/s
CI(CLK) Clock input capacitance 5 7 pF
VCC = 0,
CO(CLK) Clock output capacitance 5 7 pF
VSS = 0,
f = 1 MHz, TA= 25°C,
CIInput capacitance 6 10 pF
All other terminals grounded
COOutput capacitance 10 15 pF
Copyright ©2007–2011, Texas Instruments Incorporated 19
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VCC = 3.3 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH =–1.8 mA 2.4 V
VOL Low-level output voltage IOL = 3.2 mA 0.5 V
VCC = 3.6 V, VSS = 0,
IIInput current 10 μA
VI= 0 to 3.6 V, All other terminals floating
VCC = 3.6 V, VSS = 0,
High-impedance state VO= 0 to 3.6 V,
IOZ ±20 μA
output current Chip selected in write mode or chip deselect
VCC = 3.6 V, TA= 0°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC Supply current 12 mA
All other inputs at 0.8 V, XTAL1 at 32 MHz,
No load on outputs, Baud rate = 2 Mbit/s
CI(CLK) Clock input capacitance 5 7 pF
VCC = 0,
CO(CLK) Clock output capacitance 5 7 pF
VSS = 0,
f = 1 MHz, TA= 25°C,
CIInput capacitance 6 10 pF
All other terminals grounded
COOutput capacitance 10 15 pF
ELECTRICAL CHARACTERISTICS, VCC = 5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH =–4 mA 4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
VCC = 5.5 V, VSS = 0,
IIInput current 10 μA
VI= 0 to 5.5 V, All other terminals floating
VCC = 5.5 V, VSS = 0,
High-impedance state VO= 0 to 5.5 V,
IOZ ±20 μA
output current Chip selected in write mode or chip deselect
VCC = 5.5 V, TA= 0°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC Supply current 28 mA
All other inputs at 0.8 V, XTAL1 at 48 MHz,
No load on outputs, Baud rate = 3 Mbit/s
CI(CLK) Clock input capacitance 5 7 pF
VCC = 0,
CO(CLK) Clock output capacitance 5 7 pF
VSS = 0,
f = 1 MHz, TA= 25°C,
CIInput capacitance 6 10 pF
All other terminals grounded
COOutput capacitance 10 15 pF
20 Copyright ©2007–2011, Texas Instruments Incorporated
Frequency, f (MHz)
Div = 10
Div = 1
02
0.0
0.5
1.0
1.5
2.0
2.5
3.0
46 8 10 12 14 16
Supply Current, I (mA)
CC
V = 1.8 V,
CC
T = 25°C
A
Frequency, f (MHz)
Div = 10
Div = 1
03
0
1
2
3
4
5
6
69 12 15 18 21 24
Supply Current, I (mA)
CC
V = 2.5 V,
CC
T = 25°C
A
Frequency, f (MHz)
Div = 10
Div = 1
04
0
2
4
6
8
10
12
812 16 20 24 28 32
Supply Current, I (mA)
CC
V = 3.3 V,
CC
T = 25°C
A
Frequency, f (MHz)
Div = 10
Div = 1
06
0
5
10
15
20
25
30
12 18 24 30 36 42 48
Supply Current, I (mA)
CC
V = 5 V,
CC
T = 25°C
A
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
TYPICAL CHARACTERISTICS
All channels active
Figure 9. Supply Current vs Frequency (VCC = 1.8 V) Figure 10. Supply Current vs Frequency (VCC = 2.5 V)
Figure 11. Supply Current vs Frequency (VCC = 3.3 V) Figure 12. Supply Current vs Frequency (VCC = 5 V)
Copyright ©2007–2011, Texas Instruments Incorporated 21
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
TIMING REQUIREMENTS
TA= 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted) LIMITS
TEST
PARAMETER 1.8 V 2.5 V 3.3 V 5 V UNIT
CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
tRES Reset pulse width 200 200 200 200 ns
ET
CPCP Clock period 63 42 32 20 ns
t3w Oscillator/Clock speed 16 24 32 48 MHz
t6s Address setup time 20 15 10 5 ns
t6h Address hold time See Figure 13 and Figure 14 15 10 7 5 ns
t7w IOR strobe width See Figure 13 and Figure 14 85 70 50 40 ns
t9d Read cycle delay See Figure 14 85 70 60 50 ns
t12d Delay from IOR to data See Figure 14 65 50 35 25 ns
t12h Data disable time 35 25 20 15 ns
t13w IOW strobe width See Figure 13 85 70 50 40 ns
t15d Write cycle delay See Figure 13 85 70 60 50 ns
t16s Data setup time See Figure 13 40 30 20 15 ns
t16h Data hold time See Figure 13 35 25 15 10 ns
t17d Delay from IOW to output 50 pF load, See Figure 15 60 40 30 20 ns
Delay to set interrupt from
t18d 50 pF load, See Figure 15 70 55 45 35 ns
MODEM input
Delay to reset interrupt from
t19d 50 pF load 80 55 40 30 ns
IOR
t20d Delay from stop to set interrupt See Figure 16 1 1 1 1 Baudrate
Delay from IOR to reset
t21d 50 pF load, See Figure 16 55 45 35 25 ns
interrupt
t22d Delay from stop to interrupt See Figure 19 1 1 1 1 Baudrate
Delay from initial IOW reset to
t23d See Figure 19 8 24 8 24 8 24 8 24 Baudrate
transmit star
Delay from IOW to reset
t24d See Figure 19 75 45 35 25 ns
interrupt
t25d Delay from stop to set RXRDY See Figure 17 and Figure 18 1 1 1 1 Baudrate
t26d Delay from IOR to reset RXRDY See Figure 17 and Figure 18 1 1 1 1 μs
t27d Delay from IOW to set TXRDY See Figure 20 and Figure 21 70 60 50 40 ns
t28d Delay from start to reset TXRDY See Figure 20 and Figure 21 16 16 16 16 Baudrate
22 Copyright ©2007–2011, Texas Instruments Incorporated
Start
Bit
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
DataBits(5–8)
t20d
t21d
RX(A−D)
INT(A−D)
IOR
D1 D2 D3 D4 D5 D6 D7
D0
Active
Active
6DataBits
7DataBits
16-BaudRateClock
5DataBits
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Figure 15. Modem/Output Timing
Figure 16. Receive Timing
24 Copyright ©2007–2011, Texas Instruments Incorporated
16-BaudRateClock
Start
Bit
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
DataBits(5–8)
T27d
t28d
TX(A–D)
TXRDY (A–D)
TXRDY
IOW
D0 D7D1 D4D2 D5D3 D6
Active
Transmitter
NotReady
Byte1
Active
TransmitterReady
D0–D7
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Figure 19. Transmit Timing
Figure 20. Transmit Ready Timing in None FIFO Mode
26 Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
PRINCIPLES OF OPERATION
Register Map
Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The
programming combinations for register selection are shown in Table 9.
Table 9. Register Map –Read/Write Properties(1)
A[2] A[1] A[0] READ MODE WRITE MODE
0 0 0 Receive holding register (RHR) Transmit holding register (THR)
0 0 1 Interrupt enable register (IER) Interrupt enable register
0 1 0 Interrupt identification register (IIR) FIFO control register (FCR)
0 1 1 Line control register (LCR) Line control register
1 0 0 Modem control register (MCR) Modem control register
1 0 1 Line status register (LSR)
1 1 0 Modem status register (MSR)
1 1 1 Scratch register (SPR) Scratch register (SPR)
0 0 0 Divisor latch LSB (DLL) Divisor latch LSB (DLL)
0 0 1 Divisor latch MSB (DLH) Divisor latch MSB (DLH)
0 1 0 Alternate function register (AFR) Alternate function register (AFR)
0 1 0 Enhanced feature register (EFR) Enhanced feature register
1 0 0 Xon-1 word Xon-1 word
1 0 1 Xon-2 word Xon-2 word
1 1 0 Xoff-1 word Xoff-1 word
1 1 1 Xoff-2 word Xoff-2 word
1 1 0 Transmission control register (TCR) Transmission control register
1 1 1 Trigger level register (TLR) Trigger level register
1 1 1 FIFO ready register
(1) DLL and DLH are accessible only when LCR bit 7 is 1, and AFR is only accessible when LCR[7:5] = 100.
Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).
Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e. EFR[4] and MCR[6]
are read/write enables.
FCR FIFORdy register is accessible when any CS A–D = 0, MCR[2] = 1 and loopback MCR [4] = 0 is disabled.
MCR[7] can only be modified when EFR[4] is set.
Table 10 lists and describes the '754C internal registers.
28 Copyright ©2007–2011, Texas Instruments Incorporated
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 10. '754C Internal Registers(1) (2)
SPECIAL READ/
ADDR REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CONSIDERATIONS WRITE
000 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 Read
000 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 Write
CTS RTS Xoff Modem Rx line THR Rx data
Sleep Read/
001 IER interrupt interrupt interrupt status status empty available
mode write
enable enable enable interrupt interrupt interrupt interrupt
LCR[7] = 0 DMA
Rx trigger Rx trigger TX trigger TX trigger Resets Resets Rx Enables
010 FCR mode Write
level level level level Tx FIFO FIFO FIFOs
select
Interrupt Interrupt Interrupt Interrupt
010 IIR FCR(0) FCR(0) CTS, RTS Xoff priority Bit priority priority Bit Read
status
2 Bit 1 0
DLAB and Break Parity type Parity No. of Word Word Read/
None 011 LCR EFR Sets parity
control bit select enable stop bits length length write
enable
1×or 4×TCR and Enable IRQ FIFORdy Read/
100 MCR Xon any RTS DTR
clock TLR enable loopback enable Enable write
Error in Rx THR and THR Break Framing Parity Overrun Data in
101 LSR Read
LCR[7:0] ≠FIFO TSR empty empty interrupt error error error receiver
1011 1111 110 MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS Read
Read/
111 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
Read/
000 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
LCR[7] = 1 Read/
001 DLH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write
Read/
LCR[7:0] = 100 010 AFR DLY2 DLY1 DLY0 RCVEN 485LG 485RN IREN CONC write
Special Enable S/W flow S/W flow S/W flow S/W flow Read/
010 EFR Auto-CTS Auto-RTS character enhanced- control Bit control control Bit control Bit write
detect functions 3 Bit 2 1 0
Read/
100 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
LCR[7:0] = Read/
1011 1111 101 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
Read/
110 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
Read/
111 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
Read/
110 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
EFR[4] = 1 and
MCR[6] = 1 Read/
111 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 write
MCR[4] = 0 and RX FIFO RX FIFO RX FIFO RX FIFO TX FIFO TX FIFO TX FIFO TX FIFO
111 FIFORdy Read
MCR[2] = 1 D status C status B status A status D status C status B status A status
(1) Bits represented by shaded cells can only be modified if EFR[4] is enabled, i.e., if enhanced functions are enabled.
(2) Refer to the notes under Table 9 for more register access information.
Receiver Holding Register (RHR)
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The
RHR is actually a 64-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel
data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled,
location zero of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RHR also
stores the error status bits associated with each character.
Copyright ©2007–2011, Texas Instruments Incorporated 29
TL16CP754C, TL16C754C
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Transmit Holding Register (THR)
The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The
transmit holding register is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is
converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location zero of the FIFO is
used to store the byte. Characters are lost if overflow occurs.
FIFO Control Register (FCR)
This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and
receiver trigger levels, and selecting the type of DMA Signaling. Table 11 shows FIFO control register bit
settings.
Table 11. FIFO Control Register (FCR) Bit Settings
BIT NO. BIT SETTINGS
0 = Disable the transmit and receive FIFOs
01 = Enable the transmit and receive FIFOs
0 = No change
11 = Clears the receive FIFO and resets it’s counter logic to zero. Will return to zero after clearing FIFO.
0 = No change
21 = Clears the transmit FIFO and resets it’s counter logic to zero. Will return to zero after clearing FIFO.
0 = DMA Mode 0
31 = DMA Mode 1
Sets the trigger level for the TX FIFO:
00 –8 spaces
5:4(1) 01 –16 spaces
10 –32 spaces
11 –56 spaces
Sets the trigger level for the RX FIFO:
00 –1 characters
7:6 01 –4 characters
10 –56 characters
11 –60 characters
(1) FCR[5−4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced
function.
Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 12 shows line control register bit settings.
30 Copyright ©2007–2011, Texas Instruments Incorporated
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 12. Line Control Register (LCR) Bit Settings
BIT NO. BIT SETTINGS
Specifies the word length to be transmitted or received.
00 –5 bits
1:0 01 –6 bits
10 −7 bits
11 –8 bits
Specifies the number of stop bits:
0–1 stop bits (Word length = 5, 6, 7, 8)
21–1.5 stop bits (Word length = 5)
1–2 stop bits (Word length = 6, 7, 8) 3
0 = No parity
31 = A parity bit is generated during transmission and the receiver checks for received parity.
0 = Odd parity is generated (if LCR[3] = 1)
41 = Even parity is generated (if LCR[3] = 1)
Selects the forced parity format (if LCR(3) = 1)
5 If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.
If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.
Break control bit.
6 0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
0 = Normal operating condition
71 = Divisor latch enable
Line Status Register (LSR)
Table 13 shows line status register bit settings.
Table 13. Line Status Register (LSR) Bit Settings
BIT NO. BIT SETTINGS
0 = No data in the receive FIFO
01 = At least one character in the RX FIFO
0 = No overrun error
11 = Overrun error has occurred.
0 = No parity error in data being read from RX FIFO
21 = Parity error in data being read from RX FIFO
0 = No framing error in data being read from RX FIFO
31 = Framing error occurred in data being read from RX FIFO (i.e., received data did not have a valid stop bit)
0 = No break condition
41 = A break condition occurred and associated byte is 00. (i.e., RX was low for at least one character time frame).
0 = Transmit hold register is NOT empty
5 1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is
enabled.
0 = Transmitter hold AND shift registers are not empty.
61 = Transmitter hold AND shift registers are empty.
0 = Normal operation
7 1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no
errors are present in the FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO
(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is
output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
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LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 14 shows modem control register bit settings.
Table 14. Modem Control Register (MCR) Bit Settings(1)
BIT NO. BIT SETTINGS
0 = Force DTR output to inactive (high)
01 = Force DTR output to active (low). In loopback controls MSR[5].
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low).
1In loopback controls MSR[4].
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
0 Disables the FIFORdy register
2 1 Enable the FIFORdy register.
In loopback controls MSR[6].
0 = Forces the IRQ(A–D) outputs to high-impedance state
3 1 = Forces the IRQ(A–D) outputs to the active state.
In loopback controls MSR[7].
0 = Normal operating mode
1 = Enable local loopback mode (internal)
4In this mode the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input
internally.
0 = Disable Xon Any function
51 = Enable Xon Any function
0 = No action
61 = Enable access to the TCR and TLR registers.
0 = Divide by one clock input
7 1 = Divide by four clock input
This bit reflects the inverse of the CLKSEL pin value at the trailing edge of the RESET pulse.
(1) MCR[7:5] can only be modified when EFR[4] is set i.e., EFR[4] is a write enable.
32 Copyright ©2007–2011, Texas Instruments Incorporated
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SLLS644G –DECEMBER 2007–REVISED MAY 2011
Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the modem, data set, or
peripheral device to the processor. It also indicates when a control input from the modem changes state.
Table 15 shows modem status register bit settings.
Table 15. Modem Status Register (MSR) Bit Settings(1)
BIT NO. BIT SETTINGS
0 Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.
1 Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.
2 Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.
3 Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read.
4 This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input.
5 This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input.
6 This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input.
7 This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input.
(1) The primary inputs RI, CD, CTS, DSR are all active low but their registered equivalents in the MSR and MCR (in loopback) registers are
active high.
Interrupt Enable Register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR
interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in
response to interrupt generation. Table 16 shows interrupt enable register bit settings.
Table 16. Interrupt Enable Register (IER) Bit Settings(1)
BIT NO. BIT SETTINGS
0 = Disable the RHR interrupt
01 = Enable the RHR interrupt
0 = Disable the THR interrupt
11 = Enable the THR interrupt
0 = Disable the receiver line status interrupt
21 = Enable the receiver line status interrupt
0 = Disable the modem status register interrupt
31 = Enable the modem status register interrupt
0 = Disable sleep mode
41 = Enable sleep mode
0 = Disable the Xoff interrupt
51 = Enable the Xoff interrupt
0 = Disable the RTS interrupt
61 = Enable the RTS interrupt
0 = Disable the CTS interrupt
71 = Enable the CTS interrupt
(1) IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable.
Re-enabling IER[1] will cause a new interrupt, if the THR is below the threshold.
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TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
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Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17
shows interrupt identification register bit settings.
Table 17. Interrupt Identification Register (IIR) Bit
Settings
BIT NO. BIT SETTINGS
0 = An interrupt is pending
01 = No interrupt is pending
3:1 3-Bit encoded interrupt. See Table 16.
4 1 = Xoff/Special character has been detected.
5 CTS/RTS low to high change of state
7:6 Mirror the contents of FCR[0]
The interrupt priority list is illustrated in Table 18.
Table 18. Interrupt Priority List
PRIORITY BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INTERRUPT SOURCE
LEVEL
1 0 0 0 1 1 0 Receiver line status error
2 0 0 1 1 0 0 Receiver timeout interrupt
2 0 0 0 1 0 0 RHR interrupt
3 0 0 0 0 1 0 THR interrupt
4 0 0 1 0 0 0 Modem interrupt
5 0 1 0 0 0 0 Received Xoff signal/special character
6 1 0 0 0 0 0 CTS, RTS change of state from active (low) to inactive (high)
Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the enhanced feature
register bit settings.
Table 19. Enhanced Feature Register (EFR) Bit Settings
BIT NO. BIT SETTINGS
3:0 Combinations of software flow control can be selected by programming bit 3−bit 0. See Table 1.
Enhanced functions enable bit.
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5].
41 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write
enable.
0 = Normal operation
5 1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.
RTS flow control enable bit
0 = Normal operation
61 = RTS flow control is enabled i.e., RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is reached,
and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.
CTS flow control enable bit
7 0 = Normal operation
1 = CTS flow control is enabled i.e., transmission is halted when a high signal is detected on the CTS pin.
34 Copyright ©2007–2011, Texas Instruments Incorporated
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Divisor Latches (DLL, DLH)
Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH,
stores the most significant part of the divisor. DLL stores the least significant part of the division.
DLL and DLH can only be written to before sleep mode is enabled (i.e., before IER[4] is set).
Transmission Control Register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to start/stop transmission during
hardware/software flow control. Table 20 shows transmission control register bit settings.
Table 20. Transmission Control Register (TCR) Bit
Settings
BIT NO. BIT SETTINGS
3:0 RCV FIFO trigger level to HALT transmission (0–60)
7:4 RCV FIFO trigger level to RESTORE transmission (0–60)
TCR trigger levels are available from 0–60 bytes with a granularity of four.
TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that
TCR[3:0] >TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must
be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 4−60 can be programmed with a granularity of 4. Table 21 shows trigger level
register bit settings.
Table 21. Trigger Level Register (TLR) Bit Settings
BIT NO. BIT SETTINGS
Transmit FIFO trigger levels (4–60), number of spaces
3:0 available
RCV FIFO trigger levels (4–60), number of characters
7:4 available
TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are zero, then the
selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger
levels. Trigger levels from 4–60 bytes are available with a granularity of four. The TLR should be programmed for
N/4, where N is the desired trigger level.
FIFO Ready Register
The FIFO ready register provides real-time status of the transmit and receive FIFOs. Table 22 shows the FIFO
ready register bit settings.
Table 22. FIFO Ready Register
BIT NO. BIT SETTINGS
0 = There are less than a TX trigger level number of spaces available in the TX FIFO.
3:0 1 = There are at least a TX trigger level number of spaces available in the TX FIFO
0 = There are less than a RX trigger level number of characters in the RX FIFO.
7:4 1 = The RX FIFO has more than a RX trigger level number of characters available for reading OR a timeout condition
has occurred.
The FIFORdy register is a read only register and can be accessed when any of the four UARTs are selected CS
A–D = 0, MCR[2] (FIFORdy Enable) is a 1 and loopback is disabled. Its address space is 111.
Copyright ©2007–2011, Texas Instruments Incorporated 35
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Alternate Function Register (AFR)
The alternate function register (AFR) is used to enable some extra functionality beyond the capabilities of the
original TL16C754. The first of these is a concurrent write mode, which can be useful in more expediently setting
up all four UART channels. The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode
with baud rates from 2400 to 115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by
providing an output pin (DTRx) per channel, which is timed to keep the RS-485 driver enabled as long as
transmit data is pending.
The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.
Table 23. Alternate Function Register (AFR) Bit Settings
BIT NO. BIT SETTINGS
CONC enables the concurrent write of all four (754) or two (752) channels simultaneously,
0 which helps speed up initialization. Ensure that any indirect addressing modes have been
enabled before using.
IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps and use of this
1mode at higher speeds is not recommended.
485EN enables the half duplex RS-485 mode and causes the DTRx output to be set high
whenever there is any data in the THR or TSR and to be held high until the delay set by
2 DLY3:0 has expired, at which time it will be set low. The DTRx output is intended to drive
the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts will be
held off until the TSR is empty, unless 485LG is set.
485LG is set when the 485EN is set. This bit indicates that a relatively large data block is
being set, requiring more than a single load of the xmt fifo. In this case, the transmitter
3interrupts occur as in the standard RS-232 mode, either when the xmt fifo contents drop
below the xmt threshold or when the xmt fifo is empty.
RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in
or snoop on the RS485 traffic or IrDA traffic. RS485 mode is generally considered half
duplex, and usually a node is either driving or receiving, but there can be cases when it is
advantageous to verify what you are sending. This can be used to detect collisions or as
part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the
receiver will store any data presented on RX, if any. Note that implies that the external
RS485 receiver is enabled. Whenever 485EN is cleared, the serial receiver is enabled for
normal full duplex RS232 traffic. If RCVEN is cleared while 485EN is set, the receiver will
be disabled while that channel is transmitting. Standard IrDA (SIR) is also considered half
4duplex. Often the light energy from the transmitting LED is coupled back into the receiving
PIN diode, which creates an input data stream that is not of interest to the host. Disabling
the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading
the data. On the other hand, for diagnostic or other purposes, it may be useful to observe
this data stream. For example, a mirror could be used to intentionally couple the output LED
to the input PIN. For these cases, RCVEN could be set to enable the receiver.
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available,
even in RSA-232 mode. This can be useful when checking code for valid threshold
interrupts, as the timeout interrupt will not override the threshold interrupt.
DLY3–DLY0 sets a delay after the last stop bit of the last data byte being set before the
DTRx is set low, to allow for long cable runs. The delay is in number of bit times and is
7:5 enabled by 485EN. The delay will start only when both the xmt serial shift register (TSR) is
empty and the xmt fifo (THR) is empty, and if started, will be cleared by any data being
written to the THR.
36 Copyright ©2007–2011, Texas Instruments Incorporated
WR THR
TX
DTRx
1 Baud Time Controlled by DLY[3:0]
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
Table 24. LOOP and RCVEN Functionality
LOOP MODE RCVEN AFR MODE DESCRIPTION
Receive threshold, timeout, and error detection interrupts available.
AFR = 10 RS-232 Data stored in receive FIFO.
Receive threshold, timeout, and error detection interrupts available.
RCVEN = 1 AFR = 14 RS-485 Data stored in receive FIFO.
LOOP mode off, Receive threshold, timeout, and error detection interrupts available.
AFR = 12 IrDA
MCR4 = 0, Data stored in receive FIFO.
RX, TX active Receive threshold and error detection interrupts available.
AFR = 00 RS-232 Data stored in receive FIFO.
RCVEN = 0 AFR = 04 RS-485 No data stored in receive FIFO, hence no interrupts available.
AFR = 02 IrDA No data stored in receive FIFO, hence no interrupts available.
Receive threshold, timeout, and error detection interrupts available.
AFR = 10 RS-232 Data stored in receive FIFO.
Receive threshold, timeout, and error detection interrupts available.
RCVEN = 1 AFR = 14 RS-485 Data stored in receive FIFO.
Receive threshold, timeout, and error detection interrupts available.
AFR = 12 IrDA
LOOP mode on, Data stored in receive FIFO.
MCR4 = 1, Receive threshold and error detection interrupts available.
RX, TX inactive AFR = 00 RS-232 Data stored in receive FIFO.
Receive threshold and error detection interrupts available.
RCVEN = 0 AFR = 04 RS-485 Data stored in receive FIFO.
Receive threshold and error detection interrupts available.
AFR = 02 IrDA Data stored in receive FIFO.
RS-485 Mode
The RS-485 mode is intended to simplify the interface between the UART channel and an RS-485 driver or
transceiver. When enabled by setting 485EN, the DTRx output goes high one bit time before the first start bit of
the first data byte being sent, and remains high as long as there is pending data in the transmitter shift register
(TSR) or transmitter holding register (THR, xmt fifo). Once both are empty (after the last stop bit of the last data
byte), the DTRx output stays high for a programmable delay of 0 to 15 bit times, as set by DLY[3:0]. This helps
preserve data integrity over long signal lines. This is illustrated in the following.
Often RS-485 packets are relatively short and the entire packet can fit within the 64 byte xmt fifo. In this case, it
goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to
reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be
reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block) which causes
the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the
threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is
being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being
loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going
empty.
A. Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform
varies with baud rate but is typically in the microsecond range.
Figure 22. DTRx and Transmit Data Relationship
Copyright ©2007–2011, Texas Instruments Incorporated 37
Loopback
RS-485 XCVR
UART
TSR
RSR
48SEN
RCVEN
RX
TX
DTR
RS-485 BUS
DEN
REN
Loopback
Receive Shift Register
IREN
Int_Tx Tx
Int_Rx Rx
IrDA Converter
Baud Clock
Reset
To Optoelectronic
LED
From
Optoelectronic
Pin Diode
RCVEN
Transmit Shift Register
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
Figure 23. RS-485 Application Example 1
Figure 24. RS-485 Application Example 2
IrDA Overview
Figure 25. IrDA Mode
The infrared data association (IrDA) defines several protocols for sending and receiving serial infrared data,
including rates of 115.2 kbps, 0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified
first and the others must maintain downward compatibility with it. At the 115.2 kbps rate, the protocol
implemented in the hardware is fairly simple. It primarily defines a serial infrared data word to be surrounded by a
start bit equal to 0 and a stop bit equal to 1. Individual bits are encoded or decoded the same whether they are
start, data, or stop bits. The IrDA engine in the ’754C evaluate only single bits and only follow the 115.2 kbps
38 Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
www.ti.com
SLLS644G –DECEMBER 2007–REVISED MAY 2011
protocol. The 115.2 kbps rate is a maximum rate. When both ends of the transfer are set up to a lower but
matching speed, the protocol still works. The clock used to code or sample the data is 16 times the baud rate, or
1.843 MHz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code
a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6 μs
wide and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3
clock cycles. The transmitter output, Tx, is intended to drive a LED circuit to generate an infrared pulse. The LED
circuits work on positive pulses. A terminal circuit is expected to create the receiver input, Rx. Most, but not all,
PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally
high. The '754C can decode either negative or positive pulses on Rx.
IrDA Encoder Function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (Int_Tx) is high, the output (Tx) is always low, and the counter used to form a pulse on Tx is continuously
cleared. After Int_Tx resets to 0, Tx rises on the falling edge of the seventh 16XCLK. On the falling edge of the
tenth 16XCLK pulse, Tx falls, creating a 3-clock-wide pulse. While Int_Tx stays low, a pulse is transmitted during
the seventh to tenth clocks of each 16-clock bit cycle.
Figure 26. IrDA-SIR Encoding Scheme –Detailed Figure 27. Encoding Scheme –Macro View
Timing Diagram
After reset, Int_Rx is high and the 4-bit counter is cleared. When a falling edge is detected on Rx, Int_Rx falls on
the next rising edge of 16XCLK with sufficient setup time. Int_Rx stays low for 16 cycles (16XCLK) and then
returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on Rx,
Int_Rx remains high.
Figure 28. IrDA-SIR Decoding Scheme –Detailed Figure 29. IrDA-SIR Decoding Scheme –Macro
Timing Diagram View
It is possible for jitter or slight frequency differences to cause the next falling edge on Rx to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_Rx between consecutive zeroes. It is important
for the UART to strobe Int_Rx in the middle of the bit time to avoid latching this 1-clock-wide pulse. The
TL16C550C UART already strobes incoming serial data at the proper time. Otherwise, note that data is required
to be framed by a leading zero and a trailing one. The falling edge of that first zero on Int_Rx synchronizes the
read strobe. The strobe occurs on the eighth 16XCLK pulse after the Int_Rx falling edge and once every 16
cycles thereafter until the stop bit occurs.
Copyright ©2007–2011, Texas Instruments Incorporated 39
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
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Figure 30. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones
Figure 31. Recommended Strobing For Decoded Data
The '754C can decode positive pulses on Rx. The timing is different, but the variation is invisible to the UART.
The decoder, which works from the falling edge, now recognizes a zero on the trailing edge of the pulse rather
than on the leading edge. As long as the pulse width is fairly constant, as defined by the specification, the trailing
edges should also be 16 clock cycles apart and data can readily be decoded. The zero appears on Int_Rx after
the pulse rather than at the start of it.
Figure 32. Positive Rx Pulse Decode –Detailed View
40 Copyright ©2007–2011, Texas Instruments Incorporated
TL16CP754C, TL16C754C
SLLS644G –DECEMBER 2007–REVISED MAY 2011
www.ti.com
TL16CP754C Programmer's Guide
The base set of registers that are used during high speed data transfer have a straightforward access method.
The extended function registers require special access bits to be decoded along with the address lines. The
following guide will help with programming these registers. Note that the descriptions below are for individual
register access. Some streamlining through interleaving can be obtained when programming all the registers.
Set baud rate to VALUE1,VALUE2 Read LCR (03), save in temp
Set LCR (03) to 80
Set DLL (00) to VALUE1
Set DLM (01) to VALUE2
Set LCR (03) to temp
Set Xoff1,Xon1 to VALUE1,VALUE2 Read LCR (03), save in temp
Set LCR (03) to BF
Set Xoff1 (06) to VALUE1
Set Xon1 (04) to VALUE2
Set LCR (03) to temp
Set Xoff2,Xon2 to VALUE1,VALUE2 Read LCR (03), save in temp
Set LCR (03) to BF
Set Xoff2 (07) to VALUE1
Set Xon2 (05) to VALUE2
Set LCR (03) to temp
Set software flow control mode to VALUE Read LCR (03), save in temp
Set LCR (03) to BF
Set EFR (02) to VALUE
Set LCR (03) to temp
Set flow control threshold to VALUE Read LCR (03), save in temp1
Set LCR (03) to BF
Read EFR (02), save in temp2
Set EFR (02) to 10 + temp2
Set LCR (03) to 00
Read MCR (04), save in temp3
Set MCR (04) to 40 + temp3
Set TCR (06) to VALUE
Set LCR (03) to BF
Set EFR (02) to temp2
Set LCR (03) to temp1
Set MCR (04) to temp3
Set xmt and rcv FIFO thresholds to VALUE Read LCR (03), save in temp1
Set LCR (03) to BF
Read EFR (02), save in temp2
Set EFR (02) to 10 + temp2
Set LCR (03) to 00
Read MCR (04), save in temp3
Set MCR (04) to 40 + temp3
Set TLR (07) to VALUE
Set LCR (03) to BF
Set EFR (02) to temp2
Set LCR (03) to temp1
Set MCR (04) to temp3
Read FIFORdy register Read MCR (04), save in temp1
Set temp2 = temp1 * EF
Set MCR (04), save in temp2
Read FRR (07), save in temp2
Pass temp2 back to host
Set MCR (04) to temp1
42 Copyright ©2007–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TL16CP754CIPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CIPMG4 ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CIPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CIPMRG4 ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CPMG4 ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16CP754CPMRG4 ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL16CP754CIPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
TL16CP754CPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL16CP754CIPMR LQFP PM 64 1000 336.6 336.6 41.3
TL16CP754CPMR LQFP PM 64 1000 336.6 336.6 41.3
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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