January 2009 Rev 2 1/19
19
LD39150xx
Ultra low drop BiCMOS voltage regulator
Features
■1.5 A guaranteed output current
■Ultra low dropout voltage (200 mV typ. @ 1.5 A
load, 40 mV typ. @ 300 mA load)
■Very low quiescent current (1 mA typ. @ 1.5 A
load, 1 µA max @ 25 °C in off mode)
■Logic-controlled electronic shutdown
■Current and thermal internal limit
■± 1.5 % output voltage tolerance @ 25 °C
■Fixed and ADJ output voltages: 1.22 V, 1.8 V,
2.5 V, 3.3 V, ADJ. (see Table 1)
■Temperature range: -40 to 125 °C
■Fast dynamic response to line and load
changes
■Stable with ceramic capacitor (see Section 7.1,
Section 7.2 and Section 7.3)
■Available in PPAK, DPAK and DFN6 (3x3 mm)
Typical application
■Microprocessor power supply
■DSPs power supply
■Post regulators for switching suppliers
■High efficiency linear regulator
Description
The LD39150xx is a fast ultra low drop linear
regulator which operates from 2.5 V to 6 V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
DFN6 (3x3 mm)
PPAK DPAK
Table 1. Device summary
Part numbers
Order codes
Output voltages
DPAK (T&R) PPAK (T&R) DFN (1)
LD39150XX12 LD39150DT12-R LD39150PU12R 1.22 V
LD39150XX18 LD39150DT18-R LD39150PT18-R LD39150PU18R 1.8 V
LD39150XX25 LD39150DT25-R LD39150PT25-R LD39150PU25R 2.5 V
LD39150XX33 LD39150DT33-R LD39150PT33-R LD39150PU33R 3.3 V
LD39150XX LD39150PT-R LD39150PU-R ADJ from 1.22 to 5.0 V
1. Available on request.
www.st.com
Contents LD39150xx
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Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LD39150xx Diagram
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1 Diagram
(*) Not present on ADJ versions.
Figure 1. Block diagram
Pin configuration LD39150xx
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2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)
DFN6 (3x3 mm) DPAK
PPAK
Table 2. Pin description
Pin n°
SYMBOL NOTE
DFN PPAK DPAK
55 VSENSE/N.C. For fixed versions: to be connected with LDO output voltage pins for DFN
package and not connected on PPAK
ADJ For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V
321 V
I
LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a
distance of not more than 0.5’’ from input pin.
443 V
O
LDO output voltage pins, with minimum CO = 2.2 µF needed for stability
(also refer to CO vs ESR stability chart)
21 V
INH
Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤
0.3 V (Do not leave floating, not internally pulled down/up)
1 3 2 GND Common ground
6 N.C. Not connected
LD39150xx Typical application circuits
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3 Typical application circuits
(CI and CO capacitors must be placed as close as possible to the IC pins)
Note: Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3 V.
Note: Set R2 as close as possible to 4.7 k
Ω
Figure 3. LD39150xx fixed version with inhibit
Figure 4. LD39150xx adjustable version
VO = VREF (1 + R1/R2)
Typical application circuits LD39150xx
6/19
Figure 5. LD39150xx DPAK
Figure 6. Timing diagram
LD39150xx Maximum ratings
7/19
4 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All values are referred to GND.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VIDC input voltage -0.3 to 6.5 V
VINH INHIBIT input voltage -0.3 to VI +0.3 (6.5 V max) V
VODC output voltage -0.3 to VI +0.3 (6.5 V max) V
VADJ ADJ pin voltage -0.3 to VI +0.3 (6.5 V max) V
IOOutput current Internally limited mA
PDPower dissipation Internally limited mW
TSTG Storage temperature range -50 to 150 °C
TOP Operating junction temperature range -40 to 125 °C
Table 4. Thermal data
Symbol Parameter PPAK DPAK DFN (1) Unit
RthJA Thermal resistance junction-ambient 100 100 40 °C/W
RthJC Thermal resistance junction-case 8 8 10 °C/W
1. With PCB ground plane heatsink.
Electrical characteristics LD39150xx
8/19
5 Electrical characteristics
Table 5. Electrical characteristics
(TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = 2 V, unless otherwise
specified)
Symbol Parameter Parameter Min. Typ. Max. Unit
VIOperating input voltage 2.5 6 V
VOOutput voltage tolerance
VI = VO+1V, ILOAD = 10mA to 1.5A -1.5 1.5
% of
VO(NOM)
VI = VO+1V to 6V,
ILOAD = 10mA to 1.5A
TJ = -40 to 125°C
-3 3
VREF Reference voltage 1.22 V
ΔVO
Output voltage LINE
regulation
VI = VO+1V to 6V 0.04 %
VI = VO+1V to 6V, TJ = -40 to 125°C 0.1 0.2 %
ΔVO/ΔILOAD
Output voltage LOAD
regulation
ILOAD = 10mA to 1.5A 0.06
%/A
ILOAD = 10mA to 1.5A,
TJ = -40 to 125°C 0.2 0.4
VDROP Dropout voltage (VI - VO)ILOAD = 300mA, TJ=-40 to 125°C 40 80 mV
ILOAD = 1.5A, TJ = -40 to 125°C 200 400
IQ
Quiescent current:
ON MODE
ILOAD = 10mA to 1.5A, VINH = 2V
TJ = -40 to 125°C 12.5mA
Quiescent current:
OFF MODE
VINH = 0.3V 1 µA
VINH = 0.3V, TJ = -40 to 125°C 5
Short circuit protection
ISC Short circuit protection RL = 0 3 A
Inhibit input
VINH
Inhibit threshold LOW VI = 2.5 to 6V OFF
TJ = -40 to 125°C
0.3 V
Inhibit threshold HIGH 2
TD-OFF Current limit ILOAD = 1.5A, VO = 3.3V 15 µs
TD-ON Current limit ILOAD = 1.5A, VO = 3.3V 15
IINH Inhibit input current (1)
1. Guaranteed by design
VI = 6V, VINH = 0 to 6V ±0.1 ±1µA
AC parameters
SVR Supply voltage rejection
VI = 4.5 ± 1V,
VO = 3.3V,
ILOAD = 10mA,
f = 120Hz 65
dB
f = 1kHz 55
eNOutput noise voltage BW = 10Hz to 100kHz,
CO = 2.2µF, VO = 2.5V 100 µVRMS
TSHDN
Thermal shutdown OFF 170 °C
Hysteresis 10
LD39150xx Typical performance characteristics
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6 Typical performance characteristics
(TJ = 25 °C, VI = VO + 1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = VI, unless otherwise
specified)
Figure 7. Output voltage vs temperature Figure 8. Dropout voltage vs temperature
Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs supply
voltage
Figure 11. Quiescent current vs temperature Figure 12. Quiescent current vs temperature
Typical performance characteristics LD39150xx
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Figure 13. Short circuit current vs temperature Figure 14. Output voltage vs input voltage
Figure 15. Stability region vs CO & ESR (at 100
kHz)
Figure 16. Stability region vs CO & low ESR (at
100 kHz)
Figure 17. Load transient Figure 18. Line transient
VI = 3.5V, IO = 10mA to 1.5A, CI = 1µF, CO = 2.2µF
VI = 3.5V to 5.5V, ILOAD = 10mA, CO = 2.2µF
LD39150xx Application notes
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7 Application notes
7.1 External capacitors
The LD39150xx requires external capacitors for regulator stability. These capacitors must be
selected to meet the requirements of minimum capacitance and equivalent series resistance
(see Figure 15 and Figure 16). The input/output capacitors must be located less than 1cm
from the relative pins and connected directly to the input/output ground pins using traces
which have no other currents flowing through them. Any good quality of Ceramic or
Electrolytic capacitors can be used.
7.2 Input capacitor
An input capacitor whose minimum value is 1 µF is required with the LD39150xx (amount of
capacitance can be increased without limit). This capacitor must be located a distance of not
more than 1cm from the input pin of the device and returned to a clean analog ground. Any
good quality ceramic, tantalum or film capacitors can be used for this capacitor.
7.3 Output capacitor
It is possible to use ceramic or tantalum capacitors but the output capacitor must meet the
requirement for minimum amount of capacitance and ESR (equivalent series resistance)
value. A minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the
regulator. Anyway, other CO values can be used according to the (Figure 15 and Figure 16)
showing the allowable ESR range as a function of the output capacitance. This curve
represents the stability region over the full temperature and IO range.
7.4 Thermal note
The output capacitor must maintain its ESR in the stable region over the full operating
temperature range to assure stability. Also, capacitors tolerance and variation with
temperature must be kept in consideration in order to assure the minimum amount of
capacitance at all times.
7.5 Inhibit input operation
The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically
reducing the current consumption down to less than 1 µA. When the inhibit feature is not
used, this pin must be tied to VI to keep the regulator output ON at all times. To assure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section (VIH VIL).
The inhibit pin must not be left floating because it is not internally pulled down/up.
Package mechanical data LD39150xx
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8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
LD39150xx Package mechanical data
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Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A 2.2 2.4 0.086 0.094
A1 0.91.1 0.035 0.043
A2 0.030.230.001 0.009
B 0.4 0.6 0.015 0.023
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.480.6 0.0190.023
D 6 6.2 0.236 0.244
D1 5.1 0.201
E 6.4 6.6 0.252 0.260
E1 4.7 0.185
e 1.27 0.050
G4.95.25 0.193 0.206
G1 2.38 2.7 0.093 0.106
H9.35 10.1 0.3680.397
L2 0.81 0.0310.039
L4 0.6 1 0.0230.039
L5 1 0.039
L6 2.80.110
PPAK mechanical data
0078180-E
Package mechanical data LD39150xx
14/19
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A 2.2 2.4 0.086 0.094
A1 0.91.1 0.035 0.043
A2 0.030.230.001 0.009
B 0.64 0.90.025 0.035
b4 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.480.6 0.0190.023
D 6 6.2 0.236 0.244
D1 5.1 0.200
E 6.4 6.6 0.252 0.260
E1 4.7 0.185
e2.280.090
e1 4.4 4.6 0.1730.181
H9.35 10.1 0.3680.397
L 1 0.039
(L1) 2.80.110
L2 0.80.031
L4 0.6 1 0.0230.039
R 0.2 0.008
V2 0° 8°0° 8°
DPAK mechanical data
0068772-F
LD39150xx Package mechanical data
15/19
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A0.800.90 1.00 0.031 0.035 0.039
A1 0 0.02 0.05 0 0.001 0.002
A30.20 0.008
b0.230.300.38 0.0090.012 0.015
D2.903.00 3.10 0.114 0.1180.122
D2 2.232.38 2.480.088 0.094 0.098
E2.903.00 3.10 0.114 0.1180.122
E2 1.50 1.65 1.75 0.0590.065 0.069
e0.950.037
L0.30 0.40 0.50 0.012 0.016 0.020
DFN6 (3x3 mm) mechanical data
7946637A
Package mechanical data LD39150xx
16/19
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A330 12.992
C12.813.0 13.2 0.504 0.512 0.519
D 20.2 0.795
N60 2.362
T22.40.882
Ao 6.806.90 7.00 0.2680.272 0.2.76
Bo 10.40 10.50 10.60 0.4090.4130.417
Ko 2.55 2.65 2.75 0.100 0.104 0.105
Po 3.94.0 4.1 0.1530.157 0.161
P7.98.0 8.1 0.311 0.315 0.319
Tape & reel DPAK-PPAK mechanical data
LD39150xx Package mechanical data
17/19
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A180 7.087
C 12.813.2 0.504 0.519
D 20.2 0.795
N60 2.362
T 14.4 0.567
Ao 3.30.130
Bo 3.30.130
Ko 1.1 0.043
Po 4 0.157
P80.315
Tape & reel QFNxx/DFNxx (3x3) mechanical data
Revision history LD39150xx
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9 Revision history
Table 6. Document revision history
Date Revision Changes
26-Jan-2007 1 Initial release.
12-Jan-2009 2 Removed: package DFN8 (4x4 mm) and added package DFN6 (3x3 mm).
LD39150xx
19/19
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