ESMT PSRAM M24L28256SA 2-Mbit (256K x 8) Pseudo Static RAM Features *Advanced low-power architecture *High speed: 55 ns, 70 ns *Wide voltage range: 2.7V to 3.6V *Typical active current: 1 mA @ f = 1 MHz *Low standby power *Automatic power-down when deselected Functional Description The M24L28256SA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable( CE ) and active LOW Output Enable ( OE ).This device has an automatic power-down feature that reduces power consumption dramatically when deselected. Writing to the device is accomplished by asserting Chip Enable ( CE ) and Write Enable ( WE ) inputs LOW .Data on the eight I/O pins(I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by asserting the Chip Enable One ( CE ) and Output Enable ( OE ) inputs LOW while forcing Write Enable ( WE ) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected ( CE HIGH ), the outputs are disabled ( OE HIGH), or during write operation ( CE LOW and WE LOW). See the Truth Table for a complete description of read and write modes. Logic Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 1/12 ESMT M24L28256SA Pin Configuration[2, 3] VFBGA Top View Product Portfolio Power Dissipation VCC Range (V) Product M24L28256SA Speed(ns) Min. Typ. Max. 2.7 3.0 3.6 55 70 Operating ICC(mA) f = 1MHz Typ.[3] Max. 1 5 Standby ISB2(A) f = fMAX Typ.[3] Max. 14 22 8 15 Typ. [3] Max. 9 40 Notes: 2.NC "no connect"--not connected internally to the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 2/12 ESMT M24L28256SA Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ..............................................-55C to +125C Supply Voltage to Ground Potential . ............... ............ ...........-0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[4, 5, 6] .................................-0.4V to 3.7V DC Input Voltage[4, 5, 6].................... .........-0.4V to 3.7V Output Current into Outputs (LOW) ...............................20 mA Static Discharge Voltage ........................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current ....................................................> 200 mA Operating Range Range Ambient Temperature (TA) VCC Extended -25C to +85C 2.7V to 3.6V Industrial -40C to +85C 2.7V to 3.6V Electrical Characteristics (Over the Operating Range) -55 Parameter Description Test Conditions Min. VCC VOH VOL VIH VIL IIX IOZ Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current 2.7 VCC0.4 IOH = -0.1 mA -70 Typ .[3] 3.0 IOL = 0.1 mA Max. Min. 3.6 2.7 VCC0.4 Typ. [3] 3.0 GND VOUT Disable f = fMAX = 1/tRC VCC , Output V 0.4 V 0.8* VCC -0.4 VCC+ 0.4 0.4 0.8* VCC -0.4 VCC +0.4 0.4 -1 +1 -1 +1 A -1 +1 -1 +1 A V V 14 22 8 15 1 5 1 5 CE VCC-0.2V, VIN VCC - 0.2V, VIN 0.2V, f = fMAX (Address and Data Only), f=0 40 250 40 250 A CE VCC-0.2V, VIN VCC - 0.2V, VIN 0.2V, f = 0, VCC = 3.6V 9 40 9 40 A ICC VCC Operating Supply Current f = 1 MHz ISB1 Automatic CE Power-Down Current --CMOS Inputs ISB2 Automatic CE Power-Down Current --CMOS Inputs VCC = 3.6V IOUT = 0mA CMOS levels 3.6 V 0.4 GND VIN VCC Unit Max. mA Capacitance[7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions Max. Unit 8 8 pF pF TA = 25C, f = 1 MHz VCC = VCC(typ) Thermal Resistance[7] Parameter Description Test Conditions BGA Unit JA Thermal Resistance(Junction to Ambient) 55 C/W JC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. 17 C/W Notes: 4.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 5.VIL(MIN) = -0.5V for pulse durations less than 20 ns. 6.Overshoot and undershoot specifications are characterized and are not 100% tested. 7.Tested initially and after design or process changes that may affect these parameters. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 3/12 ESMT M24L28256SA AC Test Loads and Waveforms Parameters R1 R2 RTH VTH 3.0V (VCC) 22000 22000 11000 1.50 Unit V Switching Characteristics Over the Operating Range [8] Parameter Description -55 Min. -70 Max. Min. Max. Unit Read Cycle tRC tAA tOHA tACE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW 55 70 ns ns ns ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[9, 10] tHZOE OE HIGH to High Z[9, 10] tLZCE CE LOW tHZCE CE HIGH Address Skew tSK[12] Write Cycle [11] tWC tSCE tAW tHA tSA tPWE Write Cycle Time 55[12] 70 55 5 70 10 5 ns 5 25 2 25 ns 5 25 0 ns 25 10 ns ns WE Pulse Width 55 45 45 0 0 40 tSD Data Set-Up to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[9, 10] tLZWE WE HIGH to Low-Z[9, 10] CE LOW Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start 70 55 55 0 0 55 ns ns ns ns ns ns 25 5 25 5 ns ns Notes: 8. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 9. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 10. High-Z and Low-Z parameters are characterized and are not 100% tested. 11. The internal write time of the memory is defined by the overlap of WE , CE = VIL, . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 12. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 4/12 ESMT M24L28256SA Switching Waveforms Read Cycle 1 (Address Transition Controlled)[12, 13, 14] Read Cycle 2 ( OE Controlled)[12, 14] Notes: 13. Device is continuously selected. OE and CE = VIL. 14. WE is HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 5/12 ESMT M24L28256SA Switching Waveforms (continued) Write Cycle 1 ( WE Controlled)[10,11, 15, 16, 17] Write Cycle 2 ( CE Controlled) [9, 10, 15, 16, 17] Notes: 15.Data I/O is high impedance if OE VIH. 16. If Chip Enables go INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state. 17.During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 6/12 ESMT M24L28256SA Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[16, 17] Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 7/12 ESMT M24L28256SA Avoid Timing ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15s at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15s shown as in Avoidable timing 1 or toggle CE to high (tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing 15 s CE WE tRC Address Avoidable Timing 1 15 s CE WE tRC Address Avoidable Timing 2 15 s CE tRC WE tRC Address Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 8/12 ESMT M24L28256SA Truth Table[18] CE H X OE X X WE X X L L L L High Z High Z I/O0-I/O7 Power-Down Power-Down Mode Power Standby (ISB) Standby (ISB) H Data Out Read Active (ICC) X L Data In Write Active (ICC) H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 55 70 55 70 Ordering Code M24L28256SA-55BEG M24L28256SA-70BEG M24L28256SA-55BIG M24L28256SA-70BIG Package Type 36-Lead VFBGA (6 x 8 x 1 mm) (Pb-free) 36-Lead VFBGA (6 x 8 x 1 mm) (Pb-free) 36-Lead VFBGA (6 x 8 x 1 mm) (Pb-free) 36-Lead VFBGA (6 x 8 x 1 mm) (Pb-free) Operating Range Extended Extended Industrial Industrial Note: 18.H = Logic HIGH, L = Logic LOW, X = Don't Care. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 9/12 ESMT M24L28256SA Package Diagrams 36-Lead VFBGA (6 x 8 x 1 mm) BV36A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 10/12 ESMT M24L28256SA Revision History Revision Date 1.0 2007.07.19 1.1 2008.07.04 Elite Semiconductor Memory Technology Inc. Description Original 1. Move Revision History to the last 2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V 3.Correct type error for Extended Temperature (-40~85C => -25~85C) 4. Add Industrial grade 5. Add Avoid timing Publication Date : Jul. 2008 Revision : 1.1 11/12 ESMT M24L28256SA Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 12/12