HUF75307T3ST Data Sheet December 2001 2.6A, 55V, 0.090 Ohm, N-Channel UltraFET Power MOSFET Features * 2.6A, 55V This N-Channel power MOSFET is manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. * Ultra Low On-Resistance, rDS(ON) = 0.090 * Diode Exhibits Both High Speed and Soft Recovery * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Formerly developmental type TA75307. D Ordering Information PART NUMBER HUF75307T3ST PACKAGE SOT-223 BRAND G 5307 S NOTE: HUF75307T3ST is available only in tape and reel. Packaging SOT-223 DRAIN (FLANGE) GATE DRAIN SOURCE Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2001 Fairchild Semiconductor Corporation HUF75307T3ST Rev. B HUF75307T3ST Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg UNITS V V V 55 55 20V 2.6 Figure 5 Figures 6, 14, 15 1.1 9.09 -55 to 150 A W mW/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V (Figure 11) 55 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V VDS = 50V, VGS = 0V - - 1 A Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time VDS = 45V, VGS = 0V, TA = 150oC - - 250 A VGS = 20V - - 100 nA ID = 2.6A, V GS = 10V) (Figure 9) - 0.070 0.090 VDD = 30V, ID 2.6A, RL = 11.5, VGS = 10V, RGS = 25 - - 55 ns - 5 - ns - 30 - ns td(OFF) - 35 - ns tf - 25 - ns tOFF - - 90 ns Fall Time Turn-Off Time Total Gate Charge TEST CONDITIONS Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V VDD = 30V, ID 2.6A, RL = 11.5 Ig(REF) = 1.0mA (Figure 13) - 14 17 nC - 8.3 10 nC - 0.6 0.8 nC Gate to Source Gate Charge Qgs - 1.00 - nC Gate to Drain "Miller" Charge Qgd - 4.00 - nC Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Ambient RJA VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 250 - pF - 115 - pF - 30 - pF Pad Area = 0.171 in2 (see note 2) - - 110 oC/W Pad Area = 0.068 in2 - - 128 oC/W Pad Area = 0.026 in2 - - 147 oC/W Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL MIN TYP MAX UNITS ISD = 2.6A - - 1.25 V trr ISD = 2.6A, dISD/dt = 100A/s - - 40 ns QRR ISD = 2.6A, dISD/dt = 100A/s - - 50 nC VSD TEST CONDITIONS NOTE: 2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000s. (c)2001 Fairchild Semiconductor Corporation HUF75307T3ST Rev. B HUF75307T3ST Typical Performance Curves 1.2 3.0 POWER DISSIPATION MULTIPLIER RJA = 110oC/W 1.0 ID, DRAIN CURRENT (A) 2.5 0.8 0.6 0.4 0.2 0 0 50 100 2.0 1.5 1.0 0.5 0 25 150 50 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE ZJA, NORMALIZED THERMAL IMPEDANCE 10 1 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) TA, AMBIENT TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 RJA = 110oC/W 0.1 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 30 TJ = MAX RATED TA = 25oC RJA = 110oC/W IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) 100 10 100s 1ms 1 10ms 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.01 1 VDSS(MAX) = 55V 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 200 TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I 10 = I25 150 - TA 125 RJA = 110oC/W 1 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) 102 103 FIGURE 5. PEAK CURRENT CAPABILITY HUF75307T3ST Rev. B HUF75307T3ST Typical Performance Curves 25 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 20 (Continued) STARTING TJ = 25oC STARTING TJ = 150oC 1 0.01 20 VGS = 7V VGS = 6V 15 10 10 VGS = 5V 5 0 0.1 1 tAV, TIME IN AVALANCHE (ms) VGS = 20V VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 20 -55oC 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID, DRAIN CURRENT (A) 25 150oC 15 10 5 0 0 1.5 FIGURE 7. SATURATION CHARACTERISTICS 3.0 4.5 6.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 2.6A 2.0 1.5 1.0 0.5 -80 7.5 -40 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS 1.2 VGS = VDS, ID = 250A 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation 160 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.2 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) ID = 250A 1.1 1.0 0.9 0.8 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE HUF75307T3ST Rev. B HUF75307T3ST Typical Performance Curves (Continued) 500 400 C, CAPACITANCE (pF) VGS , GATE TO SOURCE VOLTAGE (V) 10 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 300 CISS 200 COSS 100 CRSS 0 8 10 20 30 40 50 VDS , DRAIN TO SOURCE VOLTAGE (V) VDD = 30V 6 4 2 0 0 WAVEFORMS IN DESCENDING ORDER: ID = 2.6A ID = 1.5A ID = 0.5A 60 0 2 4 8 6 Qg, GATE CHARGE (nC) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT Ig(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 17. GATE CHARGE WAVEFORM HUF75307T3ST Rev. B HUF75307T3ST Test Circuits and Waveforms (Continued) VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJ(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PD(MAX), in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJ(MAX) is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RJA = 75.9 -19.3 ln(AREA) (EQ. 1) In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PD(MAX) is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds (c)2001 Fairchild Semiconductor Corporation 200 RJA (oC/W) (T -T ) A J ( MAX ) P D ( MAX ) = -------------------------------------------R JA of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. 150 147oC/W - 0.026in2 128oC/W - 0.068in2 110oC/W - 0.171in2 100 50 0.01 0.1 1.0 AREA, TOP COPPER AREA (in 2) FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA Displayed on the curve are the three RJA values listed in the Electrical Specifications table. The three points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PD(MAX). Thermal resistances corresponding to other component side copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 75.9 - 19.3 x ln ( Area ) (EQ. 2) HUF75307T3ST Rev. B HUF75307T3ST PSPICE Electrical Model .SUBCKT HUF75307T3ST 2 1 3 ; rev 7/25/97 CA 12 8 3.5e-10 CB 15 14 3.7e-10 CIN 6 8 2.26e-10 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 57.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.4e-9 LSOURCE 3 7 3.1e-10 K1 LGATE LSOURCE 0.131 + 50 - EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.0e-3 RGATE 9 20 1.9 RLDRAIN 2 5 10 RLGATE 1 9 14 RLSOURCE 3 7 3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.6e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S2A 14 13 13 8 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))} .MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46 + XTI = 5.5) .MODEL DBREAKMOD D (RS = 0. 5IKF = 0.1 N = 1 TRS1 = 3e- 3TRS2 = -5e-5) .MODEL DPLCAPMOD D (CJO = 5.6e-1 0IS = 1e-3 0N = 10 M = 0.92) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9) .MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.08e- 3TC2 = 5e-7) .MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4) .MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4) .MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9) .MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6) .MODEL RVTEMPMOD RES (TC1 = -2.9e- 3TC2 = 2.2e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.1 VOFF= -4) VON = -4 VOFF= -7.1) VON = 0.01 VOFF= 1.9) VON = 1.9 VOFF= 0.01) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2001 Fairchild Semiconductor Corporation HUF75307T3ST Rev. B HUF75307T3ST SPICE Thermal Model 7 JUNCTION REV 15 Nov 97 HUF75307T3ST CTHERM1 7 6 7.5e-5 CTHERM2 6 5 3.5e-4 CTHERM3 5 4 1.2e-3 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 6.9e-2 CTHERM6 2 1 4.5e-1 RTHERM1 RTHERM1 7 6 7.5e-2 RTHERM2 6 5 2.0e-1 RTHERM3 5 4 1.2 RTHERM4 4 3 3.3 RTHERM5 3 2 28 RTHERM6 2 1 90 RTHERM2 CTHERM1 6 CTHERM2 5 CTHERM3 RTHERM3 4 CTHERM4 RTHERM4 3 CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 1 (c)2001 Fairchild Semiconductor Corporation CASE HUF75307T3ST Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4