FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
DS05–20814–2E
MBM29F017 - 90/-12
16 M (2 M × 8) BIT
CMOS
Embedded Erase and Embedded Program are trademarks of Advanced Micro Devices, Inc.
■DISTINCTIVE CHARACTERISTICS
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
• 48-pin TSOP
• Minimum 100,000 write/erase cycles
• High performance
90 ns maximum access time
• Sector erase architecture
Uniform sectors of 64K bytes each
Any combination of sectors can be erased. Also supports full chip erase.
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/BUSY output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low power consumption
40 mA maximum active read current
60 mA maximum program/erase current
• Enhanced power management for standby mode
<1 µA typical standby current
Standard access time from standby mode
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
• Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector
group consists of 4 adjacent sectors of 64K bytes each)
MBM29F017 -90/-12
2
■PACKAGE
FPT-48P-M19 FPT-48P-M20
Marking
Side
Marking Side
MBM29F017 -90/-12
3
■GENERAL DESCRIPTION
The MBM29F017 is a 16M-bit, 5.0 V-Only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes
of data is divided into 32 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ0
to DQ7. The MBM29F016 is offered in a 48-pin TSOP package. This device is designed to be programmed in-
system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F017 offers access times between 90 ns and 120 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE ),
write enable (
WE
), and output enable (
OE
) controls.
The MBM29F017 is command set compatible with JEDEC standard single-supply Flash standard. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and erase operations. Reading data out of the
device is similar to reading from 12.0 V Flash or EPROM devices.
The MBM29F017 is programmed by executing the program command sequence. This will invoke the
Embedded ProgramTM Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margin.
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within
one second (if already completely preprogrammed). The MBM29F017 is erased when shipped from the
factory.
The MBM29F017 device also features hardware sector group protection. This feature will disable both
program and erase operations in any combination of eight sector groups of memory.
A sector group consists of
four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and
28-31.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
The device features single 5.0 V power supply operation for both read and program functions. Internally
generated and regulated voltages are provided for the program and erase operations. A low VCC detector
automatically inhibits write operations during power transitions. The end of program or erase is detected by
Data
Polling of DQ7, or by the Toggle Bit I feature on DQ6 or RY/
BY
output pin. Once the end of a program or
erase cycle has been completed, the device automatically resets to the read mode.
The MBM29F017 also has a hardware
RESET
pin. When this pin is driven low, execution of any Embedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The
RESET
pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F017 memory electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the
EPROM programming mechanism of hot electron injection.
MBM29F017 -90/-12
4
■FLEXIBLE SECTOR-ERASE ARCHI-
TECTURE
• Thirty two 64K byte sectors
• 8 sector groups each of which consists of 4
adjacent sectors in the following pattern;
sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23,
24-27, and 28-31
• Individual-sector or multiple-sector erase
capability
• Sector group protection is user-definable
1FFFFFH
1EFFFFH
1DFFFFH
1CFFFFH
1BFFFFH
1AFFFFH
19FFFFH
18FFFFH
17FFFFH
16FFFFH
15FFFFH
14FFFFH
13FFFFH
12FFFFH
11FFFFH
10FFFFH
0FFFFFH
0EFFFFH
0DFFFFH
0CFFFFH
0BFFFFH
0AFFFFH
09FFFFH
08FFFFH
07FFFFH
06FFFFH
05FFFFH
04FFFFH
03FFFFH
02FFFFH
01FFFFH
00FFFFH
000000H
18805B-1
32 Sectors Total
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
SA 31
SA 30
SA 29
SA 28
SA 3
SA 2
SA 1
SA 0
Sector
Group 0
Sector
Group 7
MBM29F017 -90/-12
7
21 A
0
to A
20
WE
OE
CE
DQ
0
to DQ
7
8
RESET RY/BY
■LOGIC SYMBOL
Table 1 MBM29F017 Pin Configuration
Pin
A0 to A20
DQ0 to DQ7
CE
OE
WE
RY/BY
RESET
N.C.
VSS
VCC
Legend:
L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
Table 6.
2. Refer to the section on Sector Group Protection.
3.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
Table 2 MBM29F017 User Bus Operations
Operation
Auto-Select Manufacturer Code (1)
Auto-Select Device Code (1)
Read (3)
Standby
Output Disable
Write
Enable Sector Group Protection (2)
Verify Sector Group Protection (2)
Temporary Sector Group Unprotection
Reset (Hardware)
RESET
H
H
H
H
H
H
H
H
VID
L
DQ0 to DQ7
Code
Code
DOUT
High-Z
High-Z
DIN
X
Code
X
High-Z
A9
VID
VID
A9
X
X
A9
VID
VID
X
X
A6
L
L
A6
X
X
A6
X
L
X
X
A1
L
L
A1
X
X
A1
X
H
X
X
A0
L
H
A0
X
X
A0
X
L
X
X
WE
H
H
H
X
H
L
L
H
X
X
OE
L
L
L
X
H
H
VID
L
X
X
CE
L
L
L
H
L
L
L
L
X
X
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Ready-Busy Output
Hardware Reset Pin/Sector Protection
Unlock
No Internal Connection
Device Ground
Device Power Supply
(5.0 V ± 10 % or ± 5 %)
MBM29F017 -90/-12
6
■CONNECTION DIAGRAMS
N.C.
N.C.
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
CE
V
CC
N.C.
RESET
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
N.C.
N.C.
N.C.
N.C.
A
20
N.C.
WE
OE
RY/BY
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
V
SS
V
SS
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MBM29F016
Standard Pinout
N.C.
N.C.
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
DQ
3
V
SS
V
SS
V
CC
DQ
4
DQ
5
DQ
6
DQ
7
RY/BY
OE
WE
N.C.
A
20
N.C.
N.C.
N.C.
N.C.
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
RESET
N.C.
V
CC
CE
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
N.C.
N.C.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
(Marking Side)
FPT-48P-M19
TSOP
MBM29F016
Reverse Pinout
(Marking Side)
FPT-48P-M20
MBM29F017 -90/-12
7
21
A 0 to A 20
WE
OE
CE
DQ 0 to DQ 7 8
RESET RY/BY
■LOGIC SYMBOL
Table 1 MBM29F017 Pin Configuration
Pin
A0 to A20
DQ0 to DQ7
CE
OE
WE
RY/BY
RESET
N.C.
VSS
VCC
Legend:
L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
Table 6.
2. Refer to the section on Sector Group Protection.
3.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
Table 2 MBM29F017 User Bus Operations
Operation
Auto-Select Manufacturer Code (1)
Auto-Select Device Code (1)
Read (3)
Standby
Output Disable
Write
Enable Sector Group Protection (2)
Verify Sector Group Protection (2)
Temporary Sector Group Unprotection
Reset (Hardware)
RESET
H
H
H
H
H
H
H
H
VID
L
DQ0 to DQ7
Code
Code
DOUT
High-Z
High-Z
DIN
X
Code
X
High-Z
A9
VID
VID
A9
X
X
A9
VID
VID
X
X
A6
L
L
A6
X
X
A6
X
L
X
X
A1
L
L
A1
X
X
A1
X
H
X
X
A0
L
H
A0
X
X
A0
X
L
X
X
WE
H
H
H
X
H
L
L
H
X
X
OE
L
L
L
X
H
H
VID
L
X
X
CE
L
L
L
H
L
L
L
L
X
X
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Ready-Busy Output
Hardware Reset Pin/Sector Protection
Unlock
No Internal Connection
Device Ground
Device Power Supply
(5.0 V ± 10 % or ± 5 %)
MBM29F017 -90/-12
8
■ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
SPEED OPTION
See Product Selector Guide
MBM29F017 –90 PFTN
DEVICE NUMBER/DESCRIPTION
MBM29F017
16 Mega-bit (2M × 8-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
64K Bytes (32 Sectors)
MBM29F017 -90/-12
9
Read Mode
The MBM29F017 has two control functions which must be satisfied in order to obtain data at the outputs. CE
is the power control and should be used for a device selection.
OE
is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable
CE
to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.)
Standby Mode
There are two ways to implement the standby mode on the MBM29F016 device, one using both the
CE
and
RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and
RESET
inputs both held at
VCC±0.3 V. Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with
CE and
RESET
pins held at VIH. Under this condition the current is reduced to approximately 1 mA. The
device can be read with standard access time (tCE) from either of these standby modes.
When using the
RESET
pin only, a CMOS standby mode is achieved with
RESET
input held at VSS±0.3 V
(CE = “H” or “L”). Under this condition the current consumed is less than 5 µA. A TTL standby mode is
achieved with
RESET
pin held at VIL (CE = “H” or “L”). Under this condition the current required is reduced to
approximately 1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before
outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the
OE
input.
Output Disable
With the
OE
input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All
addresses are DON'T CARES except A0, A1, and A6. (See Table 3.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F017 is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table 6. (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacturer's code (Fujitsu=04H) and byte 1 (A0=VIH) the device identifier
code for MBM29F017 = ADH. These two bytes are given in the table 3. All identifiers for manufacturer and
device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when
executing the Autoselect, A1 must be VIL. (See Table 3.)
The Autoselect mode also facilitates the determination of sector group protection in the system. By performing
a read operation at the address location XX02H with the higher order address bits A18, A19, and A20 set to the
desired sector group address, the device will return 01H for a protected sector group and 00H for a non-
protected sector group.
MBM29F017 -90/-12
10
A20 A19 A18 A17 A16 Address Range
SA0 0 0 0 0 0 000000H to 00FFFFH
SA1 0 0 0 0 1 010000H to 01FFFFH
SA2 0 0 0 1 0 020000H to 02FFFFH
SA3 0 0 0 1 1 030000H to 03FFFFH
SA4 0 0 1 0 0 040000H to 04FFFFH
SA5 0 0 1 0 1 050000H to 05FFFFH
SA6 0 0 1 1 0 060000H to 06FFFFH
SA7 0 0 1 1 1 070000H to 07FFFFH
SA8 0 1 0 0 0 080000H to 08FFFFH
SA9 0 1 0 0 1 090000H to 09FFFFH
SA10 0 1 0 1 0 0A0000H to 0AFFFFH
SA11 0 1 0 1 1 0B0000H to 0BFFFFH
SA12 0 1 1 0 0 0C0000H to 0CFFFFH
SA13 0 1 1 0 1 0D0000H to 0DFFFFH
SA14 0 1 1 1 0 0E0000H to 0EFFFFH
SA15 0 1 1 1 1 0F0000H to 0FFFFFH
SA16 1 0 0 0 0 100000H to 10FFFFH
SA17 1 0 0 0 1 110000H to 11FFFFH
SA18 1 0 0 1 0 120000H to 12FFFFH
SA19 1 0 0 1 1 130000H to 13FFFFH
SA20 1 0 1 0 0 140000H to 14FFFFH
SA21 1 0 1 0 1 150000H to 15FFFFH
SA22 1 0 1 1 0 160000H to 16FFFFH
SA23 1 0 1 1 1 170000H to 17FFFFH
SA24 1 1 0 0 0 180000H to 18FFFFH
SA25 1 1 0 0 1 190000H to 19FFFFH
SA26 1 1 0 1 0 1A0000H to 1AFFFFH
SA27 1 1 0 1 1 1B0000H to 1BFFFFH
SA28 1 1 1 0 0 1C0000H to 1CFFFFH
SA29 1 1 1 0 1 1D0000H to 1DFFFFH
SA30 1 1 1 1 0 1E0000H to 1EFFFFH
SA31 1 1 1 1 1 1F0000H to 1FFFFFH
Table 3 MBM29F017 Sector Protection Verify Autoselect Codes
Code
(HEX)
A6
VIL
VIL
VIL
Manufacturer’s
Code
*: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
A1
VIL
VIL
VIH
A0
VIL
VIH
VIL
04H
3DH
01H*
DQ7
0
0
0
DQ6
0
0
0
DQ5
0
1
0
DQ4
0
1
0
DQ3
0
1
0
DQ2
1
1
0
DQ1
0
0
0
DQ0
0
1
1
X
X
X
X
X
X
Sector Group
Protection Sector Group
Addresses
Type
Table 4 Sector Address Table
A18 to A20
Device Code
MBM29F017 -90/-12
11
Table 5 Sector Group Addresses
A20 A19 A18 Sectors
SGA0 0 0 0 SA0 to SA3
SGA1 0 0 1 SA4 to SA7
SGA2 0 1 0 SA8 to SA11
SGA3 0 1 1 SA12 to SA15
SGA4 1 0 0 SA16 to SA19
SGA5 1 0 1 SA20 to SA23
SGA6 1 1 0 SA24 to SA27
SGA7 1 1 1 SA28 to SA31
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while
CE
is at VIL and
OE
is at VIH. Addresses are latched
on the falling edge of
WE
or
CE
, whichever happens later; while data is latched on the rising edge of
WE
or
CE
, whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29F017 features hardware sector group protection. This feature will disable both program and erase
operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see Table
5). The sector group protection feature is enabled using programming equipment at the user's site. The device is
shipped with all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin
OE
,
(suggest VID = 11.5 V),
CE
= VIL. The sector addresses (A20, A19, and A18) should be set to the sector to be
protected. Tables 4 and 5 define the sector address for each of the thirty two (32) individual sectors, and the
sector group address for each of the eight (8) individual group sectors. Programming of the protection circuitry
begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses
must be held constant during the WE pulse. Refer to figures 14 and 21 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with
CE
and
OE
at VIL and WE at VIH. Scanning the sector addresses (A20, A19, and A18) while (A6, A1, A0) = (0,
1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce
00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are don’t care.
Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A20, A19, and
A18) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See
Table 3 for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29F016 device in
order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high
voltage (12 V). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the 12 V is taken away from the
RESET
pin, all the previously protected
sector groups will be protected again. Refer to Figures 13 and 20.
MBM29F017 -90/-12
12
Table 6 MBM29F017 Command Definitions
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both
Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
Fourth Bus
Read/Write
Cycle
Second Bus
Write Cycle Third Bus
Write Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
First Bus
Write Cycle
Addr.
—
RA
—
PA
555H
555H
Addr.
XXXH
555H
555H
555H
555H
555H
Data
F0H
AAH
AAH
AAH
AAH
AAH
Addr.
—
2AAH
2AAH
2AAH
2AAH
2AAH
Data
—
55H
55H
55H
55H
55H
Addr.
—
555H
555H
555H
555H
555H
Data
—
F0H
90H
A0H
80H
80H
Data
—
RD
—
PD
AAH
AAH
Addr.
—
—
—
—
2AAH
2AAH
Data
—
—
—
—
55H
55H
Addr.
—
—
—
—
555H
SA
Data
—
—
—
—
10H
30H
1
3
3
4
6
6
1
1
Read/Reset*
Reset/Read*
Autoselect
Byte Program
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Bus
Write
Cycles
Req'd
Command
Sequence
Erase can be suspended during sector erase with Addr (H or L), Data (B0H)
Erase can be resumed after suspend with Addr (H or L), Data (30H)
Notes: 1.Address bits A11 to A20 = X = H or L for all address commands except or Program Address (PA) and Sector
Address (SA).
2.Bus operations are defined in Table 2.
3.RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely
select any sector.
4.RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE .
5.Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.
6.The system should generate the following address patterns: 555H or 2AAH to addresses A0 to A10
∗: Either of the two reset commands will reset the device.
MBM29F017 -90/-12
13
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command
register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of
04H. A read cycle from address XX01H returns the device code ADH. (See Table 3.)
All manufacturer and device codes will exhibit odd parity with the DQ7 defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02H.
Scanning the sector group addresses (A18, A19, A20) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at
device output DQ0 for a protected sector group.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and
also to write the autoselect command during the operation, execute it after writing read/reset command
sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of
CE
or
WE
, whichever happens later and the data is latched on the rising
edge of
CE
or
WE
, whichever happens first. The rising edge of
CE
or
WE
(whichever happens first) begins
programming. Upon executing the Embedded ProgramTM Algorithm command sequence, the system is
not
required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin.
This automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 7,
Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by
the system at this particular instance of time.
Data
Polling must be performed at the memory location which is
being programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 15 illustrates the Embedded Programming Algorithm using typical command strings and bus
operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded
EraseTM Algorithm command sequence the device will automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings
during these operations.
The automatic erase begins on the rising edge of the last
WE
pulse in the command sequence and terminates
MBM29F017 -90/-12
14
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Figure 16 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of
WE
, while the
command (Data = 30H) is latched on the rising edge of
WE
. After time-out of 50 µs from the rising edge of the
last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last
WE
will initiate the execution of the Sector Erase command(s). If another falling
edge of the
WE
occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the
sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector
Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the
previous command string. Resetting the device once execution has begun will corrupt the data in that sector.
In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation
Status section for DQ3, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 31).
Sector erase does
not require the user to program the device prior to erase. The device automatically
programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or
sectors the remaining unselected sectors are not affected. The system is not required to provide any controls
or timings during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the
WE
pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the device returns to the read mode.
Data
polling must be performed at an address
within any of the sectors being erased.
Figure 16 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data
reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector
Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be
ignored if written during the Chip Erase operation or Embedded ProgramTM Algorithm. Writting the Erase
Suspend command during the Sector Erase time-out results in immediate termination of the time-out period
and suspension of the erase operation.
Any other command written during the Erase Suspend mode will be ignored except the Erase Resume
command. Writing the Erase Resume command resumes the erase operation. The addresses are “don't-
cares” when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a
maximum of 15 ms to suspend the erase operation. When the device has entered the erase-suspended mode,
the RY/BYoutput pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the
address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
MBM29F017 -90/-12
15
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode.
Reading data in this mode is the same as reading from the standard read mode except that the data must be
read from sectors that have not been erase-suspended. Successively reading from the erase-suspended
sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ 2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.
Again, programming in this mode is the same as programming in the regular Byte Program mode except that
the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-
suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of
the erase-suspended program operation is detected by the RY/BYoutput pin,
Data
polling of DQ7, or by the
Toggle Bit I (DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from
the byte program address while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Table 7 Hardware Sequence Flags
Embedded ProgramTM Algorithm
Embedded EraseTM Algorithm
1
Toggle
Data
1
N/A
N/A
DQ3
0
1
1
Data
1
0
1
1
DQ2DQ5
0
0
0
Data
0
1
1
1
DQ6
Toggle
Toggle
1
Data
Toggle
Toggle
Toggle
DQ7
DQ7
0
1
Data
DQ7
DQ7
0
DQ7
Erase
Suspended
Mode
Erase Suspend Read (Erase Suspended Sector)
Erase Suspend Read (Non-Erase Suspended Sector)
Erase Suspend Program (Non-Erase Suspended Sector)
Embedded ProgramTM Algorithm
Embedded EraseTM Algorithm
Toggle
(Note 1)
1
(Note 3)
Erase
Suspended
Mode
Toggle
(Note 2)
Exceeded
Time Limits
Notes: 1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.
2. Performing successive read operations from any address will cause DQ6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ 2 to
toggle.
Erase Suspend Program (Non-Erase
Suspended Sector)
Write Operation Status
In Progress
Status
MBM29F017 -90/-12
16
DQ7
Data
Polling
The MBM29F017 device features
Data
Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the Embedded ProgramTM Algorithm, an attempt to read the
device will produce the complement of the data last written to DQ7. Upon completion of the Embedded
ProgramTM Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the
Embedded EraseTM Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon
completion of the Embedded EraseTM Algorithm an attempt to read the device will produce a “1” at the DQ7
output. The flowchart for
Data
Polling (DQ7) is shown in Figure 17.
Data
polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase
Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in
the Erase Suspend Mode.
During Program in Erase Suspend,
Data
polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the
Data
Polling is valid after the rising edge of the sixth
WE
pulse in the six write pulse
sequence. For sector erase, the
Data
Polling is valid after the last rising edge of the sector erase
WE
pulse.
Data
Polling must be performed at sector address within any of the sectors being erased and not a sector that
is within a protected sector group. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the
output enable (
OE
) is asserted low. This means that the device is driving status information on DQ7 at one
instant of time and then that byte's valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded
Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 to DQ 6 may be still invalid. The valid
data on DQ0 to DQ7 will be read on the successive read attempts.
The
Data
Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)
See Figure 8 for the
Data
Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29F017 also features the “Toggle Bit I” as a method to indicate to the host system that the embedded
algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (
OE
toggling) data from
the device at any address
will result in DQ6 toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on
the next
successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth
WE
pulse in the four
write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth
WE
pulse in the
six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase
WE
pulse. The Toggle Bit I is active during the sector erase time out.
Either
CE
or
OE
toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 9 for the Toggle Bit I timing specifications and diagrams.
MBM29F017 -90/-12
17
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed.
Data
Polling is the only operating function of the device under this
condition. The
CE
circuit will partially power down the device under these conditions (to approximately 2 mA).
The
OE
and
WE
pins will control the output disable functions as described in Table 2.
The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously
programmed to 0. In this case the device locks out and never completes the Embedded ProgramTM Algorithm.
Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has
exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs, reset the device.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3
will remain low until the time-out is complete.
Data
Polling and Toggle Bit I are valid after the initial sector
erase command sequence.
If
Data
Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by
Data
Polling or Toggle Bit I. If DQ3 is low
(“0”), the device will accept additional sector erase commands. To insure the command has been accepted,
the system software should check the status of DQ3 prior to and following each subsequent sector erase
command. If DQ3 were high on the second status check, the command may not have been accepted.
Refer to Table 7: Hardware Sequence Flags
DQ2
Toggle Bit II
This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded EraseTM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded EraseTM Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will
cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the
byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
MBM29F017 -90/-12
18
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles
while DQ6 does not.) See also Table 7 and Figure 14.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F017 provides a RY/
BY
open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/
BY
pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29F017 is placed in an Erase Suspend mode,
the RY/
BY
output will be high, by means of connecting with a pull-up resistor to VCC.
During programming, the RY/
BY
pin is driven low after the rising edge of the fourth
WE
pulse. During an erase
operation, the RY/
BY
pin is driven low after the rising edge of the sixth
WE
pulse. The RY/
BY
pin will indicate
a busy condition during
RESET
pulse. Refer to Figure 10 for a detailed timing diagram. The RY/
BY
pin is
pulled high in standby mode.
Since this is an open-drain output, several RY/
BY
pins can be tied together in parallel with a pull-up resistor to
VCC.
RESET
Hardware Reset
The MBM29F017 device may be reset by driving the
RESET
pin to VIL. The
RESET
pin must be kept low (VIL)
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20 ms after the
RESET
pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the
RESET
pin is low and the internal reset is complete, the device goes to standby mode and cannot be
Mode
Program
Erase
Erase Suspend Read (1)
(Erase-Suspended Sector)
Erase Suspend Program
DQ2
1
toggles
toggles
1 (2)
DQ7
DQ7
0
1
DQ7 (2)
DQ6
toggles
toggles
1
toggles
Notes: 1.These status flags apply when outputs are read from a sector that has been erase-suspended.
2.These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
MBM29F017 -90/-12
19
accessed. Also, note that all the data output pins are tri-stated for the duration of the
RESET
pulse. Once the
RESET
pin is taken high, the device requires 500 ns of wake up time until outputs are valid for read access.
The
RESET
pin may be tied to the system reset input. Therefore, if a system reset occurs during the
Embedded Program or Erase Algorithm, the device will be automatically reset to read mode and this will
enable the system’s microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F017 is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completions of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be
ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are
logically correct to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on
OE
,
CE
, or
WE
will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of
OE
= VIL,
CE
= VIH or
WE
= VIH. To initiate a write cycle
CE
and
WE
must be a logical zero while
OE
is a logical one.
Power-Up Write Inhibit
Power-up of the device with
WE
=
CE
=VIL and
OE
= VIH will not accept commands on the rising edge of
WE
.
The internal state machine is automatically reset to the read mode on power-up.
MBM29F017 -90/-12
20
■ABSOLUTE MAXIMUM RATINGS
Storage Temperature .....................................................................................–45°C to +125°C
Ambient Temperature with Power Applied.....................................................–25°C to +85°C
Voltage with Respect to Ground All pins except A9,OE ,
RESET
(Note 1) .....–2.0 V to +7.0 V
VCC (Note 1) ...................................................................................................–2.0 V to +7.0 V
A9,OE ,
RESET
(Note 2) ...............................................................................–2.0 V to +13.5 V
Notes: 1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may negative over-
shoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V.
During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods up to 20 ns.
2.Minimum DC input voltage on A9,OE ,
RESET
pins are –0.5 V. During voltage transitions,
A9,OE ,
RESET
pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC
input voltage on A9,OE ,
RESET
are +13.0 V which may overshoot to 13.5 V for periods up to 20 ns.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure of the device to absolute
maximum rating conditions for extended periods may affect device reliability.
■OPERATING RANGES
Commercial Devices
Ambient Temperature (TA).........................................................................0°C to +70°C
VCC Supply Voltages
VCC for MBM29F017-90..............................................................................+4.75 V to +5.25 V
VCC for MBM29F017-12..............................................................................+4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
MBM29F017 -90/-12
21
■MAXIMUM OVERSHOOT
Figure 1 Maximum Negative Overshoot Waveform
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
V
CC
+
0.5 V
+
2.0 V
V
CC
+
2.0 V
20 ns
20 ns20 ns
Figure 2 Maximum Positive Overshoot Waveform
+
13.0 V
V
CC
+
0.5 V
+
13.5 V
20 ns
20 ns20 ns
*: This waveform is applied for A
9
, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform
MBM29F017 -90/-12
22
■DC CHARACTERISTICS
TTL/NMOS Compatible
ILI
ILO
ILIT
ICC1
ICC2
ICC3
ICC4
VIL
VIH
VID
VOL
VOH
VLKO
µA
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
±1.0
±1.0
50
40
60
1.0
1.0
0.8
VCC+0.5
12.5
0.45
—
4.2
—
—
—
—
—
—
—
–0.5
2.0
11.5
—
2.4
3.2
Parameter
Symbol UnitMax.Min.
Input Leakage Current
Outputs Leakage Current
A9, OE, RESET Inputs Leak-
age Current
VCC Active Current (Note 1)
VCC Active Current (Note 2)
VCC Current (Standby)
VCC Current (Standby, Reset)
Input Low Level
Input High Level
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
Parameter Description Test Conditions
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
VCC = VCC Max.
A9 , OE, RESET= 12.0V
CE = VIL, OE = VIH
CE = VIL, OE = VIH
VCC = VCC Max., CE = VIH, RESET = VIH
VCC = VCC Max., RESET = VIL
—
—
VCC = 5.0V
IOL = 12mA, VCC = VCC Min.
IOH = –2.5mA, VCC = VCC Min.
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is 2 mA/MHz, with OE VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
—
MBM29F017 -90/-12
23
µA
mA
mA
µA
µA
V
V
V
V
V
V
V
50
40
60
5
5
0.8
VCC+0.3
12.5
0.45
—
—
4.2
CMOS Compatible
UnitMin.Parameter Description Test Conditions Max.
ILI
ILO
ILIT
ICC1
ICC2
ICC3
ICC4
VIL
VIH
VID
VOL
VOH1
VOH2
VLKO
Input Leakage Current
Output Leakage Current
A9, OE, RESET Inputs Leak-
age Current
VCC Active Current (Note 1)
VCC Active Current (Note 2)
VCC Current (Standby)
VCC Current (Standby, Reset)
Input Low Level
Input High Level
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-out Voltage
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
VCC = VCC Max.
A9, OE, RESET= 12.0V
CE = VIL, OE = VIH
CE = VIL, OE = VIH
VCC = VCC Max., CE = VCC ±0.3V,
RESET = VCC ±0.3V
V
CC
= V
CC
Max., RESET = V
SS
±
0.3V
—
—
VCC = 5.0V
IOL = 12.0 mA, VCC = VCC Min.
IOH = –2.5 mA, VCC = VCC Min.
IOH = –100 µA, VCC = VCC Min.
—
—
—
±1.0
±1.0
µA
µA
—
—
—
—
—
–0.5
0.7×VCC
11.5
—
0.85×VCC
VCC–0.4
3.2
Parameter
Symbol
Notes: 1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is 2 mA/MHz, with OE at VIH.
2.ICC active while Embedded Algorithm (program or erase) is in progress.
MBM29F017 -90/-12
24
C
L
5.0 V
Diodes = IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
IN3064
or Equivalent
6.2 kΩ
Note: C
L
= 100 pF including jig capacitance
■AC CHARACTERISTICS
Read only Operations Characteristics
Parameter
Symbols
JEDEC Standard
nstAVAV tRC Read Cycle Time 90Min.
Address to Output DelaytAVQV tACC ns90Max.
nstELQV tCE Chip Enable to Output Delay 90Max.
Output Enable to Output DelaytGLQV tOE nsMax.
Description Unit
Test Setup –90
(Note)
Chip Enable to Output High-Z
tEHQZ tDF ns20Max.
Output Enable to Output High-Z
tGHQZ tDF ns20
Max.
Output Hold Time From Addresses,
CE
or
OE
, Whichever Occurs First
tAXQX tOH ns0Min.
RESET
Pin Low to Read Mode
tREADY µs20
Max.
120
120
120
50
30
30
0
20
–12
(Note)
40
Note: Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45V to 2.4V
Timing measurement reference level
Input: 0.8V and 2.0V
Output: 0.8V and 2.0V
Figure 4 Test Conditions
—
—
—
—
—
—
—
CE
= VIL
OE
= VIL
OE
= VIL
MBM29F017 -90/-12
25
• Write/Erase/Program Operations
Alternate WE Controlled Writes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
sec
µs
µs
µs
µs
µs
ns
ns
90
0
45
45
0
0
0
10
0
0
0
45
20
8
1
15
50
4
100
4
4
500
40
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
Typ.
Max.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
JEDEC Standard
Parameter Symbols
Description Unit
tWC
tAS
tAH
tDS
tDH
tOES
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tGHWL
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
–90
120
0
50
50
0
0
0
10
0
0
0
50
20
8
1
15
50
4
100
4
4
500
50
–12
tOEH
tGHWL
tCS
tCH
tWP
tWPH
tWHWH1
tWHWH2
tVCS
tVLHT
tWPP
tOESP
tCSP
tRP
tBUSY
Output
Enable
Hold Time
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Output Enable Setup Time
Read
Toggle Bit I and
Data
Polling
Read Recover Time Before Write
CE
Setup Time
CE
Hold Time
Write Pulse Width
Write Pulse Width High
Byte Programming Operation
Sector Erase Operation (Note 1)
VCC Setup Time
Voltage Transition Time (Note 2)
Write Pulse Width (Note 2)
OE
Setup Time to
WE
Active (Note 2)
CE
Setup Time to
WE
Active (Note 2)
RESET
Pulse Width
Program/Erase Valid to RY/
BY
Delay
Notes: 1.This does not include the preprogramming time.
2.This timing is for Sector Protection operation.
MBM29F017 -90/-12
26
■AC/CHARACTERISTICS
• Write/Erase/Program Operations
Alternate CE Controlled Writes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
sec
µs
90
0
45
45
0
0
0
10
0
0
0
45
20
8
1
15
50
JEDEC Standard
Parameter Symbols
Description
tWC
tAS
tAH
tDS
tDH
tOES
tOEH
tGHEL
tWS
tWH
tCP
tCPH
tWHWH1
tWHWH2
tVCS
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWHWH1
tWHWH2
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
Typ.
Max.
Min.
–90
120
0
50
50
0
0
0
10
0
0
0
50
20
8
1
15
50
–12 Unit
Note: This does not include the preprogramming time.
Output
Enable
Hold Time
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Output Enable Setup Time
Read
Toggle Bit I and
Data
Polling
Read Recover Time Before Write
WE
Setup Time
WE
Hold Time
Write Pulse Width
Write Pulse Width High
Byte Programming Operation
Sector Erase Operation (Note)
VCC Setup Time
MBM29F017 -90/-12
27
WE
OE
CE
tACC
t
DF
t
OH
t
CE
t
OE
Outputs
t
RC
Addresses Addresses Stable
High-Z Output Valid High-Z
t
OEH
WAVEFORM INPUTS OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
H or L
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center Line is
High-
Impedance
“Off” State
■SWITCHING WAVEFORMS
Key to Switching Waveforms
Figure 5 AC Waveforms for Read Operations
MBM29F017 -90/-12
28
tGHWL
tWP
tDF
tDS
tWC tAH
5.0V
CE
OE
tRC
Addresses
Data
tAS
tOE
tWPH
tCS
tDH
DQ 7
PD
A0H DOUT
tCE
WE
···HPA PA
tOH
Data Polling
3rd Bus Cycle
tWHWH1
Notes: 1.PA is address of the memory location to be programmed.
2.PD is data to be programmed at byte address.
3.DQ7 is the output of the complement of the data written to the device.
4.DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles of four bus cycle sequence.
Figure 6 Alternate WE Controlled Program Operation Timings
MBM29F017 -90/-12
29
Figure 7 Alternate CE Controlled Program Operation Timings
t CP
t DS
t WHWH1
t WC t AH
5.0 V
WE
OE
Addresses
Data
t AS
t WH
t CPH
t WS
t DH
DQ 7
PD
A 0H D OUT
CE
···HPA PA
Data Polling
3 rd Bus Cycle
t GHEL
Notes: 1.PA is address of the memory location to be programmed.
2.PD is data to be programmed at byte address.
3.DQ7 is the output of the complement of the data written to the device.
4.DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles of four bus cycle sequence.
MBM29F017 -90/-12
30
tGHWL
tDS
V CC
CE
OE
Addresses
Data
tDH
AAH 55H
WE
t AH
···H···H···H
···H···HSA
tWPH
tCS
tWP
80H AAH 55H 10H/30H
tVCS
tAS
Note: SA is the sector address for Sector Erase. Addresses = ×××H for Chip Erase.
Figure 8 AC Waveforms Chip/Sector Erase Operations
MBM29F017 -90/-12
31
t
OEH
CE
WE
OE
Data
(DQ 0 to DQ 7)DQ 6 = Toggle DQ 6 = Toggle DQ 6 =
Stop Toggling DQ 0 to DQ 7
Valid
*
t
OE
t
OES
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
t
OH
WE
DQ7
t
DF
t
CH
t
CE
High-Z
DQ7 =
Valid Data
DQ0 to DQ6DQ0 to DQ6=Invalid
DQ
0
to DQ
7
Valid Data
DQ7
*
t
OE
High-Z
Figure 9 AC Waveforms for Data Polling During Embedded Algorithm Operations
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 10 AC Waveforms for Toggle Bit I During Embedded Algorithm Operations
*: DQ6 stops toggling (The device has completed the Embedded operation.)
MBM29F017 -90/-12
32
t
READY
t
RP
RESET
The rising edge of the last WE signal
CE
RY/BY
WE
t
BUSY
Entire programming
or erase operations
Figure 11 RY/BY Timing Diagram During Program/Erase Operations
Figure 12 RESET Timing Diagram
MBM29F017 -90/-12
33
A
20
, A
19
, A
18
A
9
A
1
A
6
A
9
12V
5V
12V
5V OE
WE
CE
Data
t
CSP
t
OESP
t
WPP
t
VLHT
t
VLHT
t
VLHT
t
OE
01H
SGA
X
SGA
Y
Figure 13 AC Waveforms for Sector Group Protection
SGAX: Sector Group Address for initial sector
SGAY: Sector Group Address for next sector
MBM29F017 -90/-12
34
12 V
5 V
RESET
CE
WE
RY/BY
t
VLHT
Program or Erase Command Sequence
5 V
Figure 14 Temporary Sector Group Unprotection
Figure 15 DQ2 vs. DQ6
DQ
2
DQ
6
WE Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Erase
Complete
Toggle
DQ2 and DQ6
with OE
Note: DQ
2
is read from the erase-suspended sector.
MBM29F017 -90/-12
35
No
Yes
Program Command Sequence (Address/Command):
×××
H/AAH
×××
H/55H
×××
H/A0H
Write Program Command
Sequence
(See below)
Data Polling Device
Increment Address Last Address
?
Program Address/Program Data
Start
Programming Completed
Figure 16 Embedded Programming Algorithm
■EMBEDDED ALGORITHMS
MBM29F017 -90/-12
36
×××
H/AAH
×××
H/55H
×××
H/AAH
×××
H/80H
×××
H/10H
×××
H/55H
×××
H/AAH
×××
H/55H
×××
H/AAH
×××
H/80H
×××
H/55H
Additional sector
erase commands
are optional.
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit I
Successfully Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Sector Address/30H
Sector Address/30H
Sector Address/30H
Start
Erasure Completed
■EMBEDDED ALGORITHMS
Figure 17 Embedded EraseTM Algorithm
Note: To insure the command has been accepted, the system software should check the status of DQ 3 prior to
and following each subsequent sector erase command. If DQ3 were high on the second status check, the
command may not have been accepted.
MBM29F017 -90/-12
37
VA= Byte address for programming
= Any of the sector addresses
within the sector being erased
during sector erase operation
= Any of the sector group address
within the sector not being
protected during chip erase
operation.
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 18 Data Polling Algorithm
DQ
7
= Data?
No
No
DQ
7
= Data?
DQ
5
= 1?
Yes
Yes
No
Read Byte
(DQ
0
to DQ
7
)
Addr. = V
A
Read Byte
(DQ
0
to DQ
7
)
Addr. = V
A
Yes
Start
Fail Pass
MBM29F017 -90/-12
38
DQ
6
= Toggle?
Yes
No
DQ
6
= Toggle?
DQ
5
= 1
?Yes
No
No
Yes
Read Byte
(DQ
0
to DQ
7
)
Addr. = H or L
Read Byte
(DQ
0
to DQ
7
)
Addr. = H or L
Start
Fail Pass
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5
changing to “1” .
Figure 19 Toggle Bit I Algorithm
MBM29F017 -90/-12
39
No
Yes
No
Yes
Yes
No
PLSCNT = 1
Increment PLSCNT
Data = 01H?
OE = V
ID
, A
9
= V
ID
,
CE = V
IL
, RESET = V
IH
Activate WE Pulse
Time out 100 µs
WE = V
IH
, CE = OE = V
IL
,
A
9
should remain V
ID
Read from Sector Group Addr
(A
20
, A
19
, A
18
)
A
1
= 1, A
0
= A
6
= 0
PLSCNT = 25?
Protect Another Sector
Group?
Remove V
ID
from A
9
Write Reset Command
Remove V
ID
from A
9
Write Reset Command
Start
Sector Protection
Completed
Device Failed
Set Up Sector Group Addr.
(A
20
, A
19
, A
18
)
Figure 20 Sector Group Protection Algorithm
MBM29F017 -90/-12
40
Figure 21 Temporary Sector Group Unprotection Algorithm
RESET = V
ID
(Note 1)
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector Group
Unprotection Completed
(Note 2)
Start
Notes: 1. All protected sector groups unprotected.
2. All previously protected sector groups are protected once again.
MBM29F017 -90/-12
41
■ERASE AND PROGRAMMING PERFORMANCE
Limits
Min.
Parameter Max. Unit
Typ.
15 sec
Comments
Excludes 00H programming
prior to erasure
Sector Erase Time
µsByte Programming Time Excludes system-level over-
head
sec Excludes system-level over-
head
Chip Programming Time
Erase/Program Cycle 100,000 1,000,000 Cycles
—
—
—
—
■TSOP PIN CAPACITANCE
Parameter
Symbol Parameter Description
CIN1
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
Test Setup UnitMax.Typ.
pF
pF
pF
7.5
12
9
6
8.5
7.5
VIN = 0
VOUT = 0
VIN = 0
Note: Test conditions TA = 25°C, f = 1.0 MHz
1
8 2000
16 50
MBM29F017 -90/-12
42
■PACKAGE DIMENSIONS
48-Pin Standard Thin Small Outline Package
48-Pin Reversed Thin Small Outline Package
Dimensions in mm (inches)
+0.10
–0.05
+.004
–.002
(.472±.008)
12.00±0.20
*
*
LEAD No.
48
2524
1
STAND OFF
0.10(.004) M
1.10
.043
0(0)MIN
(.008±.004)
0.20±0.10
TYP
0.50(.0197)
(.460)
11.50REF
(.006±.002)
0.15±0.05
(.020±.004)
0.50±0.10
0.10(.004)
(.748±.008)
19.00±0.20
(.787±.008)
20.00±0.20
(.724±.008)
18.40±0.20
"A"
INDEX
0.25(.010)0.15(.006) MAX
0.35(.014)
MAX
0.15(.006)
Details of "A" part
1994 FUJITSU LIMITED F48029S-1C-1
C
Dimensions in mm (inches)
+0.10
–0.05
+.004
–.002
12.00±0.20(.472±.008)*
*
LEAD No.
48
2524
1
STAND OFF
0.10(.004) M
1.10
.043
0(0)MIN
(.008±.004)
0.20±0.10
TYP
0.50(.0197)
11.50(.460)REF
(.006±.002)
0.15±0.10
(.020±.004)
0.50±0.10
0.10(.004)
(.748±.008)
19.00±0.20
(.787±.008)
20.00±0.20
(.724±.008)
18.40±0.20
"A"
INDEX
0.25(.010)0.15(.006) MAX
0.35(.014)
MAX
0.15(.006)
Details of "A" part
1994 FUJITSU LIMITED F48030S-1C-1
C
(MOUTING HEIGHT)
* Resin Protrusion.(Each side: 0.15(.006)MAX)
* Resin Protrusion.(Each side: 0.15(.006)MAX)
(MOUTING HEIGHT)
MBM29F017 -90/-12
43
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Com-
plete Information sufficient for construction purposes is not nec-
essarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu as-
sumes no responsibility for inaccuracies.
The information contained in this document does not convey
any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10
63303 Dreieich–Buchschlag
Germany
Tel: (06103) 690–0
Fax: (06103) 690–122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 0718
Tel: 336-1600
Fax: 336-1609
FUJITSU LIMITED Printed in Japan
P9606
