UVDM40SC
DC to 40 GHz MMIC Medium Power
Voltage Controlled Attenuator
Data Sheet
Application
The UVDM40SC MMIC voltage
controlled attenuator is ideal for
high frequency and broadband
applications in test equipment,
commercial and military systems.
The attenuator is especially suited
for applications needing a moder-
ate amount of adjustable attenua-
tion and fast attenuation control
from DC to millimeter frequen-
cies. The device is also useful as a
general purpose building block in
communications systems.
Description
The UVDM40SC is a medium-
power DC-40 GHz PHEMT FET
attenuator. The performance of the
device is controlled by two bias
voltages, Vseries and Vshunt. The bias
voltages control the match and
attenuation of the device when
varied between -1V and +0.5V
DC. Please refer to the tables of
recommended bias settings opti-
mized for flat insertion loss and
flat attenuation for additional
information.
Features
• Wideband operation: DC to 40 GHz
•Low Insertion Loss (<3 dB)
•Good Input/Output Match
•Medium Attenuation (max. 18 dB)
•Size: 1640 x 920 µm
Specifications subject to change without notice. Copyright © 2003 Centellax Inc. Printed in USA Rev 1001-0001
Centellax Inc. 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069 • Email sales@centellax.com • Tel 866.522.6888 • Fax 707.568.7647
Key Specifications
Zo=50 Ω
Parameter Description Minimum Typical Maximum
Attenuation (dB) DC to 40 GHz 0 — 18
Flatness (±dB) DC to 40 GHz — 1.0 —
Insertion Loss (dB) DC to 40 GHz 3 — 20
S11 (dB) DC to 50 GHz — -10 -8
S22 (dB) DC to 50 GHz — -10 -8
P-1dB (dBm) 1dB Gain Compression 10 12 —
0 to 15 dB Attenuation
Figure 2: Typical on wafer measured performance.
Figure 1: Typical on wafer measured performance.
Note: S-parameter measurement files are available upon request. Email: support@centellax.com for more information.
(*) Midband
Centellax Inc. 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069 • Email sales@centellax.com • Tel 866.522.6888 • Fax 707.568.7647
Vseries(V) Vshunt (V) Att. (dB)*
-0.625 0.343 18.3
-0.625 -0.287 15.9
-0.625 -0.400 13.6
-0.616 -0.456 11.6
-0.608 -0.501 9.6
-0.601 -0.544 7.5
-0.595 -0.583 5.7
-0.569 -0.622 3.8
-0.550 -0.700 1.8
0.500 -1.000 0
Vseries(V) Vshunt (V) Loss (dB)*
-0.650 0.000 19.2
-0.650 -0.312 16.9
-0.650 -0.413 14.6
-0.650 -0.475 12.4
-0.641 -0.513 10.7
-0.618 -0.549 8.9
0.595 -0.583 7.1
-0.568 -0.624 5.1
-0.550 -0.700 3.3
0.500 -1.000 1.4
Figure 4: Typical on wafer measured performance.
Figure 3: Typical on wafer measured performance.
Optimized for Flat Insertion Loss (Typical)
Optimized for Flat Attenuation (Typical)
18
16
14
12
10
8
6
4
2
0
19
17
15
12
10
9
7
5
3
1
Figure 5: Typical on evaluated package measured performance.
Supplemental Specifications
Parameter Description Minimum Typical Maximum
Vseries Attenuation Control Voltage -2 V — 0.5 V
Vshunt Attenuation Control Voltage -2 V — 0.5 V
DCin DC feedback circuit input 0 V 0.25 V 1 V
DCout DC feedback circuit output 0 V 0.25 V 1 V
GND Backside Ground Plane
Tch Channel Temperature — — 150oC
Θch Thermal Resistance (Tcase=25oC) — 60oC/Watt — Pick up and Chip Handling:
The chip has exposed air bridges
on the top surface. Do not pick up
chip with vacuum on the die cen-
ter; handle at edges or with a cus-
tom collet.
ESD Handling and Bonding:
This MMIC is ESD sensitive and
preventive measures should be
taken during handling, die attach
and bonding.
Epoxy die attach is recommended.
Please visit our website for more
handling, die attach and bonding
information.
(www.centellax.com)
Figure 6: UVDM40SC
Simplified Schematic
Diagram
Centellax Inc. 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069 • Email sales@centellax.com • Tel 866.522.6888 • Fax 707.568.7647
6
8
10
12
14
16
18
20
22
24
26
0 5 10 15 20
Input Referred P1dB (dBm)
Attenuation (dB)
Typical Pin(-1dB) vs Attenuation
2GHz
4GHz
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
20GHz
22GHz
Centellax Inc. 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069 • Email sales@centellax.com • Tel 866.522.6888 • Fax 707.568.7647
DC Feedback Circuit for
Variable Attenuator
The following feedback circuit
does a good job of providing the
series and shunt biases to the vari-
able attenuator for a user-selected
amount of attenuation.
The circuit references a 1/3 scale
version of the microwave attenua-
tor, which is used for the DC feed-
back loop. Because the devices are
1/3 the size of the unscaled atten-
uator , the reference impedence is 3
times larger (150Ω instead of
50Ω).
The circuit uses two ordinary
opamps to provide the bias control
voltages to the attenuator. Opamp
OA1 senses the input impedance
of the attenuator and adjusts the
series FET gate voltage Vseries so
that the impedance looking into
the attenuator is 150Ω. The input
impedance can be adjusted with
the potentiometer shown in the
schematic (Figure 7). When this
feedback loop is at DC equilib-
rium the voltage at DCin will be
Vref/2.
The second opamp OA2 adjusts
the shunt FET gate voltage so that
the DC output voltage DCout is
equal to the voltage at the opamp
negative input terminal. When 0V
is applied to the negative input ter-
minal of OA2, the attenuation is
maximized.
Conversely, if Vref/2 is applied at
the negative input of OA2 then the
attenuation is minimized.
A voltage divider with the shunt
resistor terminated by the voltage
Vref makes for a convienient con-
version of voltage to attenuation.
If the input to the divider Vatten is
set to 0 volts then the negative
input of OA2 will have a value of
Vref/2 and the attenuator will have
minimum attenuation.
Conversely, if Vatten is set to –Vref
then the negative input of OA2 is
set 0V and the attenuator will have
maximum attenuation. This makes
the calculation of Vatten easy and
requires a minimum number of
parts.
Figure 7: Scaled DC Attenuator
Circuit (1/3 scale attenuator)
Figure 8:
The DC feedback
circuit to adjust
the attenuator
Centellax Inc. 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069 • Email sales@centellax.com • Tel 866.522.6888 • Fax 707.568.7647
Specifications subject to change without notice. Copyright © 2003 Centellax Inc. Printed in USA Rev 1001-0001
Physical
Characteristics of
UVDM40SC
Assembly Diagram of
UVDM40SC
Chip size: 1640 x 920 µm
Chip size Tolerance: ±5 µm
Chip Thickness: 100 ±10 µm
Pad Dimensions: 80 x 80 µm