LTC6102
LTC6102-1/LTC6102HV
1
6102fc
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Precision Zero Drift
Current Sense Amplifi er
The LTC
®
6102/LTC6102HV are versatile, high voltage, high-
side current sense amplifi ers. Their high supply voltage
rating allows their use in many high side applications,
while the low drift and offset ensure accuracy across a
wide range of operating conditions. The LTC6102-1 is a
version of the LTC6102 that includes a low power disable
mode to conserve system standby power.
The LTC6102/LTC6102HV monitor current via the voltage
across an external sense resistor (shunt resistor). Internal
circuitry converts input voltage to output current, allowing
a small sense signal on a large common mode voltage to
be translated to a ground-referred signal. Low DC offset
allows the use of very low shunt resistor values and large
gain-setting resistors. As a result, power loss in the shunt
is reduced.
The wide operating supply and high accuracy make the
LTC6102 ideal for a large array of applications, from auto-
motive, to industrial and power management. A maximum
input sense voltage of 2V allows a wide range of currents
and voltages to be monitored. Fast response makes the
LTC6102 the perfect choice for load current warnings and
shutoff protection control.
All versions of the LTC6102 are available in 8-lead MSOP
and 3mm × 3mm DFN packages.
n Supply Range:
4V to 60V, 70V Maximum (LTC6102)
5V to 100V, 105V Maximum (LTC6102HV)
n ±10μV Input Offset Maximum
n ±50nV/°C Input Offset Drift Maximum
n Fast Response: 1μs Step Response
n Gain Confi gurable with Two Resistors
n Low Input Bias Current: 3nA Maximum
n PSRR 130dB Minimum
n Output Currents up to 1mA
n Operating Temperature Range: –40°C to 125°C
n Disable Mode (LTC6102-1 Only): 1μA Maximum
n Available in 8-Lead MSOP and 3mm × 3mm
DFN Packages
n Current Shunt Measurement
n Battery Monitoring
n Remote Sensing
n Load Protection
n Motor Control
n Automotive Controls
Dynamic Current
Measurement Range
10A Current Sense with 10mA Resolution and 100mW
Maximum Dissipation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TO μP
6102 TA01
LTC2433-1
ROUT
4.99k
VOUT
1μF
5V
L
O
A
D
VOUT = • VSENSE = 249.5VSENSE
ROUT
RIN
*PROPER SHUNT SELECTION COULD ALLOW
MONITORING OF CURRENTS IN EXCESS OF 1000A
LTC6102
RIN
20Ω
VSENSE
1mΩ
5V TO
105V
V+
V–
OUT
+IN
+
–
–INF
–INS
VREG 0.1μF
–
+
+
DYNAMIC RANGE (dB)
MAXIMUM SENSE VOLTAGE (V)
0.0001
110
100
90
80
70
60
50
40
30
20
0.001 0.01 10.1
6102 TA01b
DYNAMIC RANGE RELATIVE
TO 10μV OFFSET VOLTAGE
RSENSE = 100mΩ
Max VSENSE = 1V
RSENSE = 10mΩ
Max VSENSE = 100μV
LTC6102
LTC6102-1/LTC6102HV
2
6102fc
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V–):
LTC6102/LTC6102-1 .............................................70V
LTC6102HV .........................................................105V
Input Voltage Range
–INF, –INS ................................ (V+ – 4V to V+ + 0.3V)
+IN ............................................ (V+ – 20V to V+ + 1V)
EN ............................................ (V– – 0.3V to V– + 9V)
Differential (–INS – +IN), 1 Second ......................60V
Output Voltage Range
LTC6102/LTC6102HV ............... (V– – 0.3V to V– + 9V)
LTC6102-1 ............................. (V– – 0.3V to V– + 15V)
Input Current
–INF, –INS ........................................................±10mA
+IN ...................................................................–10mA
EN ....................................................................±10mA
(Note 1)
Output Current .......................................(+1mA, –10mA)
Output Short Circuit Duration........................... Indefi nite
Operating Temperature Range: (Note 2)
LTC6102C/LTC6102C-1/LTC6102HVC .. –40°C to 85°C
LTC6102I/LTC6102I-1/LTC6102HVI ...... –40°C to 85°C
LTC6102H/LTC6102H-1
LTC6102HVH...................................... –40°C to 125°C
Specifi ed Temperature Range: (Note 2)
LTC6102C/LTC6102C-1/LTC6102HVC ...... 0°C to 70°C
LTC6102I/LTC6102I-1/LTC6102HVI ...... –40°C to 85°C
LTC6102H/LTC6102H-1
LTC6102HVH...................................... –40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
TOP VIEW
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN
5
6
7
8
4
9
3
2
1–INS
–INF
V–/EN*
OUT
+IN
V+
VREG
V–
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB
*V– FOR THE LTC6102/LTC6102HV, EN FOR THE LTC6102-1
1
2
3
4
–INS
–INF
V–/EN*
OUT
8
7
6
5
+IN
V+
VREG
V–
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 200°C/W
*V– FOR THE LTC6102/LTC6102HV, EN FOR THE LTC6102-1
PIN CONFIGURATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6102CDD#PBF LTC6102CDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102IDD#PBF LTC6102IDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HDD#PBF LTC6102HDD#TRPBF LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102CDD-1#PBF LTC6102CDD-1#TRPBF LDYB 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102IDD-1#PBF LTC6102IDD-1#TRPBF LDYB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HDD-1#PBF LTC6102HDD-1#TRPBF LDYB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102HVCDD#PBF LTC6102HVCDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102HVIDD#PBF LTC6102HVIDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HVHDD#PBF LTC6102HVHDD#TRPBF LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102CMS8#PBF LTC6102CMS8#TRPBF LTCKJ 8-Lead Plastic MSOP 0°C to 70°C
LTC6102IMS8#PBF LTC6102IMS8#TRPBF LTCKJ 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HMS8#PBF LTC6102HMS8#TRPBF LTCKJ 8-Lead Plastic MSOP –40°C to 125°C
ORDER INFORMATION
LTC6102
LTC6102-1/LTC6102HV
3
6102fc
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6102CMS8-1#PBF LTC6102CMS8-1#TRPBF LTDXZ 8-Lead Plastic MSOP 0°C to 70°C
LTC6102IMS8-1#PBF LTC6102IMS8-1#TRPBF LTDXZ 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HMS8-1#PBF LTC6102HMS8-1#TRPBF LTDXZ 8-Lead Plastic MSOP –40°C to 125°C
LTC6102HVCMS8#PBF LTC6102HVCMS8#TRPBF LTCVB 8-Lead Plastic MSOP 0°C to 70°C
LTC6102HVIMS8#PBF LTC6102HVIMS8#TRPBF LTCVB 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HVHMS8#PBF LTC6102HVHMS8#TRPBF LTCVB 8-Lead Plastic MSOP –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6102CDD LTC6102CDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102IDD LTC6102IDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HDD LTC6102HDD#TR LCKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102CDD-1 LTC6102CDD-1#TR LDYB 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102IDD-1 LTC6102IDD-1#TR LDYB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HDD-1 LTC6102HDD-1#TR LDYB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102HVCDD LTC6102HVCDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6102HVIDD LTC6102HVIDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6102HVHDD LTC6102HVHDD#TR LCVC 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6102CMS8 LTC6102CMS8#TR LTCKJ 8-Lead Plastic MSOP 0°C to 70°C
LTC6102IMS8 LTC6102IMS8#TR LTCKJ 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HMS8 LTC6102HMS8#TR LTCKJ 8-Lead Plastic MSOP –40°C to 125°C
LTC6102CMS8-1 LTC6102CMS8-1#TR LTDXZ 8-Lead Plastic MSOP 0°C to 70°C
LTC6102IMS8-1 LTC6102IMS8-1#TR LTDXZ 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HMS8-1 LTC6102HMS8-1#TR LTDXZ 8-Lead Plastic MSOP –40°C to 125°C
LTC6102HVCMS8 LTC6102HVCMS8#TR LTCVB 8-Lead Plastic MSOP 0°C to 70°C
LTC6102HVIMS8 LTC6102HVIMS8#TR LTCVB 8-Lead Plastic MSOP –40°C to 85°C
LTC6102HVHMS8 LTC6102HVHMS8#TR LTCVB 8-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
(LTC6102, LTC6102-1) The l denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at TA = 25°C. RIN = 10Ω, ROUT = 10k, VSENSE+ = V+ (see Figure 1 for
details), V+ = 12V, V– = 0V, VEN = 2.2V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V+Supply Voltage Range 460V
VOS Input Offset Voltage
(Note 3)
VSENSE = 100μV
6V ≤ V+ ≤ 60V
V+ = 4V
3
5
10
25
μV
μV
Input Offset Voltage
(Note 4)
VSENSE = 100μV
6V ≤ V+ ≤ 60V
V+ = 4V
3
5
35
50
μV
μV
ΔVOS/ΔTInput Offset Voltage Drift
(Note 3)
VSENSE = 100μV
LTC6102C, LTC6102I, LTC6102C-1, LTC6102I-1
LTC6102H, LTC6102H-1
l
l
25
25
50
75
nV/°C
nV/°C
IBInput Bias Current (Note 5) RIN = 40k, VSENSE = 2mV
LTC6102C, LTC6102I, LTC6102C-1, LTC6102I-1
LTC6102H, LTC6102H-1
l
l
60
3
20
pA
nA
nA
LTC6102
LTC6102-1/LTC6102HV
4
6102fc
ELECTRICAL CHARACTERISTICS
(LTC6102, LTC6102-1) The l denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at TA = 25°C. RIN = 10Ω, ROUT = 10k, VSENSE+ = V+ (see Figure 1 for
details), V+ = 12V, V– = 0V, VEN = 2.2V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection Ratio VSENSE = 100μV, V+ = 6V to 60V
l
130
125
150 dB
dB
VSENSE = 100μV, V+ = 4V to 60V
l
120
115
140 dB
dB
VSENSE(MAX) Input Sense Voltage Full Scale
(V+ – VIN+)
Error <1%, RIN = 10k, ROUT = 10k
6V ≤ V+ ≤ 60V
V+ = 4V
l
l
2
0.8
V
V
VOUT Maximum Output Voltage
(LTC6102)
VSENSE = 2mV, ROUT = 100k
12V ≤ V+ ≤ 60V
V+ = 6V
V+ = 4V
l
l
l
8
3
1
V
V
V
Maximum Output Voltage
(LTC6102-1)
VSENSE = 2mV, ROUT = 100k
V+ = 60V
V+ = 12V
V+ = 4V
l
l
l
14
11.7
3.8
V
V
V
IOUT Maximum Output Current 6V ≤ V+ ≤ 60V, RIN = 1k, ROUT = 1k, VSENSE = 1.1V
V+ = 4V, RIN = 10Ω, ROUT = 1k, VSENSE = 11mV
l
l
1
0.5
mA
mA
trInput Step Response (to 2.5V on
a 5V Output Step)
ΔVSENSE = 100mV Transient, 6V ≤ V+ ≤ 60V, RIN = 100Ω,
ROUT = 4.99k, IOUT = 100μA
1μs
V+ = 4V 1.5 μs
BW Signal Bandwidth IOUT = 200μA, RIN = 100Ω, ROUT = 4.99k
IOUT = 1mA, RIN = 100Ω, ROUT = 4.99k
140
200
kHz
kHz
eNInput Noise Voltage 0.1Hz to 10Hz 2 μVP-P
ISSupply Current V+ = 4V, IOUT = 0, RIN = 10k, ROUT = 100k
l
275 400
475
μA
μA
V+ = 6V, IOUT = 0, RIN = 10k, ROUT = 100k
l
290 425
500
μA
μA
V+ = 12V, IOUT = 0, RIN = 10k, ROUT = 100k
l
300 450
525
μA
μA
V+ = 60V, IOUT = 0, RIN = 10k, ROUT = 100k l420 575 μA
LTC6102C, LTC6102I, LTC6102C-1, LTC6102I-1 l650 μA
LTC6102H, LTC6102H-1 l675 μA
IDIS Supply Current in Disable Mode
(LTC6102-1 Only)
VEN = 0.8V, V+ = 12V
VEN = 0.8V, V+ = 60V
l
l
1
18
μA
μA
VENL Enable Input Voltage Low
(LTC6102-1 Only)
l0.8 V
VENH Enable Input Voltage High
(LTC6102-1 Only)
l2.2 V
IBEN Enable Input Pin Current
(LTC6102-1 Only)
VEN = 0V to 9V l8μA
tON Turn-On Time (LTC6102-1 Only) VEN = 2.2V, VSENSE = 1mV, Output Settles to Within 1% of
Final Value
500 μs
tOFF Turn-Off Time (LTC6102-1 Only) VEN = 0.8V, VSENSE = 1mV, Supply Current Drops to Less
Than 10% of Nominal Value
100 μs
fSSampling Frequency 10 kHz
LTC6102
LTC6102-1/LTC6102HV
5
6102fc
ELECTRICAL CHARACTERISTICS
(LTC6102HV) The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. RIN = 10Ω, ROUT = 10k, VSENSE+ = V+ (see Figure 1 for details),
V+ = 12V, V– = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V+Supply Voltage Range 5 100 V
VOS Input Offset Voltage
(Note 3)
VSENSE = 100μV
6V ≤ V+ ≤ 100V
V+ = 5V
3
5
10
25
μV
μV
Input Offset Voltage
(Note 4)
VSENSE = 100μV
6V ≤ V+ ≤ 100V
V+ = 5V
3
5
35
50
μV
μV
ΔVOS/ΔTInput Offset Voltage Drift (Note 3) VSENSE = 100μV
LTC6102HVC, LTC6102HVI
LTC6102HVH
l
l
25
25
50
75
nV/°C
nV/°C
IBInput Bias Current (Note 5) RIN = 40k, VSENSE = 2mV
LTC6102HVC, LTC6102HVI
LTC6102HVH
l
l
60
3
20
pA
nA
nA
PSRR Power Supply Rejection Ratio VSENSE = 100μV, V+ = 6V to 100V
l
130
125
150 dB
dB
VSENSE = 100μV, V+ = 5V to 100V
l
120
115 140
dB
dB
VSENSE(MAX) Input Sense Voltage Full Scale
(V+ – V+IN)
Error <1%, RIN = 10k, ROUT = 10k
6V ≤ V+ ≤ 100V
V+ = 5V
l
l
2
1
V
V
VOUT Maximum Output Voltage VSENSE = 2mV, ROUT = 100k
12V ≤ V+ ≤ 100V
V+ = 5V
l
l
8
3
V
V
IOUT Maximum Output Current 6V ≤ V+ ≤ 100V, RIN = 1k, ROUT = 1k, VSENSE = 1.1V
V+ = 5V, RIN = 10Ω, ROUT = 1k, VSENSE = 11mV
l
l
1
0.5
mA
mA
trInput Step Response (to 2.5V on a
5V Output Step)
ΔVSENSE = 100mV Transient, 6V ≤ V+ ≤ 100V,
RIN = 100Ω, ROUT = 4.99k, IOUT = 100μA
1μs
V+ = 5V 1.5 μs
BW Signal Bandwidth IOUT = 200μA, RIN = 100Ω, ROUT = 4.99k
IOUT = 1mA, RIN = 100Ω, ROUT = 4.99k
140
200
kHz
kHz
eNInput Noise Voltage 0.1Hz to 10Hz 2 μVP-P
ISSupply Current V+ = 5V, IOUT = 0, RIN = 10k, ROUT = 100k
l
275 400
475
μA
μA
V+ = 6V, IOUT = 0, RIN = 10k, ROUT = 100k
l
280 425
500
μA
μA
V+ = 12V, IOUT = 0, RIN = 10k, ROUT = 100k
l
290 450
525
μA
μA
V+ = 100V, IOUT = 0, RIN = 10k, ROUT = 100k 420 575 μA
LTC6102HVC, LTC6102HVI l650 μA
LTC6102HVH l675 μA
fSSampling Frequency 10 kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. In addition to the Absolute Maximum Ratings, the
output current of the LTC6102 must be limited to ensure that the power
dissipation in the LTC6102 does not allow the die temperature to exceed
150°C. See the Applications Information “Output Current Limitations Due
to Power Dissipation” for further information.
Note 2: The LTC6102C/LTC6102C-1/LTC6102HVC are guaranteed to meet
specifi ed performance from 0°C to 70°C. The LTC6102C/LTC6102C-1/
LTC6102HVC are designed, characterized and expected to meet specifi ed
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. LTC6102I/LTC6102I-1/LTC6102HVI are guaranteed
to meet specifi ed performance from –40°C to 85°C. The LTC6102H/
LTC6102H-1/LTC6102HVH are guaranteed to meet specifi ed performance
from –40°C to 125°C.
LTC6102
LTC6102-1/LTC6102HV
6
6102fc
Input VOS vs Temperature Input VOS vs Supply Voltage Input Sense Range
LTC6102: VOUT Maximum vs
Temperature
LTC6102HV: VOUT Maximum vs
Temperature
LTC6102/LTC6102-1: IOUT
Maximum vs Temperature
INPUT OFFSET (μV)
20
15
10
5
0
–5
–10
–15
–20
6102 G01
TEMPERATURE (°C)
–40 12004080
–20 20 60 100
VS = 12V
VS = 4V
SUPPLY VOLTAGE (V)
6102 G02
43212 168242820 36 44 4840 52 56 60
INPUT OFFSET (μV)
20
15
10
5
0
–5
–10
–15
–20
TA = –40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 85°C
TA = 125°C
04020 12010060 80
VSUPPLY (V)
MAXIMUM VSENSE (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
6102 G03
TA = 25°C
TEMPERATURE (°C)
–40 40 80 120100–20
6102 G04
020 60
MAXIMUM VOUT (V)
VS = 60V
VS = 12V
VS = 6V
VS = 5V
VS = 4V
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEMPERATURE (°C)
–40 40 80 120100–20
6102 G05
020 60
MAXIMUM VOUT (V)
VS = 100V
VS = 12V
VS = 6V
VS = 5V
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEMPERATURE (°C)
6102 G06
MAXIMUM IOUT (mA)
VS = 12V
VS = 60V
VS = 6V
VS = 5V
VS = 4V
–40 40 80 120100–20 0 20 60
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Note 3: These Parameters are guaranteed by design and are not 100%
tested. Thermocouple effects preclude measurements of these voltage
levels during automated testing.
Note 4: Limits are fully tested. Limit is determined by high speed
automated test capability.
Note 5: IB specifi cation is limited by practical automated test resolution.
Please refer to the Typical Performance Characteristics section for
more information regarding actual typical performance. For tighter
specifi cations, please contact LTC Marketing.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6102
LTC6102-1/LTC6102HV
7
6102fc
LTC6102HV: IOUT Maximum vs
Temperature Gain vs Frequency
TEMPERATURE (°C)
6102 G07
MAXIMUM IOUT (mA)
VS = 12V
VS = 100V
VS = 6V
VS = 5V
–40 40 80 120100–20 0 20 60
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GAIN (dB)
FREQUENCY (Hz)
1k
40
35
30
25
20
15
10
5
0
–5
–10 10k 100k 10M1M
6102 G09
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
IOUT = 200μA DC
IOUT = 1mA DC
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs Temperature
LTC6102: Supply Current vs
Supply Voltage Step Response 0mV to 10mV
Step Response 10mV to 20mV
LTC6102HV: Supply Current vs
Supply Voltage
Step Response 100mV
100000
10
100
1000
10000
TEMPERATURE (°C)
–40 40 80 120100–20
6102 G10
020 60
BIAS CURRENT (pA)
VS = 100V
VS = 60V
VS = 12V
VS = 6V
VS = 5V
600
500
400
300
200
100
0
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (μA)
32
6102 G11
816 485624 4028412 445220 36 60
VIN = 0
RIN = 2M
TA = 125°C
TA = 85°CTA = 70°C
TA = 25°C
TA = –40°CTA = 0°C
600
500
400
300
200
100
0
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (μA)
32
6102 G12
8 16 4856647280889624 40
VIN = 0
RIN = 2M
TA = 125°C
TA = –40°C
TA = 70°C
TA = 85°C
TA = 25°C
TA = 0°C
V+
V+– 10mV
0.5V
0V
TIME (10μs/DIV)
6102 G13
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
VSENSE+ = V+
VSENSE–
VOUT
V+ – 10mV
V+ – 20mV
1V
0.5V
6102 G14
TIME (10μs/DIV)
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
VSENSE+ = V+
VSENSE–
VOUT
V+
V+ – 100mV
5V
0V
6102 G15
CLOAD = 1000pF
CLOAD = 10pF
TIME (10μs/DIV)
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
VSENSE+ = V+
VSENSE–
VOUT
Step Response Rising Edge
5.5V
5V
0.5V
0V
TIME (500ns/DIV)
6102 G17
VOUT
VSENSE– = 100mV
IOUT = 100μA
IOUT = 0
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
VSENSE+ = V+
LTC6102
LTC6102-1/LTC6102HV
8
6102fc
TYPICAL PERFORMANCE CHARACTERISTICS
Step Response Falling Edge PSRR vs Frequency
5.5V
5V
0.5V
0V
6102 G18
VOUT
VSENSE– = 100mV
IOUT = 100μA
IOUT = 0
TIME (500ns/DIV)
TA = 25°C
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
VSENSE+ = V+
FREQUENCY (Hz)
PSRR (dB)
0.1 1 10 100 1k 10k 100k 1M
6102 G19
160
140
120
100
80
60
40
20
V+ = 12V
RIN = 100Ω
ROUT = 4.99k
AV = 49.9
IOUT = 500μA
Input Referred Noise
0.1Hz to 10Hz
Noise Spectral Density
6102 G20
TA = 25°C
V+ = 12V
RIN = 10Ω
ROUT = 1k
VSENSE = 2mV
TIME (s)
NOISE (μV)
012345678910
5
4
3
2
1
0
–5
–4
–3
–2
–1
VOLTAGE NOISE DENSITY (μV/√Hz)
FREQUENCY (Hz)
100
2
1
01k 10k 1M100k
6102 G21
LTC6102-1: Supply Current vs
Supply Voltage
LTC6102-1: Supply Current vs
Supply Voltage when Disabled
LTC6102-1: Supply Current vs
Enable Voltage
LTC6102-1: Enable Pin Current vs
Enable Voltage
VOLTAGE SUPPLY (V)
0
300
400
600
30 50
6102 G22
200
100
10 20 40 60 70
0
–100
500
SUPPLY CURRENT (μA)
VEN = 2V
VSENSE = –0.1V
TA = 125°C
TA = –40°C
TA = 85°C
TA = 25°C
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (μA)
10
14
18
40
6102 G23
6
2
8
12
16
4
0
–2 10 20 30 50 7060
TA = 125°C
TA = –40°C
TA = 25°C
TA = 85°C
VEN = 0.8V
ENABLE VOLTAGE (V)
0
SUPPLY CURRENT (μA)
250
350
450
8
6102 G24
150
50
200
300
400
100
0
–50 21 43 67 9
510
TA = 25°C
VSENSE = 0V
V+ = 60V
V+ = 12V
TURN OFF (12V)
ENABLE VOLTAGE (V)
0
0
–1
ENABLE PIN CURRENT (μA)
1
3
4
5
157
6102 G25
2
6
4910
2368
TA = 25°C
V+ = 12V
LTC6102
LTC6102-1/LTC6102HV
9
6102fc
–INS (Pin 1): Amplifi er Inverting Input. When tied to –INF,
the internal sense amplifi er will drive –INS to the same
potential as +IN.
–INF (Pin 2): Force Input. This pin carries the input
current from RIN and must be tied to –INS near RIN. A
resistor (RIN) tied from V+ to –INF sets the output current
IOUT = VSENSE/RIN. VSENSE is the voltage across the ex-
ternal RSENSE.
V– (Pin 3, LTC6102/LTC6102HV Only): Negative Supply.
EN (Pin 3, LTC6102-1 Only): Enable Pin, Referenced to
the Negative Supply. When the enable pin is pulled high,
the LTC6102-1 is active. When the enable pin is pulled low
or left fl oating, the LTC6102-1 is disabled.
OUT (Pin 4): Open-Drain Current output. OUT will source
a current that is proportional to the sense voltage into
an external resistor. IOUT is the same current that enters
–INF.
V– (Pin 5): Negative Supply.
VREG (Pin 6): Internal Regulated Supply. A 0.1μF (or
larger) capacitor should be tied from VREG to V+. VREG is
not designed to drive external circuits.
V+ (Pin 7): Positive Supply. Supply current is drawn
through this pin.
+IN (Pin 8): Amplifi er Noninverting Input. Must be tied
to the system load end of the sense resistor. The +IN pin
has an internal 5k series resistor designed to allow large
input voltage transients or accidental disconnection of the
sense resistor. This pin can be held up to 20V below the
–INS pin indefi nitely, or up to 60V below the –INS pin for
up to one second (see Absolute Maximum Ratings).
Exposed Pad (Pin 9, DFN Only): V–. The Exposed Pad
must be soldered to PCB.
PIN FUNCTIONS
LTC6102-1: Turn-On Time LTC6102-1: Turn-Off Time
TYPICAL PERFORMANCE CHARACTERISTICS
TIME (μs)
–200
–1
VOLTAGE (V)
0
2
3
4
400 600
8
6102 G26
1
0 200 800
EN
5
6
7
OUT
TA = 25°C
V+ = 12V
VSENSE = 1mV
TIME (μs)
–20
–0.5
VOLTAGE (V)
0
1.0
1.5
2.0
10 20
4.0
6102 G27
0.5
–10 0
–15 15 25
–5 5 30
2.5
3.0
3.5
OUT
TA = 25°C
V+ = 12V
VSENSE = 1mV
EN
LTC6102
LTC6102-1/LTC6102HV
10
6102fc
BLOCK DIAGRAM
Figure 1. Block Diagram and Typical Connection
–
+
V+VREG
0.1μF
V–
V–
EN*
VENABLE
OUT
*LTC6102-1 ONLY 6102 BD
IOUT
ROUT
RIN
RSENSE
VSENSE
ILOAD
VBATTERY
L
O
A
D
VOUT = VSENSE • ROUT
RIN
5k
5k
10V 5V
10V 5V
–INS
–INF
+IN
+
–
LTC6102
LTC6102-1/LTC6102HV
11
6102fc
The LTC6102 high side current sense amplifi er (Figure 1)
provides accurate monitoring of current through a user-
selected sense resistor. The sense voltage is amplifi ed by
a user-selected gain and level shifted from the positive
power supply to a ground-referred output. The output
signal is analog and may be used as is or processed with
an output fi lter.
Theory of Operation
An internal sense amplifi er loop forces –INS to have the
same potential as +IN. Connecting an external resistor,
RIN, between –INS and V+ forces a potential across RIN
that is the same as the sense voltage across RSENSE. A
corresponding current, VSENSE/RIN, will fl ow through RIN.
The high impedance inputs of the sense amplifi er will not
conduct this input current, so it will fl ow through the –INF
pin and an internal MOSFET to the output pin.
The output current can be transformed into a voltage by
adding a resistor from OUT to V–. The output voltage is
then VO = V– + IOUT • ROUT
.
Useful Gain Confi gurations
GAIN RIN ROUT VSENSE AT VOUT = 5V
200 49.9Ω 10k 25mV
500 20Ω 10k 10mV
1000 10Ω 10k 5mV
4990 1Ω 4.99k 1mV
Selection of External Current Sense Resistor
The external sense resistor, RSENSE, has a signifi cant effect
on the function of a current sensing system and must be
chosen with care.
First, the power dissipation in the resistor should be
considered. The system load current will cause both heat
dissipation and voltage loss in RSENSE. As a result, the sense
resistor should be as small as possible while still providing
the input dynamic range required by the measurement.
Note that input dynamic range is the difference between
the maximum input signal and the minimum accurately
reproduced signal, and is limited primarily by input DC
offset of the internal amplifi er of the LTC6102. In addition,
RSENSE must be small enough that VSENSE does not exceed
APPLICATIONS INFORMATION
the maximum sense voltage specifi ed by the LTC6102 or
the sense resistor, even under peak load conditions. As
an example, an application may require that the maximum
sense voltage be 100mV. If this application is expected
to draw 20A at peak load, RSENSE should be no more
than 5mΩ.
Once the maximum RSENSE value is determined, the
minimum sense resistor value will be set by the resolu-
tion or dynamic range required. The minimum signal
that can be accurately represented by this sense amp is
limited by the input offset. As an example, the LTC6102
has a typical input offset of 3μV. If the minimum current
is 1mA, a sense resistor of 3mΩ will set VSENSE to 3μV.
This is the same value as the input offset. A larger sense
resistor will reduce the error due to offset by increasing
the sense voltage for a given load current.
For this example, choosing a 5mΩ RSENSE will maximize
the dynamic range and provide a system that has 100mV
across the sense resistor at peak load (20A), while input
offset causes an error equivalent to only 0.6mA of load
current.
Peak dissipation is 2W. If a 0.5mΩ sense resistor is em-
ployed, then the effective current error is 6mA (0.03%
of full-scale), while the peak sense voltage is reduced to
10mV at 20A, dissipating only 200mW.
The low offset and corresponding large dynamic range of
the LTC6102 make it more fl exible than other solutions
in this respect. The 3μV typical offset gives 100dB of dy-
namic range for a sense voltage that is limited to 300mV
max, and over 116dB of dynamic range if a maximum of
2V is allowed.
The previous example assumes that a large output dynamic
range is required. For circuits that do not require large
dynamic range, the wide input range of the LTC6102 may
be used to reduce the size of the sense resistor, reducing
power loss and increasing reliability. For example, in a
100A circuit requiring 60dB of dynamic range, the input
offset and drift of most current-sense solutions will require
that the shunt be chosen so that the sense voltage is at
least 100mV at full scale so that the minimum input is
greater than 100μV. This will cause power dissipation in
excess of 10W at full scale! That much power loss can put
LTC6102
LTC6102-1/LTC6102HV
12
6102fc
Dynamic Range vs Maximum
Power Dissipation in RSENSE
APPLICATIONS INFORMATION
a signifi cant load on the power supply and create thermal
design headaches. In addition, heating in the sense resistor
can reduce its accuracy and reliability.
In contrast, the large dynamic range of the LTC6102 allows
the use of a much smaller sense resistor. The LTC6102
allows the minimum sense voltage to be reduced to less
than 10μV. The peak sense voltage would then be 10mV,
dissipating only 1W at 100A in a 100μΩ sense resistor!
With a specialized sense resistor, the same system would
allow peak currents of more than 1000A without exceeding
the input range of the LTC6102 or damaging the shunt.
Figure 2. Kelvin Input Connection Preserves Accuracy
with Large Load Current and Large Output Current
LTC6102
ROUT
VOUT
6102 F02
RIN–
V+
LOAD
RSENSE RIN+
–
+
V+
–INF
V–
OUT
VREG 0.1μF
TIE AS CLOSE TO RIN AS POSSIBLE
–INS+IN
LOADV+
V–
OUTPUT
RSENSE*
ROUT LTC6102
RIN–RIN+
CREG
*VISHAY VCS1625 SERIES
WITH 4 PAD KELVIN CONNECTION
V–
high-current paths, this error can be reduced by orders of
magnitude. A sense resistor with integrated Kelvin sense
terminals will give the best results. Figure 2 illustrates the
recommended method. Note that the LTC6102 has a Kelvin
input structure such that current fl ows into –INF. The –INS
and –INF pins should be tied as close as possible to RIN.
This reduces the parasitic series resistance so that RIN
may be as low as 1Ω, allowing high gain settings to be
used with very little gain error.
Sense Resistor Connection
Kelvin connection of +IN and –INS to the sense resistor
should be used in all but the lowest power applications.
Solder connections and PC board interconnections that
carry high current can cause signifi cant error in measure-
ment due to their relatively large resistances. One 10mm
× 10mm square trace of one-ounce copper is approxi-
mately 0.5mΩ. A 1mV error can be caused by as little
as 2A fl owing through this small interconnect. This will
cause a 1% error in a 100mV signal. A 10A load current
in the same interconnect will cause a 5% error for the
same 100mV signal. An additional error is caused by the
change in copper resistance over temperature, which is in
excess of 0.4%/°C. By isolating the sense traces from the
Selection of External Input Resistor, RIN
The external input resistor, RIN, controls the transconduc-
tance of the current sense circuit, IOUT = VSENSE/RIN. For
example, if RIN = 100, then IOUT = VSENSE/100 or IOUT =
1mA for VSENSE = 100mV.
RIN should be chosen to provide the required resolution
while limiting the output current. At low supply voltage,
IOUT may be as much as 1mA. By setting RIN such that
MAXIMUM POWER DISSIPATION (W)
DYNAMIC RANGE (dB)
110
100
90
80
70
60
50
40
30
20
6102 AI01
0.001 0.01 0.1 1 10 100
MAX ISENSE = 1A
MAX ISENSE = 10A
MAX ISENSE = 100A
DYNAMIC RANGE RELATIVE
TO 10μV, MINIMUM VSENSE
RSENSE = 10mΩRSENSE = 100mΩ
100dB: MAX
VSENSE = 1V
40dB: MAX
VSENSE = 1mV
RSENSE = 10μΩ
RSENSE = 100μΩ
RSENSE = 1Ω
RSENSE = 1mΩ
LTC6102
LTC6102-1/LTC6102HV
13
6102fc
the largest expected sense voltage gives IOUT = 1mA, then
the maximum output dynamic range is available. Output
dynamic range is limited by both the maximum allowed
output current (Note 1) and the maximum allowed output
voltage, as well as the minimum practical output signal. If
less dynamic range is required, then RIN can be increased
accordingly, reducing the output current and power dis-
sipation. If small sense currents must be resolved ac-
curately in a system that has very wide dynamic range, a
smaller RIN may be used if the max current is limited in
another way, such as with a Schottky diode across RSENSE
(Figure 3). This will reduce the high current measurement
accuracy by limiting the result, while increasing the low
current measurement resolution. This approach can be
helpful in cases where occasional large burst currents
may be ignored.
APPLICATIONS INFORMATION
the LTC6102, and into ROUT via the OUT pin. In order to
minimize gain error, –INS should be routed in a separate
path from –INF to a point as close to RIN as possible. In
addition, the higher potential terminal of RIN should be
connected directly to the positive terminal of RSENSE (or
any input voltage source). For the highest accuracy, RIN
should be a four-terminal resistor if it is less than 10Ω.
Selection of External Output Resistor, ROUT
The output resistor, ROUT
, determines how the output cur-
rent is converted to voltage. VOUT is simply IOUT • ROUT
.
In choosing an output resistor, the max output voltage
must fi rst be considered. If the circuit that is driven by the
output does not have a limited input voltage, then ROUT
must be chosen such that the max output voltage does
not exceed the LTC6102 max output voltage rating. If the
following circuit is a buffer or ADC with limited input range,
then ROUT must be chosen so that IOUT(MAX) • ROUT is less
than the allowed maximum input range of this circuit.
In addition, the output impedance is determined by ROUT
. If
the circuit to be driven has high enough input impedance,
then almost any output impedance will be acceptable.
However, if the driven circuit has relatively low input imped-
ance, or draws spikes of current, such as an ADC might
do, then a lower ROUT value may be required in order to
preserve the accuracy of the output. As an example, if the
input impedance of the driven circuit is 100 times ROUT
,
then the accuracy of VOUT will be reduced by 1% since:
VIRR
RR
OUT OUT
OUT IN DRIVEN
OUT IN DRIVEN
=
+
=
••()
()
IIR IR
OUT OUT OUT OUT
•• .••
100
101 099=
Error Sources
The current sense system uses an amplifi er and resistors
to apply gain and level shift the result. The output is then
dependent on the characteristics of the amplifi er, such as
gain and input offset, as well as resistor matching.
Figure 3. Shunt Diode Limits Maximum Input Voltage to Allow
Better Low Input Resolution Without Overranging
V+
LOAD
DSENSE
6102 F03
RSENSE
Care should be taken when designing the PC board lay-
out for RIN, especially for small RIN values. All trace and
interconnect impedances will increase the effective RIN
value, causing a gain error. It is important to note that the
large temperature drift of copper resistance will cause a
change in gain over temperature if proper care is not taken
to reduce this effect.
To further limit the effect of trace resistance on gain,
maximizing the accuracy of these circuits, the LTC6102 has
been designed with a Kelvin input. The inverting terminal
(–INS) is separate from the feedback path (–INF). During
operation, these two pins must be connected together.
The design of the LTC6102 is such that current into –INS
is input bias current only, which is typically 60pA at 25°C.
Almost all of the current from RIN fl ows into –INF, through
LTC6102
LTC6102-1/LTC6102HV
14
6102fc
Figure 5. Second Input R Minimizes
Error Due to Input Bias Current
–INF
VREG 0.1μF
–INS
6102 F05
RIN+=RIN––RSENSE
LTC6102
ROUT
VOUT
V+
LOAD
RSENSE
–
+
V+
V–
OUT
+IN
RIN–
RIN+
APPLICATIONS INFORMATION
For instance if IBIAS is 1nA and ROUT is 10k, the output
error is –10μV.
Note that in applications where RSENSE ≈ RIN, IB(+) causes
a voltage offset in RSENSE that cancels the error due to
IB(–) and EOUT(IBIAS) ≈ 0. In applications where RSENSE <
RIN, the bias current error can be similarly reduced if an
external resistor RIN(+) = (RIN – RSENSE) is connected as
shown in Figure 5. Under both conditions:
E
OUT(IBIAS) = ± ROUT • IOS; IOS = IB(+) – IB(–)
Adding RIN+ as described will maximize the dynamic
range of the circuit. For less sensitive designs, RIN+ is
not necessary.
Ideally, the circuit output is:
VV R
RVRI
OUT SENSE OUT
IN SENSE SENSE SENSE
==•; •
In this case, the only error is due to resistor mismatch,
which provides an error in gain only.
Output Error, EOUT
, Due to the Amplifi er DC Offset
Voltage, VOS
E
OUT(VOS) = VOS • (ROUT/RIN)
The DC offset voltage of the amplifi er adds directly to
the value of the sense voltage, VSENSE. This error is very
small (3μV typ) and may be ignored for reasonable values
of RIN. See Figure 4. For very high dynamic range, this
offset can be calibrated in the system due to its extremely
low drift.
INPUT VOLTAGE (V)
OUTPUT ERROR (%)
100
10
1
0.1
0.01
0.001
0.0001
6102 F04
0.00001 0.0001 0.001 0.01 0.1 1
FOR A 500M7 SHUNT
VIN = 100mV, ISHUNT = 200A
ERROR DUE TO VOS IS 6mA
VIN = 10MV
Figure 4. LTC6102 Output Error Due to Typical Input Offset
vs Input Voltage
Output Error, EOUT
, Due to the Bias Currents,
IB(+) and IB(–)
The input bias current of the LTC6102 is vanishingly small.
However, for very high resolution, or at high temperatures
where IB increases due to leakage, the current may be
signifi cant.
The bias current IB(+) fl ows into the positive input of the
internal op amp. IB(–) fl ows into the negative input.
E
OUT(IBIAS) = ROUT((IB(+) • (RSENSE/RIN) – IB(–))
Since IB(+) ≈ IB(–) = IBIAS, if RSENSE << RIN then,
E
OUT(IBIAS) ≈ –ROUT • IBIAS
Clock Feedthrough, Input Bias Current
The LTC6102 uses auto-zeroing circuitry to achieve an
almost zero DC offset over temperature, sense voltage,
and power supply voltage. The frequency of the clock
used for auto-zeroing is typically 10kHz. The term clock
feedthrough is broadly used to indicate visibility of this
clock frequency in the op amp output spectrum. There are
typically two types of clock feedthrough in auto zeroed
amps like the LTC6102.
The fi rst form of clock feedthrough is caused by the
settling of the internal sampling capacitor and is input
referred; that is, it is multiplied by the internal loop gain
LTC6102
LTC6102-1/LTC6102HV
15
6102fc
of the amp. This form of clock feedthrough is indepen-
dent of the magnitude of the input source resistance or
the magnitude of the gain setting resistors. The LTC6102
has a residue clock feedthrough of less then 1μVRMS input
referred at 10kHz.
The second form of clock feedthrough is caused by the
small amount of charge injection occurring during the
sampling and holding of the amp’s input offset voltage.
The current spikes are multiplied by the impedance seen
at the input terminals of the amp, appearing at the output
multiplied by the internal loop gain of the internal op amp.
To reduce this form of clock feedthrough, use smaller
valued gain setting resistors and minimize the source
resistance at the input.
Input bias current is defi ned as the DC current into the
input pins of the op amp. The same current spikes that
cause the second form of clock feedthrough described
above, when averaged, dominate the DC input bias current
of the op amp below 70°C.
As temperature increases, the leakage of the ESD protec-
tion diodes on the inputs increases the input bias currents
of both inputs in the positive direction, while the current
caused by the charge injection stays relatively constant. At
temperatures above 70°C, the leakage current dominates
and both the negative and positive pins’ input bias currents
are in the positive direction (into the pins).
Output Current Limitations Due to Power Dissipation
The LTC6102 can deliver more than 1mA continuous cur-
rent to the output pin. This current fl ows through RIN and
enters the current sense amp via the –INF pin. The power
dissipated in the LTC6102 due to the output current is:
P
OUT = (V–INF – VOUT) • IOUT
Since V–INF ≈ V+, POUT ≈ (V+ – VOUT) • IOUT
There is also power dissipated due to the quiescent sup-
ply current:
P
Q = IS • V+
The total power dissipated is the output current dissipation
plus the quiescent dissipation:
P
TOTAL = POUT + PQ
APPLICATIONS INFORMATION
At maximum supply and maximum output current, the
total power dissipation can exceed 100mW. This will
cause signifi cant heating of the LTC6102 die. In order to
prevent damage to the LTC6102, the maximum expected
dissipation in each application should be calculated. This
number can be multiplied by the θJA value listed in the
package section on page 2 to fi nd the maximum expected
die temperature. This must not be allowed to exceed 150°C
or performance may be degraded.
As an example, if an LTC6102 in the MSOP package is to
be biased at 55V ±5V supply with 1mA output current at
80°C:
P
Q(MAX) = IDD(MAX) • V+(MAX) = 39mW
P
OUT(MAX) = IOUT • V+(MAX) = 60mW
T
RISE = θJA • PTOTAL(MAX)
T
MAX = TAMBIENT + TRISE
T
MAX must be < 125°C
P
TOTAL(MAX) ≈ 99mW and the max die temp
will be 100°C
If this same circuit must run at 125°C, the max die temp
will increase to 145°C. (Note that supply current, and
therefore PQ, is proportional to temperature. Refer to
Typical Performance Characteristics section.) Note that
the DD package has a smaller θJA than the MSOP pack-
age, which will substantially reduce the die temperature
at similar power levels.
The LTC6102HV can be used at voltages up to 105V. This
additional voltage requires that more power be dissipated
for a given level of current. This will further limit the allowed
output current at high ambient temperatures.
It is important to note that the LTC6102 has been designed
to provide at least 1mA to the output when required, and
can deliver more depending on the conditions. Care must
be taken to limit the maximum output current by proper
choice of sense and input resistors and, if input fault
conditions are likely, an external clamp.
LTC6102
LTC6102-1/LTC6102HV
16
6102fc
Figure 6. V+ Powered Separately from Load Supply (VBAT)
6102 F06
LTC6102
ROUT
VOUT
RIN
VBAT
LOAD
(V+ – 2V) TO V+
RSENSE
V+
V–
OUT
+IN
V+
–INF
–INS
VREG 0.1μF
–
+
APPLICATIONS INFORMATION
Output Filtering
The output voltage, VOUT
, is simply IOUT • ZOUT
. This
makes fi ltering straightforward. Any circuit may be used
which generates the required ZOUT to get the desired fi lter
response. For example, a capacitor in parallel with ROUT
will give a low pass response. This will reduce unwanted
noise from the output, and may also be useful as a charge
reservoir to keep the output steady while driving a switch-
ing circuit such as a mux or ADC. This output capacitor
in parallel with an output resistor will create a pole in the
output response at:
fRC
dB OUT OUT
–•• •
3
1
2
=
π
Useful Equations
Input Voltage: V
Voltage
SENSE =IR
SENSE SENSE
•
GGain: V
V
Current Gain: I
I
OUT
SENSE
OUT
S
=R
R
OUT
IN
EENSE
OUT
SENSE
Transconductance: I
V
=
=
R
R
SENSE
IN
11
R
RR
R
IN
SENSE OUT
Transimpedance: V
I
OUT
SENSE
=•
IIN
Input Sense Range
The inputs of the LTC6102 can function from V+ to (V+ – 2V).
Not only does this allow a wide VSENSE range, it also allows
the input reference to be separate from the positive supply
(Figure 6). Note that the difference between VBAT and V+
must be no more than the input sense voltage range listed
in the Electrical Characteristics table.
Monitoring Voltages Above V+ and Level Translation
The LTC6102 may be confi gured to monitor voltages that are
higher than its supply, provided that the negative terminal
of the input voltage is within the input sense range of the
LTC6102. Figure 7 illustrates a circuit in which the LTC6102
has its supply pin tied to the lower potential terminal of the
sense resistor instead of the higher potential terminal. The
Figure 7. LTC6102 Supply Current Monitored with Load
–INF
–INS
LTC6102
ROUT
VOUT
6102 F07
RIN
LOAD
VBAT
RSENSE
V+
V–
OUT
+IN
VREG 0.1MF
–
+
operation of the LTC6102 is such that the –INS and –INF
pins will servo to within a few microvolts of +IN, which is
shorted to V+. Since the input sense range of the LTC6102
includes V+, the circuit will operate properly. The voltage
across RSENSE will be held across RIN by the LTC6102,
causing current VSENSE/RIN to fl ow to ROUT
. In this case,
the supply current of the LTC6102 is also monitored, as
it fl ows through RSENSE.
Because the voltage across RSENSE is not restricted to
the sense range of the LTC6102 in this circuit, VSENSE
can be large compared to the allowed sense voltage. This
facilitates the sensing of very large voltages, provided
that RIN is chosen so that VSENSE/RIN does not exceed
LTC6102
LTC6102-1/LTC6102HV
17
6102fc
Figure 10. Additional Resistor R3 Protects
Output During Supply Reversal
APPLICATIONS INFORMATION
6102 F10
LTC6102
R2
4.99k
D1
R1
100Ω
RSENSE
–+
V+
V–
OUT
+IN
VBATT
R3
1k
–INF
–INS
VREG 0.1μF
L
O
A
D
ADC
the allowed output current. The gain is still controlled by
ROUT/RIN, so either gain or attenuation may be applied to
the input signal as it is translated to the output. Finally,
the input may be a voltage source rather than a sense
resistor, as shown in Figure 8. This circuit allows the
translation of a wide variety of input signals across the
entire supply range of the LTC6102 with only a tiny offset
error while retaining simple gain control set by ROUT/RIN.
Again, very large voltages may be sensed as long as RIN
is chosen so that IOUT does not exceed the allowed output
current. For example, VIN may be as large as 1V with RIN =
1k, or as large as 10V with RIN = 10k. For a 10V maximum
input and a 5V maximum output, RIN = 10k and ROUT = 5k
will allow the LTC6102HV to translate VIN to VOUT with a
common mode voltage of up to 100V. For the case where
a large input resistor is used, a similar resistor in series
with +IN will reduce error due to input bias current.
Figure 8. Voltage Level-Shift Circuit
Figure 9. Schottky Prevents Damage During Supply Reversal
–INF
–INS
LTC6102
ROUT
VOUT
6102 F08
RIN
VIN
VCM
V+
V+
V–
OUT
+IN
VREG 0.1μF
–
+
VOUT = VIN • ROUT
RIN
6102 F09
LTC6102
R2
4.99k
D1
R1
100Ω
VBATT
RSENSE
V+
V–
–INF
OUT
–INS+IN
VREG 0.1μF
L
O
A
D
–+
Reverse Supply Current
Some applications may be tested with reverse-polarity
supplies due to an expectation of this type of fault during
operation. The LTC6102 is not protected internally from
external reversal of supply polarity. To prevent damage
that may occur during this condition, a Schottky diode
should be added in series with V– (Figure 9). This will
limit the reverse current through the LTC6102. Note that
this diode will limit the low voltage performance of the
LTC6102 by effectively reducing the supply voltage to the
part by VD.
In addition, if the output of the LTC6102 is wired to a device
that will effectively short it to high voltage (such as through
an ESD protection clamp) during a reverse supply condi-
tion, the LTC6102’s output should be connected through
a resistor or Schottky diode (Figure 10).
Response Time
The LTC6102 is designed to exhibit fast response to inputs
for the purpose of circuit protection or signal transmission.
This response time will be affected by the external circuit
in two ways, delay and speed.
LTC6102
LTC6102-1/LTC6102HV
18
6102fc
APPLICATIONS INFORMATION
If the output current is very low and an input transient
occurs, there may be a delay before the output voltage
begins changing. This can be reduced by increasing the
minimum output current, either by increasing RSENSE or
decreasing RIN. The effect of increased output current
is illustrated in the step response curves in the Typical
Performance Characteristics section of this datasheet.
Note that the curves are labeled with respect to the initial
output currents.
The speed is also affected by the external circuit. In this
case, if the input changes very quickly, the internal ampli-
fi er will slew the gate of the internal output FET (Figure 1)
in order to close the internal loop. This results in current
fl owing through RIN and the internal FET. This current slew
rate will be determined by the amplifi er and FET charac-
teristics as well as the input resistor, RIN. Using a smaller
RIN will allow the output current to increase more quickly,
decreasing the response time at the output. This will also
have the effect of increasing the maximum output current.
Using a larger ROUT will also decrease the response time,
since VOUT = IOUT • ROUT
. Reducing RIN and increasing
ROUT will both have the effect of increasing the voltage
gain of the circuit.
Bandwidth
For applications that require higher bandwidth from the
LTC6102, care must be taken in choosing RIN. For a gen-
eral-purpose op-amp, the gain-bandwidth product is used
to determine the speed at a given gain. Gain is determined
by external resistors, and the gain-bandwidth product is
an intrinsic property of the amplifi er. The same is true
for the LTC6102, except that the feedback resistance is
determined by an internal FET characteristic. The feedback
impedance is approximately 1/gm of the internal MOSFET.
The impedance is reduced as current into –INF is increased.
At 1mA, the impedance of the MOSFET is on the order of
10kΩ. RIN sets the closed-loop gain of the internal loop
as 1/(RIN • gm). The bandwidth is then limited to GBW •
(RIN • gm), with a maximum bandwidth of around 2MHz.
This is illustrated in the characteristic curves, where gain
vs frequency for two input conditions is shown. The exact
impedance of the MOSFET is diffi cult to determine, as it
is a function of input current, process, and capacitance,
and has a very different characteristic for low currents
vs high currents. However, it is clear that smaller values
of RIN and smaller values of IOUT will generally result in
lower closed-loop bandwidth. VSENSE and RIN should be
chosen to maximize both IOUT and closed-loop gain for
highest speed. Theoretically, maximum bandwidth would
be achieved for the case where VIN = 10VDC and RIN = 10k,
giving IOUT = 1mA and a closed-loop gain near 1. However,
this may not be possible in a practical application. Note
that the MOSFET gm is determined by the average or DC
value of IOUT
, not the peak value. Adding DC current to a
small AC input will help increase the bandwidth.
VREG Bypassing
The LTC6102 has an internally regulated supply near V+
for internal bias. It is not intended for use as a supply or
bias pin for external circuitry. A 0.1μF capacitor should be
connected between the VREG and V+ pins. This capacitor
should be located very near to the LTC6102 for the best
performance. In applications which have large supply tran-
sients, a 6.8V zener diode may be used in parallel with this
bypass capacitor for additional transient suppression.
Enable Pin Operation
The LTC6102-1 includes an enable pin which can place
the part into a low power disable state. The enable pin is a
logic input pin referenced to V– and accepts standard TTL
logic levels regardless of the V+ voltage. When the enable
pin is driven high, the part is active. When the enable pin is
fl oating or pulled low, then the part is disabled and draws
very little supply current. When driven high, the enable pin
draws a few microamps of input bias current.
If there is no external logic supply available, the enable
pin can be pulled to the V+ supply through a large value
resistor. The voltage at the enable pin will be clamped
by the built-in ESD protection structure (which acts like
a zener diode). The resistor should be sized so that the
current through the resistor is a few milliamps or less to
prevent any reduction in long-term reliability. For practi-
cal purposes, the current through the resistor should be
minimized to save power. The resistor value is limited
by the input bias current requirements of the enable
LTC6102
LTC6102-1/LTC6102HV
19
6102fc
APPLICATIONS INFORMATION
–INF
VREG 0.1μF
–INS
6102 F11
RIN+=RIN––RSENSE
LTC6102-1
ROUT
VOUT
V+
LOAD
RBIAS
2.7M
RSENSE
V+
V–
OUT
+IN
EN
RIN–
RIN+
–
+
Figure 11
Figure 12. LTC6102-1 VREG Voltage During
Bypass Capacitor Discharge when Disabled
pin. Figure 11 shows the LTC6102-1 with a 2.7M pull-up
resistor to limit the current to less than 20μA with a 60V
supply, which is enough to satisfy the input bias current
requirement.
Start-Up Current
The start-up current of the LTC6102 when the part is
powered on or enabled (LTC6102-1) consists of three
parts: the fi rst is the current necessary to charge the
VREG bypass capacitor, which is nominally 0.1μF. Since the
VREG voltage charges to approximately 4.5V below the V+
voltage, this can require a signifi cant amount of start-up
current. The second source is the active supply current of
the LTC6102 amplifi er, which is not signifi cantly greater
during start-up than during normal operation. The third
source is the output current of the LTC6102, which upon
start-up may temporarily drive the output high. This could
cause milliamps of output current (limited mostly by the
input resistor RIN) to fl ow into the output resistor and/or
the output limiting ESD structure in the LTC6102. This is
a temporary condition which will cease when the LTC6102
amplifi er settles into normal closed-loop operation.
When the LTC6102-1 is disabled, the internal amplifi er is
also shut down, which means that the discharge rate of
the 0.1μF capacitor is very low. This is signifi cant when the
LTC6102-1 is disabled to save power, because the recharg-
ing of the 0.1μF capacitor is a signifi cant portion of the
overall power consumed in startup. Figure 12 shows the
discharge rate of the 0.1μF capacitor after the LTC6102-1
is shut down at room temperature.
In a system where the LTC6102-1 is disabled for short
periods, the start-up power (and therefore the average
power) can be reduced since the VREG bypass capacitor
is never signifi cantly discharged. The time required to
charge the VREG capacitor will also be reduced, allowing
the LTC6102-1 to start-up more quickly.
TIME (ms)
–2
0
ENABLE VOLTAGE (V)
VREG VOLTAGE (V)
0.25
0.75
1.00
1.25
10
2.25
6102 F12
0.50
4
012
6
214
816
1.50
1.75
2.00
7.4
7.5
7.7
7.8
7.9
8.3
7.6
8.0
8.1
8.2
VREG
EN
TA = 25°C
V+ = 12V
LTC6102
LTC6102-1/LTC6102HV
20
6102fc
Bidirectional Current Sense Circuit with Separate Charge/Discharge Output
LTC6102 Monitors Its Own Supply Current
TYPICAL APPLICATIONS
CHARGER
–+
–+
+
–
+
–
L
O
A
D
VOUT D = IDISCHARGE •RSENSE
( )
WHEN IDISCHARGE ≥ 0DISCHARGING: ROUT D
RIN D
VOUT C = ICHARGE •RSENSE
( )
WHEN ICHARGE ≥ 0CHARGING: ROUT C
RIN C
6102 TA02
VBATT
RIN D
100Ω
LTC6102
RIN C
100Ω
RIN D
100Ω
LTC6102
VOUT C
ROUT C
4.99k
ROUT D
4.99k
VOUT D
RIN C
100Ω
ICHARGE RSENSE IDISCHARGE
V+
V–
OUT
–INS+IN
V+V–
OUT
–INS +IN
–INF –INF
VREG 0.1μF VREG
0.1μF
L
O
A
D
–+
6102 TA03
R2
4.99k VOUT
R1
100
VBATT
RSENSE
LTC6102 +
–
VOUT = 49.9 •RSENSE (ILOAD + ISUPPLY)
ILOAD
ISUPPLY
V+
V–
OUT
–INS+IN
–INF
VREG 0.1μF
LTC6102
LTC6102-1/LTC6102HV
21
6102fc
16-Bit Resolution Unidirectional Output into LTC2433 ADC
Intelligent High-Side Switch with Current Monitor
TYPICAL APPLICATIONS
TO μP
6102 TA05
LTC2433-1
LTC6102-1
ROUT
4.99k
RIN
100Ω
VOUT
VSENSE
ILOAD
4V TO 60V
POWER ENABLE
1μF
5V
L
O
A
D
–+
–
+
VOUT = • VSENSE = 49.9VSENSE
ROUT
RIN
ADC FULL-SCALE = 2.5V
21
9
8
7
1063
4
5
VCC SCK
REF+
REF–GND
IN+
IN–CC
FO
SDD
V+
V–
EN
OUT
–INS+IN
–INF
VREG 0.1μF
6102 TA06
L
O
A
D
FAULT
OFF ON
15
4.99k
VO
RS
3
4
47k
2
8
6
100Ω
100Ω
1%
10μF
63V
1μF
14V
VLOGIC
SUB85N06-5
VO = 49.9 • RS • IL
FOR RS = 5mΩ,
VO = 2.5V AT IL = 10A (FULL SCALE)
LT1910 LTC6102
IL
V+
V–
OUT
–INS
–INF
+IN
VREG
0.1μF
LTC6102
LTC6102-1/LTC6102HV
22
6102fc
TYPICAL APPLICATIONS
Input Overvoltage Protection
Simple 500V Current Monitor
6102 TA08
LTC6102
RIN
100Ω
VOUT
ROUT
4.99k
L
O
A
D
–+
VOUT = • VSENSE = 49.9 VSENSE
ROUT
RIN
M1 AND M2 ARE FQD3P50 TM
M1
M2
51V
BZX884-C51
BAT46
2M
VSENSE RSENSE
ISENSE
+
–
DANGER! Lethal Potentials Present — Use Caution
DANGER!!
HIGH VOLTAGE!!
V+
V–
OUT
–INS+IN
500V
–INF
VREG 0.1μF
LTC6102
DZ: CENTRAL SEMICONDUCTOR
CMZ5931B 18V 1.5W ZENER DIODE 6102 TA07
RIN–
1k
3W
V+
LOAD
RSENSE
–
+
V+
–INF
V–
DZ
OUT
VREG 0.1μF
–INS+IN
ROUT
1k
LTC6102
LTC6102-1/LTC6102HV
23
6102fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.115
TYP
2.38 p0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN 1203
0.25 p 0.05
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)2.15 p0.05
0.50
BSC
0.675 p0.05
3.5 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 p 0.152
(.193 p .006)
8765
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
LTC6102
LTC6102-1/LTC6102HV
24
6102fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0209 REV C • PRINTED IN USA
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT
®
1636 Rail-to-Rail Input/Output, Micropower Op Amp VCM Extends 44V above VEE, 55μA Supply Current, Shutdown Function
LT1637/LT1638/
LT1639
Single/Dual/Quad, Rail-to-Rail, Micropower Op Amp VCM Extends 44V above VEE, 0.4V/μs Slew Rate, >1MHz Bandwidth, <250μA
Supply Current per Amplifi er
LT1787/LT1787HV Precision, Bidirectional, High Side Current Sense
Amplifi er
2.7V to 60V Operation, 75μV Offset, 60μA Current Draw
LTC1921 Dual –48V Supply and Fuse Monitor ±200V Transient Protection, Drives Three Optoisolators for Status
LT1990 High Voltage, Gain Selectable Difference Amplifi er ±250V Common Mode, Micropower, Pin Selectable Gain = 1, 10
LT1991 Precision, Gain Selectable Difference Amplifi er 2.7V to ±18V, Micropower, Pin Selectable Gain = –13 to 14
LTC2050/LTC2051/
LTC2052
Single/Dual/Quad Zero-Drift Op Amp 3μV Offset, 30nV/°C Drift, Input Extends Down to V–
LTC4150 Coulomb Counter/Battery Gas Gauge Indicates Charge Quantity and Polarity
LT6100 Gain-Selectable High Side Current Sense Amplifi er 4.1V to 48V Operation, Pin-Selectable Gain: 10, 12.5, 20, 25, 40, 50V/V
LTC6101/
LTC6101HV
High Voltage High Side Current Sense Amplifi er in
SOT-23
4V to 60V/5V to 100V Operation, External Resistor Set Gain
LTC6103 Dual High Side Precision Current Sense Amplifi er 4V to 60V, Gain Confi gurable, 8-Pin MSOP
LTC6104 Bidirectional High Side Precision Current Sense
Amplifi er
4V to 60V, Gain Confi gurable, 8-Pin MSOP
LT6105 Precision Rail-to-Rail Input Current Sense Amplifi er Input VCM Extends 44V Above and 0.3V Below V–, 2.85V to 36V Operation
LT6106 Low Cost, High Side Precision Current Sense
Amplifi er
2.7V to 36V, Gain Confi gurable, SOT23
LT6107 High Temperature High Side Current Sense Amplifi er
in SOT-23
2.7V to 36V, Fully Tested at –55°C and 150°C
Remote Current Sense with Simple Noise Filter
RELATED PARTS
LTC6102
6102 TA09
RIN–
V+
LOAD
RSENSE
–
+
V+
–INF
V–
OUT LONG WIRE
VREG 0.1μF
TIE AS CLOSE TO RIN AS POSSIBLE
–INS+IN
ROUT
ADC
fC = 1
2 • P • ROUT • COUT
REMOTE ADC
COUT
