5962F9655603QXX - Aeroflex Incorporated

UT54ACS164E/UT54ACTS164E

Radiation-Hardened

8-Bit Shift Registers

January, 2004

www.aeroflex.com/radhard

FEATURES

• AND-gated (enable/disable) serial inputs

• Fully buffered clock and serial inputs

• Direct clear

• 0.6µm CRH CMOS Process

- Latchup immune

• High speed

• Low power consumption

• Wide operating power supply from 3.0V to 5.5V

• Available QML Q or V processes

• 14-lead flatpack

DESCRIPTION

The UT54ACS164E and the UT54ACTS164E are 8-bit shift

registers which feature AND-gated serial inputs and an asyn-

chronous clear. The gated serial inputs (A and B) permit com-

plete control over incoming data. A low at either input inhibits

entry of new data and resets the first flip-flop to the low level

at the next clock pulse. A high-level at both serial inputs sets

the first flip-flop to the high level at the next clock pulse. Data

at the serial inputs may be changed wh ile the clock is high or

low , providing the minimum setup time requirements are met.

Clocking occurs on the low-to-high-level transition of the clock

input.

The devices are characterized over full military temperature

range of -55°C to +125°C.

PINOUT

14-Lead Flatpack

Top View

FUNCTION TABLE

Notes:

1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively , before the indicated

steady-state input conditions were established.

2. QAn and QGn = the level of QA or QG before the most recent ↑ transition of

the clock; indicates a one-bit shift.

LOGIC SYMBOL

VDD

CLR

CLK

VSS

INPUTS OUTPUTS

CLR CLK A B QAQB ... QH

L X X X L L L

H L X X QA0 QB0 QH0

H↑H H H QAn QGn

H↑L X L QAn QGn

H↑X L L QAn QGn

(9)

CLR (8)

CLK R

Note:

1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

(1)

A(2)

B(3) QA

SRG8

(4) QB

(5) QC

(6) QD

(10) QE

(11) QF

(12) QG

(13) QH

C1/

LOGIC DIAGRAM

RADIATION HARDNESS SPECIFICATIONS 1

Notes:

1. Logic will not latchup during radiation exposure within the limits defined in the table.

2. Device storage elements are immune to SEU affects.

ABSOLUTE MAXIMUM RATINGS

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at

these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

PARAMETER LIMIT UNITS

Total Dose 1.0E6 rads(Si)

SEU Threshold 280 MeV-cm2/mg

SEL Threshold 120 MeV-cm2/mg

Neutron Fluence 1.0E14 n/cm2

(8)

CLK

K K

QBQCQDQEQFQGQH

CLR (9)

(2)

(1)

SERIAL R

CCC C C CCC

(3) (4) (5) (6) (10) (11) (12) (13)

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage -0.3 to 7.0 V

VI/O Voltage any pin -.3 to VDD + .3 V

TSTG Storage Temperature range -65 to +150 °C

TJMaximum junction temperature +175 °C

TLS Lead temperature (soldering 5 seconds) +300 °C

ΘJC Thermal resistance junction to case 20 °C/W

IIDC input current ±10 mA

PDMaximum po wer d issipation 1 W

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage 3.0 to 5.5 V

VIN Input voltage any pin 0 to VDD V

TCTemperature range -55 to + 125 °C

DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E7

( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)

Notes:

1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,

as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed

to VIH(min) and VIL(max).

2. Supplied as a design limit but not guaranteed or tested.

3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz.

4. Not more than one output may be shorted at a time for maximum duration of one secon d.

5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at

frequency of 1MHz and a signal ampl itude of 50mV rms maximum.

6. Maximum allowable relative shift equals 50mV.

7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.

8. Power dissipation specified per switching output.

9. This value is guaranteed based on characterization data, but not tested.

SYMBOL Description CONDITION VDD MIN MAX UNIT

VIL Low-level input vo ltage 13.0V 0.9 V

5.5V 1.65

VIH High-level input voltage 13.0V 2.1 V

5.5V 3.85

IIN Input leakage current VIN = VDD or VSS 5.5V -1 1µA

VOL Low-level output voltage 3IOL = 100µA3.0V 0.25 V

4.5V 0.25

VOH High-level output voltage 3IOH = -100µA3.0V 2.75 V

4.5V 4.25

IOS Short-circuit output current 2 ,4 VO = VDD and VSS 3.0V -100 100 mA

5.5V -200 200

IOL Low level output current9VIN = VDD or VSS

VOL = 0.4V

3.0V 6mA

5.5V 8

IOH High level output current9VIN = VDD or VSS

VOH = VDD-0.4V

3.0V -6 mA

5.5V -8

Ptotal Power dissipatio n 2, 8 CL = 50pF 5.5V

3.0V

1.9

0.76 mW/

MHz

IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 µA

CIN Input capacitance 5ƒ = 1MHz 0V 15 pF

COUT Output capacitance 5 ƒ = 1MHz 0V 15 pF

AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E2

(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)

Notes:

1. Maximum allowable relative shift equals 50mV.

2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.

3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested.

SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT

tPHL1 CLK to Qn CL = 30pF 3.0V & 3.6V 4 21 ns

4.5V & 5.5V 4 17

CL = 50pF 3.0V & 3.6V 4 25 ns

4.5V & 5.5V 4 21

tPLH1 CLK to Qn CL = 30pF 3.0V & 3.6V 2 18 ns

4.5V & 5.5V 2 14

CL = 50pF 3.0V & 3.6V 2 22 ns

4.5V & 5.5V 2 18

tPLH2 CLR to Qn CL = 30pF 3.0V & 3.6V 5 21 ns

4.5V & 5.5V 5 17

CL = 50pF 3.0V & 3.6V 5 25 ns

4.5V & 5.5V 5 21

fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and

5.5V 83 MHz

tSU1 Data setup time before CLK ↑CL = 50pF 3.0V, 4.5V, and

5.5V 4ns

tSU2 CLR inactive

Setup time before CLK ↑ CL = 50pF 3.0V, 4.5V, and

5.5V 4ns

tH3Data hold time after CLK ↑ CL = 50pF 3.0V, 4.5V, and

5.5V 2ns

tWMinimum pulse width

CLR low

CLK high

CLK low

CL = 50pF 3.0V, 4.5V, and

5.5V 6ns

DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E7

( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)

Notes:

1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,

as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed

to VIH(min) and VIL(max).

2. Supplied as a design limit but not guaranteed or tested.

3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz.

4. Not more than one output may be shorted at a time for maximum duration of one secon d.

5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at

frequency of 1MHz and a signal ampl itude of 50mV rms maximum.

6. Maximum allowable relative shift equals 50mV.

7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.

8. Power does not include power contribution of any T TL output sink current

9. Power dissipation specified per switching output.

10. This value is guaranteed based on characterization data, but not tested.

SYMBOL Description CONDITION VDD MIN MAX UNIT

VIL Low-level input vo ltage 13.0V 0.8 V

5.5V 0.8

VIH High-level input voltage 13.0V 2.0 V

5.5V 2.75

IIN Input leakage current VIN = VDD or VSS 5.5V -1 1µA

VOL Low-level output voltage 3IOL = 6mA 3.0V 0.4 V

IOL = 8mA 4.5V 0.4 V

VOH High-level output voltage 3IOH = -6mA 3.0V 2.4 V

IOH = -8mA 4.5V 3.15 V

IOS Short-circuit output current 2 ,4 VO = VDD and VSS 3.0V -100 100 mA

5.5V -200 200

IOL Low level output current10 VIN = VDD or VSS

VOL = 0.4V

3.0V 6mA

5.5V 8

IOH High level output current10 VIN = VDD or VSS

VOH = VDD-0.4V

3.0V -6 mA

5.5V -8

Ptotal Power dissipatio n 2 , 8, ,9 CL = 50pF 5.5V

3.0V

1.9

0.76 mW/

MHz

IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 µA

∆IDDQ Quiescent Supply Current Delta For input under test

VIN = VDD - 2.1V

For all other inputs

VIN = VDD or VSS

5.5V 1.6 mA

CIN Input capacitance 5ƒ = 1MHz 0V 15 pF

COUT Output capacitance 5 ƒ = 1MHz 0V 15 pF

AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E2

(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)

Notes:

1. Maximum allowable relative shift equals 50mV.

2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.

3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested.

SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT

tPHL1 CLK to Qn CL = 30pF 3.0V & 3.6V 4 21 ns

4.5V & 5.5V 4 17

CL = 50pF 3.0V & 3.6V 4 25 ns

4.5V & 5.5V 4 21

tPLH1 CLK to Qn CL = 30pF 3.0V & 3.6V 2 18 ns

4.5V & 5.5V 2 14

CL = 50pF 3.0V & 3.6V 2 22 ns

4.5V & 5.5V 2 18

tPLH2 CLR to Qn CL = 30pF 3.0V & 3.6V 5 21 ns

4.5V & 5.5V 5 17

CL = 50pF 3.0V & 3.6V 5 25 ns

4.5V & 5.5V 5 21

fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and

5.5V 83 MHz

tSU1 Data setup time before CLK ↑CL = 50pF 3.0V, 4.5V, and

5.5V 4ns

tSU2 CLR inactive

Setup time before CLK ↑ CL = 50pF 3.0V, 4.5V, and

5.5V 4ns

tH3Data hold time after CLK ↑ CL = 50pF 3.0V, 4.5V, and

5.5V 2ns

tWMinimum pulse width

CLR low

CLK high

CLK low

CL = 50pF 3.0V, 4.5V, and

5.5V 6ns

Packaging

Ordering Information UT54ACS164E/UT54ACTS164E

I/O Type:

ACS = CMOS compatible I/O level

ACTS = TTL compatible I/O level

Part Number:

164E = 8-bit Shift Registers

Package Type:

U = 14-lead ceramic bottom-brazed dual-in-line Flatpack

Screen ing: (Note 3)

C = Military Temperature Range (-55

C to +125

Lead Finish: (Notes 1 & 2)

A = Solder

C = Gold

X = Optional

UT54 *** ****

***

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices have 48 hours of burn-in and are test at -55

room temperature, and 125

C. Radiation characterisitics are neither tested nor guaranteed and may not be specified.

UT54ACS164E/UTACTs164E: SMD

Drawing Number:

96556 = UT54ACS164E

96557 = UT54ACTS164E

Device Type:

02 = TID per MIL-STD-883 TM1019 Condition B

Package Type:

X = 14-lead ceramic bottom-brazed dual-in-line Flatpack

Lead Finish: (Notes 1 & 2)

A = Solder

C = Gold

X = Optional

5962 ***** ** * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. Total dose radiation must be specified when ordering. QML V is not available without radiation testing.

Total Dose: (Note 3 and 4)

R = 1E5 rads(Si)

F = 3E5 rads(Si)

G = 5E5 rads(Si)

H = 1E6 rads(Si)

03 = TID per MIL-STD-883 TM1019 Condition A

Class Designator:

Q = QML Class Q

V = QML Class V

4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with

MIL-STD-883 Test Method 1019 Condition B. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si),

3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.

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