SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
1.65-V to 5.5-V VCC Operation
D
Useful for Both Analog and Digital
Applications
D
Specified Break-Before-Make Switching
D
Rail-to-Rail Signal Handling
D
High Degree of Linearity
D
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
D
Low On-State Resistance, Typically ≈6 Ω
(VCC = 4.5 V)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes
of up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
–40 C to 85 C
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Tape and reel
SN74LVC1G3157YEPR
_ _ _C5_
–40
°
C to 85
°
C
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel
SN74LVC1G3157YZPR
_ _ _C5_
SOT (SOT-23) – DBV Tape and reel SN74LVC1G3157DBVR CC5_
SOT (SC-70) – DCK Tape and reel SN74LVC1G3157DCKR C5_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, •= Pb-free).
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
B2
GND
B1
S
VCC
A
3
2
1
4
5
6
B1
GND
B2
A
VCC
S
YEP OR YZP PACKAGE
(BOTTOM VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
CONTROL
INPUT
ON
INPUT
S
ON
CHANNEL
L B1
H B2
logic diagram (positive logic)
A
B2
B1
1
3
4
S6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, VIN (see Notes 1 and 2) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VI/O (see Notes 1, 2, 3, and 4) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, IIK (VIN < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state switch current, II/O (VI/O = 0 to VCC) (see Note 5) ±128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 6): DBV package 165°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 259°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 123°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
5. II, IO, IA, and IBn are used to denote specific conditions for II/O.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 7)
MIN MAX UNIT
VCC 1.65 5.5 V
VI/O 0 VCC V
VIN 0 5.5 V
VIH
High-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC × 0.75
V
VIH
High-level input voltage, control input
VCC = 2.3 V to 5.5 V VCC × 0.7
V
VIL
Low-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC ×0.25
V
VIL
Low-level input voltage, control input
VCC = 2.3 V to 5.5 V VCC ×0.3
V
t/ v
Input transition rise/fall time
VCC = 1.65 V to 1.95 V 20
ns/V
∆t/∆v
Input transition rise/fall time
VCC = 2.3 V to 2.7 V 20
ns/V
∆t/∆v
Input transition rise/fall time
VCC = 3 V to 3.6 V 10
ns/V
VCC = 4.5 V to 5.5 V 10
TA–40 85 °C
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
r
On-state switch resistance‡
See
VI = 0 V IO= 4 mA
1.65 V
11 20
r
On-state switch resistance‡
See
VI = 1.65 V IO = –4 mA
1.65 V
15 50
r
On-state switch resistance‡
See
VI = 0 V IO = 8 mA
2.3 V
8 12
r
On-state switch resistance‡
See
VI = 2.3 V IO = –8 mA
2.3 V
11 30
ron
On-state switch resistance‡
See
Figures 1 and 2
VI = 0 V IO = 24 mA
3 V
7 9 Ω
on
Figures 1 and 2
VI = 3 V IO = –24 mA
3 V
9 20
VI = 0 V IO = 30 mA
4.5 V
6 7
VI = 2.4 V IO = –30 mA
4.5 V
7 12
VI = 4.5 V IO = –30 mA 7 15
r
On-state switch resistance
0 V V
IA = –4 mA 1.65 V 140
rrange
On-state switch resistance
‡§
0
≤
VBn
≤
VCC
IA = –8 mA 2.3 V 45
Ω
rrange
On-state switch resistance
over signal range
‡§
0 VBn VCC
(see Figures 1 and 2) IA = –24 mA 3 V 18
Ω
IA = –30 mA 4.5 V 10
r
Difference of on-state
See Figure 1
VBn = 1.15 V IA = –4 mA 1.65 V 0.5
∆ron
Difference of on-state ‡¶#
See Figure 1
VBn = 1.6V IA = –8 mA 2.3 V 0.1
Ω
∆ron
Difference of on-state
resistance between switches
‡¶#
See Figure 1
VBn = 2.1 V IA = –24 mA 3 V 0.1
Ω
VBn = 3.15 V IA = –30 mA 4.5 V 0.1
r
ON resistance flatness‡¶||
0 V V
IA = –4 mA 1.65 V 110
ron(flat)
ON resistance flatness‡¶||
0 ≤VBn ≤VCC
IA = –8 mA 2.3 V 26
Ω
ron(flat)
ON resistance flatness‡¶||
0 ≤VBn ≤VCC
IA = –24 mA 3 V 9
Ω
IA = –30 mA 4.5 V 4
Ioff
k
Off-state switch leakage current
0 ≤VI, VO ≤VCC, (see Figure 3)
1.65 V
±1
µA
I
off
k
Off-state switch leakage current
0 ≤VI, VO ≤VCC, (see Figure 3)
1.65 V
to 5.5 V ±0.05 ±1†µ
A
IS(on)
On-state switch leakage current
VI = VCC or GND,
5.5 V
±1
µA
IS(on)
On-state switch leakage current
VI = VCC or GND,
VO = Open (see Figure 4)
5.5 V
±0.1†µ
A
IIN
Control input current
0 ≤VIN ≤VCC
0 V to
±1
µA
IIN
Control input current
0 ≤VIN ≤VCC
0 V to
5.5 V ±0.05 ±1†µ
A
ICC Supply current VIN = VCC or GND 5.5 V 1 10 µA
∆ICC Supply-current change VIN = VCC – 0.6 V 5.5 V 500 µA
Cin Control input
capacitance S5 V 2.7 pF
Cio(off) Switch input/output
capacitance Bn 5 V 5.2 pF
Cio(on)
Switch input/output
capacitance
Bn
5 V
17.3
pF
Cio(on)
Switch input/output
capacitance A
5 V
17.3
pF
†TA = 25°C
‡Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of the
voltages on the two (A or B) ports.
§Specified by design
¶∆ron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels.
#This parameter is characterized, but not tested in production.
|| Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of conditions.
k
Ioff is the same as IS(off) (off-state switch leakage current).
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog switch characteristics, TA = 25°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS VCC TYP UNIT
Frequency response
A or Bn
Bn or A
R = 50 ,
1.65 V 300
MHz
Frequency response
†
A or Bn
Bn or A
RL = 50 Ω,
fin = sine wave
2.3 V 300
MHz
Frequency response
(switch on)
†
A or Bn
Bn or A
fin = sine wave
(see Figure 6)
3 V 300
MHz
(see Figure 6)
4.5 V 300
B1 or B2
B2 or B1
R = 50 ,
1.65 V –54
dB
Crosstalk
B1 or B2
B2 or B1
RL = 50 Ω,
fin = 10 MHz (sine wave)
2.3 V –54
dB
Crosstalk
(between switches)‡
B1 or B2
B2 or B1
fin = 10 MHz (sine wave)
(see Figure 7)
3 V –54
dB
(see Figure 7)
4.5 V –54
Feed-through attenuation
A or Bn
Bn or A
C = 5 pF, R = 50 ,
1.65 V –57
dB
Feed-through attenuation
‡
A or Bn
Bn or A
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
2.3 V –57
dB
Feed-through attenuation
(switch off)
‡
A or Bn
Bn or A
fin = 10 MHz (sine wave)
(see Figure 8)
3 V –57
dB
(see Figure 8)
4.5 V –57
Charge injection§
S
A
CL = 0.1 nF, RL = 1 M
Ω
,
3.3 V 3
pC
Charge injection§
S
A
CL = 0.1 nF, RL = 1 M ,
(see Figure 9) 5 V 7
pC
Total harmonic distortion
A or Bn
Bn or A
VI = 0.5 V p-p, RL = 600 Ω,
1.65 V 0.1
%
Total harmonic distortion
A or Bn
Bn or A
VI = 0.5 V p-p, RL = 600 Ω,
f
in
= 600 Hz to 20 kHz 2.3 V 0.025
%
Total harmonic distortion
A or Bn
Bn or A
fin = 600 Hz to 20 kHz
(sine wave)
(see Figure 10)
3 V 0.015
%
(see Figure 10)
4.5 V 0.01
†Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
‡Adjust fin voltage to obtain 0 dBm at input.
§Specified by design
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 5 and 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
±0.15 V VCC = 2.5 V
±0.2 V VCC = 3.3 V
±0.3 V VCC = 5 V
±0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd¶A or Bn Bn or A 2 1.2 0.8 0.3 ns
ten#
S
Bn
7 24 3.5 14 2.5 7.6 1.7 5.7
ns
tdis||
S
Bn
3 13 2 7.5 1.5 5.3 0.8 3.8
ns
tB-M
k
0.5 0.5 0.5 0.5 ns
¶tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and the
specified load capacitance when driven by an ideal voltage source (zero output impedance).
#ten is the slower of tPZL or tPZH.
|| tdis is the slower of tPLZ or tPHZ.
k
Specified by design
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
VIL or VIH
VO
VI – VO
V
IO
VI = VCC or GND
ron
+Ť
VI
*
VO
IO
Ť
W
Figure 1. On-State Resistance Test Circuit
0
20
40
60
80
100
120
012345
on
r
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V VCC = 4.5 V
VI – V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
VIL or VIH
VO
VIA
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
VIL or VIH
VO
VIA
VO = Open
VI = VCC or GND
Figure 4. On-State Switch Leakage-Current Test Circuit
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
W aveform 1
S1 at VLOAD
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH – V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
500 Ω
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
VLOAD CL
50 pF
50 pF
50 pF
50 pF
0.3 V
0.3 V
0.3 V
0.3 V
V∆
VCC
VCC
VCC
VCC
VI
VCC/2
VCC/2
VCC/2
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 5. Load Circuit and Voltage Waveforms
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
fin 50 ΩRL = 50 Ω
RL
VIL or VIH
VO
Figure 6. Frequency Response (Switch On)
B1
B2
S
A
VCC
VCC
GND
50 Ω
VIL or VIH VB1
fin
VB2 Analyzer
S
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
RL = 50 Ω
RL
Figure 7. Crosstalk (Between Switches)
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
fin 50 Ω
RL = 50 Ω
RL
Analyzer
VIL or VIH
Figure 8. Feed Through
B1
B2
RL
S
A
VOUT
CLRL/CL = 1 MΩ/100 pF
VOUT
VCC
VCC
SW
1
2
RGEN
GND
LOGIC
INPUT
LOGIC
INPUT OFF OFFON
Q = (∆VOUT) (CL)
∆VOUT
VGE
Figure 9. Charge-Injection Test
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
fin 600 Ω
VIL or VIH
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
VCC = 4.50 V, VI = 4.0 VP-P
VO
10 µF
CL
50 pF
RL
10 kΩ
VCC/2
Figure 10. Total Harmonic Distortion
VI = VCC/2
B1
B2
RL
S
A
VO
CLRL/CL = 50 Ω/35 pF
0.9 x VO
VO
t
D
VS
V
CC
VCC
GND
Figure 11. Break-Before-Make Internal Timing
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE
0,15
Gage Plane
0,10
M
0,10
0,65
0°–8°0,46
0,26
0,13 NOM
4093553-3/D 01/02
0,15
0,30
1,40
1,10 2,40
1,80
46
2,15
1,85
1 3
1,10
0,80 0,10
0,00
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
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